CXP80600A

Sony Corporation

CMOS 8-bit Single Chip Microcomputer

Manufacturer: Sony Corporation

Document: 24 Pages / 1Mb

Request Quote Download Datasheet Read online HTML view

More from Sony Corporation Browse C parts

Online Datasheet

Read CXP80600A online.

CXP80624A SONY | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 24

Technical content

FEEDER EREEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEDE? TEE’ SONY. CXP80620A/80624A | — CMOS 8-bit Single Chip Microcomputer Description i The CXP80620A/80624A is a CMOS 68-bit 100 pin QFP (Plastic) 100 pin VOFP (Plastic) j microcomputer which consists of A/D converter, serial interface (2ch independently), timer/counter, time base timer, vector interruption, high precision timing pattern ve — ' generation circuit, PWM generator, general purpose Z 2 Pees . prescaler, PWM for tuner, VCR vertical syne separation ee : ~<a Seen circuit and the measuring circuit which measure signals Sirs oe er of capstan FG and drum FG/PG and ‘other servo a | systems, as well as basic configurations fike 8-bit CPU, | ROM, RAM and I/O port. They are integrated into a | single chip. Lo . 1 Also CXP80620A/80624A provides power on reset : function, sleep/stop function which enables to lower power consumption. Features . | A wide instruction set (213 instructions) which cover various types of data. | — 16-bit arithmetic instruction/multiplication and division instructions/boolean bit operation instruction { ¢ Minimum instruction cycle During operation 333ns/12MHz | © Incorporated ROM capacity 20Kbytes (CXPB0620A) : 24Kbytes (CXP80624A) Incorporated RAM capacity 800bytes i Peripheral function — A/D converter 8-bit, 12-channel, successive approximation system {Conversion time: 26.7 j1s/12MHz) . — Serial I/O with auto transfer mode —_ Incorporated 8-bit and 8-stage FIFO for data i (1 to 8 bytes auto transfer) 2-channel independently © . | — Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer — High precision timing pattern generator PPG 19 pins 32-stage programmable H * RTG 5 pins 2-channel — PWMiIDA gate output 12-bit, 2-channel (Repetitive frequency 46kHz/12MHz) . — Servo input control Capstan FG, Drum FG/PG, CTL input — VSYNC separator — FRC capture unit Incorporated 26-bit and 8-stage FIFO — PWM output for tuner 14-bit — General purpose prescaler 10-bit (System clock asynchronous) @ Interruption 17 factors, 14 vectors, multi-interruption possible © Standby mode SLEEP/STOP : . © Package 100-pin plastic QFP/VQFP . © Piggyback/evaluation chip CXP80600A . | i Structure | Silicon gate CMOS IC { Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. at €92220-_ST | MH 8382383 0017549 573 ml ;

i Pair Gy | Pre fybibior, | ze ¢ PSS fo bog | viel el es cteleticfst Gf i sf | Eee ff fn ole ro oe fn] or] | OOO oF So UoGoCo TU: | we Bg § ; tS 33 suk H ! md 35 Ee 18 ' cera $y BF z a 335 [=P een wn ot \\ i es ' ' 1 | 8 = I : 1 | 58 * 2 fs veo} L R= i | i QUOT OM OW OE TS RUE i | : ° ' ® H H i x H i H H -2— | | @® 43423483 0017550 2oT |

SONY CXP80620A/806244 | a SSSeSeeSeeSSeSSSSSSSSSSsSSSSSSssSseSeeeeeeeeeeeeEeEeeee AREA \\ Pin Configuration 1 (Top View) 100 pin QFP Package Note 1) NC (Pin 90) is always connected to Voo. > 2) Vss (Pins 41 and 88) are bath connected to GND. g F S$ |z ELorunsger a So90 oo SOoO9 Zz SIE Ie { BRP FRRR FF ELeEPE IEE EL TODMEIEIENEDEDE NEDEDEDEEDNENENENENE)) | PBS/PPO130e—(4) G00 P16 / Sot i PB4/PPOIZ0e-—{2) GSO PI7/S11 | PB3/PPO!10+—{3) Gey-—o PEOs INTO | PB2/PPOIO0+—{4) Q7}-—OPEIVEC/INT2 | PBI/PPO9O+—{5) (?6}-—-0 PE2/PWMO | PBO/ PPOS O+—{6) (7s)—+0 PE3/PWM1 i ~ PC7/ RTOT O+—+{7) (4)—+0 PE4/DAAO | PC6/RTO6O+—+(8) (73)—+0 Pes/DAAt | PCS/ RTOS Oo—e(9) @2}——+0 PE6/DABO | PC4/RTO4 On—a(10) @1)—*0 PE7/ DAB! | PC3/RTOS O+—+(11) (fo }-—0 PGO/ CFG PC2/PPO1BO+—+(/2) €3+— PG 1/0FS PC1/ PPOI7 0+—=(13) €8)+—0 Pe2/DPG | PCO/ PPOIGO+—(14) @t}-—0 Ps /PECTL / Pu7O+—>(5) (G6-—0 PG4/ syNcO | PUG O+—>416) G5}-—0 P6s/syNct j Pus O—+(7) €4}-—0 Pcé/EXI0 | Pu4 O+—+(18) @3)s—0 PG7/ EXIt | PU3 O+—o(49) 2—©0 ANO i PU2 0-20) Go ant i PJ} O++) o}+—0 Anz i P10 OG) @8)-—o ANS ! PD7 O+—+63) 68)-—0 PFO /ANa : PO6O+—+Za) 61)}+—0 PF1/ ANS | P04 O+ +5) 6s}—0 PF3/aN7 PD3 O+—+Q7) 64)—0 Avoo | P020+—+(a) €3)\\—0 avaer ; PD10+—+(29) G2)-—0 avas i P000+—+40) 61-0 PF4/ane BIIEHEHNEYENDES)EOE NEIEICIEI GOED ESCDNEO) ; °000000000000 fe) 0° j kenenas 3 = PEPLPZEPIR S228 SSE 52 2 | “ r3e8 | fae 1 -3- Mi 43623483 0017551 loeb

Pin Configuration 2 (Top View) 100 pin VOFP Package | Note 1) NC (Pin 88) is always connected to Voo. | 2) Vss (Pins 39 and 86) are both connected to GND. i Lo. z4 = Ie EEEEREEEEEEE ee: 5S efecscss ec Ssh CODGOCE OCOOS DE OOOOCVC WD RO | PBS/PPONO {1 @ © PEV/EC s INTE . Pa2/PPOIO © (2) (74) PEZ/PWMO PBI/PPO9 © (3) (3) © PES/PwMI PBO/PPOS © (4) G3 © PE4/0AA0 PcrsRtoT O (3) Gi © PES/DAAL } PCG/RTO6O (6) Go) © PEG/DABO 4 PCS/RTOS © (x) 6 © PET/DAB! PCAs ATOS © (8) €8) © PGOs CEG PC3/ RTOS O {3) @ © PG1/0FG : ec2sPpore © Cc) ) © Pozv0rc | PCI/PPONT © Gy) 6 © PGS/PECTL | PCO/PROIG © (2) iC) © pca/synco i Put £13) 3} © PGS/SYNCI i Pus O (34) © © PGE/EXIO | pas Ose) -<—© Porvexit puso (9) ©) © AKO | Pu3 0 ©) G9) © ANI ! Pizo Go) GS) O AN2 : puto ie) G—o ans Ps0 0 Go os © PFO/ANA P06 © 23 cc) © PF2/ANG Pos 0 £3 6 © PFS/ANT + Pos Oe —> 29) Ge © AVOD POS O @) Gi) © AVRcr i DIOO DOOD OVO DEVIN DOODID . | i —4- | i ME 8382383 0017552 Oboe |

SONY CxPBOB204/80824A | Pin Description ; [symbo |W nC (Port A) | 8-bit output port. Data is | PAOIPPOO | Cutpull | gated with PPO contents : PA7/PPO7 | Output by OR-gate and they are i output. 4 (8 pins) Hq (Port B) ; Programmable pattern generator (PPG) output. | 8-bit output port. Data is Functions as high precision real time pulse output PBOIPPOB | Outpul | gated with PPO contents | port. by OR-gate and they are | (19 pins) : PB7/PPO15 | Output output (8 pins) ! PCO/PPO16 | VO/ (Port C) to Realtime | 8-bit input/output port, PC2/PPO18 | Output enables to specity Data gated vith PPO ta or | PC3/RTOS | WOH RTO contents by OR-gate | Real time pulse generator (RTG) output. Functions to Real time and they are output. as high precision real time pulse output port. i PC7/RTO7 | Output (8 piris) (5 pins) (Port D) H PDO to PD7 8-bit input/output port. Enable to specify input/output by 4-bit unit. | Enables to drive 12mA sinc current. | (8 pins) | Input pin to request external interruption, PEOANTO jim | Active when falling edge. Ext , Input pin to request NTS fernal event input pin for | external interruption. | PELVEC/INT2 (Port) timer/counter. Active when falling | edge, 8-bit port. Lower 2 bits are PE2/PWMO input pins and upper 6 bits | PWM output pins. « [ PEADAAO eps) PES/DAA1 DA gate pulse output pins. tan | ANOtoAN3 | Input | Analog input pins to A/D converter. (12 pins) : PFO/ANS to Input (Port F) PFS/AN7 Lower 4 bits are Input port and upper 4 bits are output port. PF4/ANB Lower 4 bits also serve as standby release input pin. ‘ to (8 pins) : PF7/AN11 [SCKO [VO _| Serial clock (CHO) input/output pin. | [soo | Output | Seria data (CHO) output pin, | -5— | M@® 8342383 0017553 TTT

SONY CXPB0620A“80624A | een | - | Saba [0 ite [sio | input__—_| Serial data (CHO) input pin, [e558 [rp | Seria chip eet CHO) mpi | PGOICFG : Capstan FG input pin. | PGi/DFG Drum FG Input pin. rears [rea | Drum Pa neu ps B-bit Input port. | pewsynco [input | grins) Composite syne signal input pin ; resismici [mew | | External input pin to FRC capture unit. i (Port H) PHOtoPH7 | Output 8-bit output port ; Medium withstand voltage (12V) and high current (12mA), N-ch open : drain output, (8 pins) : External clock Input pin of generat purpose prescaler. |Pueo | YO / Output Genera! purpose prescaler output pin. ‘ort VO/ Output | Lower 1 bits Input port and upper 7 bits | Timer/counter output pin. are input/output port. {duty=50%) Input/output port can be specified by bit unit | input pin to request extemal interruption. PLANT? VO H Input (8 pins). Active when falling edge. | VO1VO Serial clock (CH1) Inputfoutput pin. PIG/SO1 | 40 / Output Serial data (CH1) output pin. PI7/SI1 WO / Input Serial data (CH1) input pin. j (Port J) PUO to PU7 8-bit input /output port. Function as standby release input can be specified by bit unit. | Input/output can be specified by bit unit. | cn EXTAL Connecting pln of crystal oscillator for system clock. When supplying the extemal clock, [xtaL [Ou input the external clock to EXTAL pin and input opposite phase clock to XTAL pin, ‘System reset pin of active “L" level. RST pin Is input/output pin, which output “L” level by | incorporated power on reset functlon when power on. (Mask option) | [me _| input___| Microprocessor mode input pin, Always connect to GND. [avo | Positive power supply pin of A/D converter. | [avaer | Input | Reference voltage ipl pin of AD converter. | [aves || enn at i comonr: [vss |__| GND pin. Connect both Vss pins to GND. i , | -—6- { M™ 8382383 0017554 935

SONY CKPBOB20A/ 808244, | Input/Output Circult Formats for Pins i a cd , | PAO/PPOO . to [| OPE | PAZ/PPO7 PPO date > i LT. i ss p | to Port 8 | PB7/PPO15 os ftom teh | itput becomes active from hi i Date bus <I impedance by data writing to port register. | RD ! 16 pins } PCOIPPOI6 i» : to PPO, RTO data {| | PCS/RTOS ~ ee Pron | ea PCTIATOT Por © on a | ver vi) [LF] | im om oe CE V | RO (Port C) : 8 pins reo | PDO tq © High current | PD7 Hi-Z : CH] \\ every 4 bits) Le} PDO to 3' { Data bus <<" Che (Foe to 2) V ! RD (Port D) | 8 pins i i -1- | : i MH 6382383 0017555 87] |

SONY CXPBOE20A/806244 | PEO/INTO . | PEVECINTE [_ H1EH> | > Data bus ; 2pins RD (Port E) ( rere] | DA gate output | : or PWM output D: | PEQ/PWMO HiZ control in > PE3/PWM1 i ke " ; PE4/DAAO Ei, [| 1 PES/DAAI Port/DA output I select Data bus <} i 4pins RD (Port £) | DA gate output: D: i HiZ control ie t mn [rene a | > PE7/IDABY nt & Hlevel Port/DA output — select | Data bus -<“} | 2 pins RD (Port £) | . \\ ano Input multiplexer | ANS A/D converter 4pins Inout maltistexer | PFO/AN4 | HH es A/D converter | to PF3/AN7 \\7 ‘ > Data bus | 4pins RO (Port F) ME 8382383 0017556 708 a |

SONY ©xPB0620A/806244 | a Port | function 1 select Plt ++ From general purpose prescaler D: | PI/PO ( Pi2-~ From 14-bit RWM | PI2PWM PI + From. timer“counter | | | i> & | = H Date bus +<] Ht Y | 3 pins RD (Port 1) [ror aaa | ia = i PI7/Sit oH Data bus =<] <4,4 Lr] | RD (Port |) {| | - Schmitt input A P14-- To interruption circuit } 2 pins PiT--To sei CHT | Port | funetion / | | Sea > PISSCKT = fi > a | to Pass Para | HL | Hz | ; = i ‘4G: Note) \\7/ ows oo CE | sco 2pins RD (Port 1) To serial CHI | reo | ro + | PUT @= | Data bus <<} HS | Le] 5 t7< (or J) ' 8 pins Standby release Edge detection — 10 | i . MM 8382383 0017558 580 mm |

*1) AVoo and Voo should be set to a same voltage. i *2) Normal input port (each pin of PC, PD, PEO to PE1, PFO to PF3, PG, Pl, PJ and PK), MP pin *3) Each pin of C50, SIO, SCKO, AST, PEO/INTO, PE1/EC/INT2, PG (For PG4 and PGS, when CMOS schmitt input is selected with mask option), PI4/INT1, PIS/SCK7 and PI7/SI1. * 4) Each pin of PG4 and PGS (When TTL schmitt input is selected with mask option) | *5) It specifies only when the external clock is Input, |

Electrical Characteristics

DC characteristics (Ta= — 20 to +75°C , Vss=0V) | [tem [Symbol] Pa | Condon [tin | Typ. | Max nt) High level Von | PAto PD, PE2to PE7, | Voo=4.5V, lous — 0.5mA [so] [ [vi | output voltage PF4, to PF7, PH (VoL va 5 [3s] [| Low level 1 Lowe ce | vo [FST#* (oon) | VoondsV.tou3ema | |__| 06 |v | PD, PH Voo=4.5V,toixi20mA_ | | | 15 | vi | ca Voo=55V,VeessV | 05) | 40 [ual Inputeurent he _| [Voocsav,vazoav[-05|__|-a0|ua] Pn _[AST=® | voonssv,vanoav [-15[ [00] wa} PA to PG, Pl to PK: MP, | $00, RST *? moe | Open drain output | leakage current PH Voo=5.5V A (N-CH Tr OFF in Vor=12V Le | state) | Crystal oscillation mA (C1=C2=15pF) of 12MHz | Voo=5V + 10%*4 | Supply current*3_ | !0081 | Vpp SLEEP mode Ww mA | “ STOP mode 10 . / Clock 1MHz | ‘ Other than Vo, Vss, | Input capacity Cw eee OV other than the i AVoo, AVss pins measured pins *1) RST pin specifies only when the power on reset circuit has been selected with mask option. *2) AST pin specifies the Input current when the pull-up resistance is selected, and specifies leakage current when non-resistance Is selected. ! * 3) When entire output pins are open. , *4) When setting upper 2 bits (CPU clock selection) of clock contro! register CLC (address: OOFEx) to “00” and | operating In high speed mode (1/2 dividing clock). | -139- i i M™ 6382383 0017561 075 a

SONY CXPBOB20A/ 206264 | AC Characteristics : (1) Clock timing (Ta= — 20 to +75°C , Voo=4.5 to 5.5V, Vss=0V) : System clock frequency | | ate Fig. 1, Fig. 2 | + | 12 MHz | | as | | Syste lock input pulse width 37.5 ‘System clock input rising and falling (External clock drive) 4 times | serene (5 ie ee |e) =| Event count clock input rising and | falling times i | * tsys indicates three values according to the contents of the clock control register (address; OOFEx) upper 2 bits | (CPU clock selection), | . tsys [ns] =2000/c (Upper 2-bit="00"), 4000/fc (Upper 2-bit="01"), 16000/c (Upper 2-bit="11") | : | : Fig. 1 Clock timing . : } fe | Von - 0.4V | i EXTAL i oav I ! } : | 1 ber tor te ter | | Fig. 2 Clock applying condition | Crystal oscillation | Ceramic oscillation External clock . m PSe ° ‘= mx A, 74H004 @ | ! Flg.3 Event count clock timing | 0.8Vo0 | 1x04 0.2Vo0. i ‘ten ter tel tER i i i i —4- i | M@® =8382383 00175b2 TO] a |

—— SSSSSSsSSSSSSSSSSSSSSSSSSSSSSSSs j SONY : ‘CXPBOS20A/B06244 | Dee eee | (2) Serial transfer (CHO) (Ta= — 20 to +75°C , Voo=4.5 to 5.5V, Vss=0V) | [tem [Symbol Fin [Condon [Min [Max Unt) | CSO | + SCKO delay time | tocsx | SCKG|Chipsetecttranster | =| tsys+200_| ns | ; i mode CSE | =SObieayine [wows | SO] a C50 | +500 foaing deayine_[tesor | soo | Cgselettanster | —————Preyasz00 ns] CSO Nigh ve wi Lema [des] [inpamode | Bayesooo [re] SCKO cycle time tkey — | SCKO high and low level widths sos eee teyset09_[ tas} aooore-so [dns] SiO input setup time SCKOinputmode | 100 | ns | eee [ScKGoupwmose [200 | de] Sion bed ine | SCKinput made | yesa60_| [na] Soma eats [ScKOoupumede | 100 | |r| | SCKOinputmode | tsysx200 | SCKO | +SO00 delay time txso SO pak mode ys+200 [os | SRGouputmese || _100 [re] | Note 1) tsys indicates three values according to the contents of the clock control register (address; OOFEn) \\ upper 2 bits (CPU clock selection). tsys {ns] =2000/fc (Upper 2-bit="00"), 4000/fc (Upper 2-bit="01"), 16000/c (Upper 2-bit="11") | 2) The Load of SCKO output mode and SOO output delay time is SOpF-+1TTL. | i —-15- | @™ 6382383 0017563 948 me |

SONY CXPBO620A/ 808244 | BONN Fig. 4 Serlal transfer CHO timing ; _ | 0.8Vpp | = | . 0.2Vo0 | axer | tDWCsK tocsKr | |_| | Cy 0.800 SKS - 4 ; 0.2Vb0 | ts! ! 0.8Vo0 | sto ( ) --- 0.2Ve0 i toeso ixso tocsor | 0.8Vo0 i soo { { 0.2V00 i “- | i —16— | ME 8342383 0017564 844 mm

SONY CXPBOS208/806244 | Serial transfer (CH1} (SIO mode) (Ta= — 20 to +75°C , Von=4.5 to 5.5V, Vss=0V) | [tem |Symbol]_Pin | Condon [win | Moc [um] ayo [| i 1 SER high and ow [inputmode | teyeot00_ |__| ve | iovel ws [cuoutmode | Soeone = 80 ne | SI1 input setup time ‘SCKi input mode ee ee (against SCK? +) SCKioutputmode | 200 [ns | i 2h puto fire [SCkTinputmode | wyeea00_| [rs] (against SRT [ScRFouputmeae [100 | [wm] SORT | =501 deny ScKTnputmode | | wee fs] time [sce ouputmedes |_| 00 fm] | Note 1) tsys indicates three values according to the contents of the clock control register (address; OOFEx) | upper 2 bits (CPU clock selection). | tsys [ns] =2000 /fc (Upper 2-bit="00"), 4000/fc (Upper 2-bit="01"), 16000/fc (Upper 2-bits"11"). 2) The Load of SCKT output mode and SO1 output delay time is 50pF +1T TL. ' i Flg.5 Serial transfer CH1 timing (SIO mode) i . wxcy ! ; O8Vo0 | : i 0.2Vo0 | ts | . | 0.8V00 | a {|} rout cata 0.2V0 | SO | 0.8Vo00 sol | Output data | 0.2Ve0 | -W7w- | MM 8382383 0017565 710 |

a SONY CXPB0B20A/80624A | Serlal transfer (CH1) (Special mode) (Ta=-20 to +75°C , Vop=4.5 to 5.5V, Vss=0V) i siasem om [fom || | Siidatasewuptime [uw [sr [| 2 | Ts | [sitdsiahoidtime [wo [sn] | 2 || | ss | | Note 1) tucy specifies only serlal mode register (CH1) (SIOM1: Address 01FAx) lower 2 bits (SO1 clock selection) has been set at 104 ps. 2) The Load of SO1 pin is 50pF +1TTL. | : Fig.6 Serlal transfer CH1 timing (Special mode) | an in| | ” ones ome si input “pOSveo | data bit F O.2V00 | ; | ~~ | . j M@™@ 6382343 O0175bb 657 |

ee | SONY CXPBO620A,/B082¢A — Cee (3) A/D converter characteristics (Ta= — 20 to +75 °C, Voo=AVpp=4.5 to 5.5V, AVREF=4.0V to AVop, Vss=AVss=0V) [tem [Symbol] Pin | Coneton | Min. | Typ. | Max [Unt] [ Resotuton Ts | [nearer | | raagy Lt | Zerotansiionvotage | Va*™] | VoosAVonns.ov [-10 | 90] 70 [av] FallsealeWanstion votage [Vn== |__| Ws#eAVes=0V ferwrentne Pew [Peers Sampling time [iw [OP tateoees Ps | [Referenceinpuivatage —[Vner | Aver |_| Ave-o5| | Wem fv] [ier | [Operaingmeds |_| 08 | 70 [ma] AVnrer current AVAEF | SLEEP mode | STOP mode HA i Fig. 7. Definitions of A/D converter terms | FFH . Z i *1) Vz: Indicates the value that digital conversion value . § } changes from 00x to 01H and vice versa. g { *2) Vet: Indicates the value that digital conversion vatue | 5 | . changes from FEx to FF and vice versa. | i *3) The value of favc is as follows by selecting ADC i 3 i operation clock (MSC: Address O1FFi bit 0). i Linearity error i When PS2is selected, fanc=fc/2 : ol i When PS1 is selected, fanc=fe i OOH at Ver i Analog input —19- | : M™ 8382383 0017567 593

SONY (CXPROB20A7808264, | oe (6) General purpose prescaler {Ta=-20 to +75°C , Voo=4.5 to 5.5V, Vss-0V) | ttem Symbol [Pin [Condition |_Min. | Typ. | Max | unit J Ereralcckinpatenenay [rex [pce | S| | Eaeralsbekinoutpuiowah [twain [PK | TT External clock input rising and falling times tate | PCK | Presalr output dla tine Extemalcockinst | | 20 | too | oe | Prescaler output rising and External clock Input |_| 0 | 0 | ns | st meee [eters] Note) The Load of PO pin is S0pF. i . Fig. 11 General purpose prescaler timing :

1 Pox :

i pcK —-0.5Vo0 ff i dl 08¥e0 : 0.2V00 il | oe | trLH 7 0.8Vo0. i] ; PO 0.5V00. 44 f | t | tru th, | * (7) Others (Ta= — 20 to +75°C , Voo=4.5 to 5.5V, Vss=0V) [tem TT symbor Trin] Goneition | win, | ax. [unt | CFShpatighendiowlevelwidte [ematen [OFS |__| tyse200 | ——* ns | DFG inputigh and iow evel widths | torn ton. [DFG [| 1000ee200| | ns | DPG minimum pusewah dew [bra || 0 | fes| [OPE minimum removalime [vem [opa_[ |_| |s] | EEessneco Lawn [me [wma [ewan | [m| crimp [mom [BR | wean) ewan [fw] Note) tsys indicates three values according to the contents of the clock control register (address; OOFEnx) upper 2 bits (CPU clock selection). tsys [ns] =2000/fe (Upper 2-bit="00"), 4000/fc (Upper 2-bit="01"), 16000/fc (Upper 2-bit="11") —2-— MH 43823583 0017569 3bb

a ! SONY CXPEO620A808244 | . Fig. 12 Others timing ‘tCrH tere ora 0.800 | 0.2Vo0 | tore tore 0.8Vo0 ' | os \\ 0.2Vo0 O.8Vo0 | PG ; | tema ten. | PECTE 0.8Vo0 0.2Vo0 | ton ten i ExIO 0.8Vo0 | em 0.2¥e0 | i | ~—2- | | M® =43423483 0017570 066 |

SONY ‘CXPBOB20A/806248 | mo ee Supplement . | Fig. 13 Recommended oscillation circuit MURATA MFG ot T, Manufacturer Frequency | cs, Ce jo 7m range (MHz) 1, Cz (pF) RIVER ELETEC. con. [rene |e |e KINSEKILTO._[AGAO |e | eC CITIZEN WATCH : [gon focom |e |e | Mask option table . ee | input circuit format Note) {| C-MOS schmitt TTL schmitt Note) In PG4/SYNCO pin and PG5/SYNC1 pin, the input clrcuit format can be selected to every pin. Characteristics Curve : : {po vs, Vop top vs. fe i | (to=12MHz, Ta=25°C, Typical) (Vp0=5V, Ta=25°C , Typical) ! i } 20.0[-—- 772 dividing clock | . 10.0 Lt 4 1/4 dividing clock — 20 i = 59 a 11X16 dividing clock £3 | 2 eee ee . 172 dividing clock ‘ 2 of Lee site oat : 6 oo — 1/4 dividing clock : SSeS E | ae 3 2S == 3 1/16 dividing clock J ee a a ! 5 | 2 SLEEP mode A 2 3 4 5 6 Tr 1 5 10 Voo — Power supply voltage (V) fc — System clock (MHz) . i —23- | MMH 8382383 0017571 TL4 om ;

—_— en SONY ‘CXPBO620A,/806248 | eee Package Outline Unit : mm i t 100din GFP (Plastich 4.7¢ i : 00 oss rary | ' | 9.0*f | HODOLORINDIOONOROG OD OINORD OGG | ead (4) | 138s | | . \\ | . 100pin VOFP (Plastic) | ! arse | | | || ostt os!88 . [ Hoses | im Bs) res) | i [1a save loeoj00-P= 1434-4 | 0° 10%, ‘Detsited disgram of A . Mois) Dimensions marked with ¢ dee not sichide ream revidue, —24— , This data sheet has been made from recycled paper to help protect the environment. M$ 8342383 0017572 950

Product Information

CXP80600A specifications and overview.

Summary

CMOS 8-bit Single Chip Microcomputer

Description

CMOS 8-bit Single Chip Microcomputer

Source title CXP80600A Datasheet(PDF) - Sony Corporation

Related Parts

More parts from the same family.

Browse manufacturer