CXP508L4 SONY | Alldatasheet

Document overview

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Technical content

Features

  • Instruction cycle 4µs/2MHz (2.4V to 3.5V)
  • ROM capacity 4.096 · 8 bits (CXP508L4) 6.144 · 8 bits (CXP508L6)
  • RAM capacity 400 · 4 bits (24 · 4 bits is used in combination with the LCD display memory)
  • 32 general purpose I/O ports (For 16 segment outputs)
  • LCD controller/driver (Direct drive possible) — Optical specification of 24, 20 or 16 segment outputs — 1/2, 1/3, 1/4 duty selectable through program — 1/3 bias
  • 2 external interruption input pins
  • 8-bit/4-bit variable serial I/O
  • 8-bit timer, 8bit timer/event counter and 18-bit time base timer are independently controllable
  • Arithmetic and logical operations possible between the entire RAM area, I/O area and the accumulator by means of memory mapped I/O
  • Reference to the entire ROM area is possible with the table look-up instruction
  • 2 types of power down models, sleep and stop
  • 64-pin plastic SDIP/QFP available
  • Piggy back package (CXP5080) available Structure Silicon gate CMOS IC – 1 – CXP508L4/508L6 E95108-ST CMOS 4-bit Single Chip Microcomputer Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. 64 pin SDIP (Plastic) 64 pin QFP (Plastic)

– 2 – CXP508L4/508L6 Block Diagram Accumulator Flag ALU Timer/Counter (8) Timer (8) Serial I/O (8) Interrupt control 400 × 4 bits Register Data memory Stack Data memory Program counter (13) Program memory 6144 × 8 bits (CXP508L6) 4096 × 8 bits (CXP508L4) Time base timer (18) Instruction control Clock control Port A Port B Port C Port D Port E Port F Port YPort X LCD controller/driver 4 4 4 4 1684 SEG0 to SEG15 COM0 to COM3 SEG16 to SEG23 (Common with Port E, Port F) VL VLC1 VLC2 VLC3 PX3/SI PX2/SOAPX1/SOBPX0/SCPY3/ECPY2/INT2 PY1PY0 WP INT1V DD V SS RST (Common with serial I/O) EXTAL XTAL (Enables to specify the I/O with bit unit) (Enables to specify the I/O with port unit) (Combines use of mask with segment output, optional)

– 3 – CXP508L4/508L6 Pin Configuration (Top View) VL XTAL EXTAL RST WP INT1 PY0 PY1 INT2/PY2 EC/PY3 SC/PX0 SOB/PX1 SOA/PX2 SI/PX3 PD0 PD1 PD2 PD3 PC0 PC1 PC2 PC3 PB0 PB1 PB2 PB3 PA0 PA1 PA2 PA3 NC Vss VDD VLC3 VLC2 VLC1 COM0 COM1 COM2 COM3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16/PF0 SEG17/PF1 SEG18/PF2 SEG19/PF3 SEG20/PE0 SEG21/PE1 SEG22/PE2 SEG23/PE3 20 21 22 23 24 25 26 27 28 29 30 31 32 51PY0 PY1 INT2/PY2 EC/PY3 SC/PX0 SOB/PX1 SOA/PX2 SI/PX3 PD0 PD1 PD2 PD3 PC0 PC1 PC2 PC3 PB0 PB1 PB2 PB3 PA0 PA1 PA2 PA3 Vss NC PE3/SEG23 PE2/SEG22 PE1/SEG21 PE0/SEG20PF3/SEG19 PF2/SEG18 COM3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16/PF0 SEG17/PF1 INT1 WP RST EXTAL XTAL V L VDD VLC3 VLC2 VLC1 COM0 COM1 COM2 5253545556575859606364 6162 Note) Do not make any connection to NC pin.

– 4 – CXP508L4/508L6 Absolute Maximum Ratings Item Power supply voltage LCD bias voltage Input voltage Output voltage High level output current High level total output current Low level output current Low level total output current Operating temperature Storage temperature Allowable power dissipation V DD VLC1 , VLC2 , VLC3 VIN VOUT IOH ∑ IOH IOL ∑ IOL Topr Tstg PD –0.3 to +5.0 –0.3 to +5.0*1 –0.3 to +5.0*1 –0.3 to +5.0*1 –50 –20 to +75 –55 to +150 1000 600 V V V V mA mA mA mA mW mW General purpose port* 2: per pin Entire pin total General purpose port* 2: per pin Entire pin total SDIP QFP Symbol Ratings Unit Remarks *1 VLC1 , VLC2 , VLC3 , VIN and VOUT should not exceed VDD + 0.3V. *2 The PE and PF are specified when PA to PD, PX0 to PX2, PY0, PY1 and mask option are port selected. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should better take place under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. Recommended Operating Conditions Item Power supply voltage VDD VLC1 , VLC2 , VLC3 VIH VIHS VIHEX VIL VILS VILEX Topr LCD bias voltage High level input voltage Low level input voltage Operating temperature Symbol Min. 2.4 2.0 VSS 0.7VDD 0.8VDD VDD – 0.4 –0.3 –20 3.5 3.5 V DD VDD VDD VDD + 0.3 0.3VDD 0.2VDD 0.4 +75 V V V V V V V V V Guaranteed range during operation Guaranteed data hold operation range during STOP Liquid crystal power supply voltage* Hysteresis input*2 EXTAL pin*3 Hysteresis input*2 EXTAL pin*3 Max. Unit Remarks *1 The optimum value is determined by the characteristics of the liquid crystal display element used. *2 They are the respective pins of INT1, WP, PX0, PX3, PY2, PY3 and RST. *3 Specified only during external clock input. (VSS = 0V) (Ta = –20 to +75°C, VSS = 0V)

– 5 – CXP508L4/508L6

Electrical Characteristics

DC characteristics (Ta = –20 to +75°C, VSS = 0V) Item High level output voltage VOH PA to PF*1, PX0 to PX2, PY0, PY1, V L (VOL only) VDD = 2.4V, IOH = –0.3mA*2 VDD = 2.4V, IOH = –0.5mA*2 VDD = 2.4V, IOH = –5µA*3 VDD = 2.4V, IOH = –10µA*3 VDD = 2.4V, IOL = 1.0mA VDD = 2.4V, IOL = 2.0mA VDD = 3.5V, VIH = 3.5V VDD = 3.5V, VIL= 0.4V 1.8 1.4 1.8 1.4 0.3 –0.3 –1.5 1.3 0.6 0.4 0.6 –20 –200 –1.0 1.2 V V V V V V µA µA µA mA µA kΩ kΩ mA mA µA pF V DD = 3.5V VI= 0, 3.5V VDD = 3.5V VLC1 = 2.65V VLC2 = 1.75V VLC3 = 0.88V VDD = 3.5V During external clock 1MHz operation Entire output pins open Clock 1MHz 0V other than the measured pins SLEEP mode STOP mode EXTAL * RST *5 PA to PF*6, PX0 to PX2*6, PX3 *8, PY0*7, PY1 *7, PY2*8, PY3 *8, INT1*8, WP *8, RST*5 COM0 to COM3 SEG0 to SEG15 SEG16 to SEG23*1 VDD VLC1 to VLC3, COM0 to COM3, SEG0 to SEG15, SEG16 to SEG23* Other pins than VDD , VSS VOL IIH IILE IILR IIL IIZ R COM R SEG IDD IDDSP IDDS C IN Low level output voltage Input current High impedance I/O leakage current Common output impedance Segment output impedance Current power supply Input capacitance Symbol Pin Condition Min. Typ. Max. Unit

1 The PE to PF show when the combined pins are selected as the port, and SEG16 to SEG23 show when

the combined pins are selected as the segment output. *2 It is when the respective pins of PA to PF and PX0 to PX2 select the 3-state output circuit, and PY0 and PY1 are when the inverter output circuit is selected. *3 It is when the respective pins of PA to PF, PX0 to PX2, PY0 and PY1 select the pull-up resistance. *4 It is when the crystal or ceramic oscillation circuit is selected. *5 The RST pin specifies the input current when the pull-up resistance is selected, and specifies leakage current when non-resistance is selected. *6 The respective pins of PA to PF and PX0 to PX2 specify the input current when the pull-up resistance is selected, and specify the leakage current when in the port state during the 3-state output circuit or standby is selected at high impedance. 7 The respective pins of PY0 and PY1 specify the input current when the pull-up resistance is selected, and specify the leakage current when in the port state during standby is selected at high impedance. *8 The respective pins of PX3, PY2, PY3, INT1 and WP only specify the leakage current.

– 6 – CXP508L4/508L6 AC characteristics (1) Clock timing (Ta = –20 to +75°C, V DD = 2.4 to 3.5V, VSS = 0V) Item System clock frequency System clock input pulse width System clock input rising and falling times Event count clock input pulse width Event count clock input rising and falling times fc tXL tXH tCR tCF tEL tEH tER tEF XTAL EXTAL EXTAL EXTAL EC EC Fig. 1., Fig. 2. Fig. 1., Fig. 2.* External clock drive Fig. 1., Fig. 2.*1 External clock drive Fig. 3. Fig. 3. 0.5 230 tsys*2 + 0.05 200 MHz ns ns µs ms Symbol Pin Condition Min. Max. Unit 1 The external clock in Fig. 2. specified only when the option is selected for crystal or ceramic oscillation. *2 tsys = 8/fc Note) When adjusting the frequency accurately, there may be cases in which they may differ from Fig. 2. Fig. 1. Clock timing EXTAL tXH tXLtCF tCR 0.4V VDD – 0.4V 1/fc Fig. 2. Clock applying condition /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines External clock∗1 EXTAL XTAL /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Crystal oscillation Ceramic oscillation EXTAL XTAL C 1 C 2 OPEN Fig. 3. Event count clock timing EC tEH tELtEF tER 0.2VDD 0.8VDD

– 7 – CXP508L4/508L6 (2) Serial transfer (Ta = –20 to +75°C, VDD = 2.4 to 3.5V, VSS = 0V) Item Serial transfer clock (SC) cycle time tKCY tKH tKL tSIK tKSI tKSOA tKSOB tKSOA tKSOB tKSOA tKSOB SC Input mode Output mode input mode Output mode* Output mode*2 SC input mode SC output mode SC input mode SC output mode tsys/4 + 1.42 tsys tsys/8 + 0.7 tsys/2 – 0.1 tsys/2 – 1.6 0.1 0.2 tsys/8 + 0.5 0.1 tsys/8 + 0.5 tsys/8 + 1.6 tsys/8 + 0.5 µs µs µs µs µs µs µs µs µs µs µs µs SC SI SI SOA SOB SOA SOB SOA SOB Serial transfer clock (SC) high and low level widths Serial data input setup time (against SC ›) Serial data input hold time (against SC ›) High data* 3 output delay time from the SC falling time High data*4 output delay time from the SC falling time Low data output delay time from the SC falling time Symbol Pin Condition Min. Max. Unit Note 1)tsys = 8/fc Note 2)The load of data output delay time is 50pF + 1TTL. *1 It is specified when SC pin is selected to the 3-atate output by the mask option. *2 It is specified when SC pin is selected to the pull-up resistance by the mask option. As the tsys receives restriction by this item, take notice that it limits the upper limit of the system clock frequency fc. *3 It is specified when SOA and PX1/SOB pins are selected to the 3-state output by the mask option. *4 It is specified when SOA and PX1/SOB pins are selected to the pull-up resistance by the mask option.

– 8 – CXP508L4/508L6 SC SI SOA SOB tKCY tKL tKH 0.2VDD 0.8VDD tSIK tKSI tKSOA tKSOB Input data Output data 0.2VDD 0.8VDD 0.2VDD 0.8VDD Fig. 4. Serial transfer timing (3) Others (Ta = –20 to +75°C, VDD = 2.4 to 3.5V, VSS = 0V) Item External interruption high and low level widths tI1H, tI1L tI2H, tI2L tRSL tWPH INT1 INT2 RST WP During edge detection mode STOP mode SLEEP mode µs µs µs ns µs tsys + 0.05 tsys + 0.05 2tsys 500 tsys + 0.05 Reset input low level width Wake-up input high level width Symbol Pin Condition Min. Max. Unit Note)tsys = 8/fc

– 9 – CXP508L4/508L6 Fig. 5. Interruption input timing 0.2VDD 0.8VDD tI1H tI1L INT1 (Falling edge) 0.8VDD tI1L tI1H INT1 (Rising edge) 0.2VDD 0.8VDD tI2L tI2H INT2 0.2VDD Fig. 6. Reset input timing tRSL 0.2VDD RST Fig. 7. Wake-up input timing tWPH 0.8VDD WP

– 10 – CXP508L4/508L6 Notes on Operation See Fig. 8., Additive capacity calculation chart, when using the crystal oscillator and select the appropriate capacity. Fig. 8. Crystal oscillation circuit additive capacity calculation chart (Ta = –20 to +75°C, V DD = 2.4 to 3.5V) /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines EXTAL XTAL C 1 C 1 = C2 = C C 2 0.1 1 5 100 f-Crystal oscillation frequency [MHz] C-Additive capacity [pF] 100 150 200 Note) The above chart shows a range in which the average quartz resonator has a relatively fast oscillation rising edge and stable characteristics. The capacity should be selected to correspond to the appropriate constant for each quartz resonator, should the frequency of the quartz resonator be accurately adjusted. Fig. 9. Shows recommended circuit and oscillators. Use the trimmer capacitor to C 1, in the case of accurate adjustment of the oscillation frequency. Fig. 9. Recommended oscillation circuit EXTAL XTAL C 1 C 2 Rd Manufacturer MURATA MFG CO., LTD. Model CSA2.00MG040 CST2.00MG040 Frequency 2.00MHz 2.00MHz 100pF (built in) 100pF (built in) C 1 C 2 Rd

– 11 – CXP508L4/508L6 Package Outline Unit: mm PACKAGE STRUCTURE MOLDING COMPOUND LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT SONY CODE EIAJ CODE JEDEC CODE SDIP-64P-01

42 ALLOY

64PIN SDIP (PLASTIC) 750mil SDIP064-P-0750-A 57.6 – 0.1 + 0.4 64 33 13 2 1.778 19.05 17.1 – 0.1 + 0.3 0° to 15° 0.25 – 0.05 + 0.1

0.5 MIN

4.75 – 0.1 + 0.4 3 MIN0.5 ± 0.1 0.9 ± 0.15 8.6g SONY CODE EIAJ CODE JEDEC CODE 23.9 ± 0.4 20.0 – 0.1 1.0 0.4 – 0.1 + 0.15 14.0 – 0.1 1 19 3351 0.15 – 0.05 + 0.1 2.75 – 0.15 16.3 0.1 – 0.05 + 0.2 0.8 ± 0.2M± 0.12 0.15 + 0.4 17.9 ± 0.4 + 0.4 + 0.35 64PIN QFP(PLASTIC) QFP–64P–L01 ∗QFP064–P–1420 PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER/PALLADIUM COPPER /42 ALLOY PACKAGE STRUCTURE PLATING 1.5g