CXP402

CXP402 SONY | Alldatasheet

Document overview

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Technical content

Features

• Instruction cycle 1.89µs for 16.93MHz oscillation
• ROM capacity 6144
• 8 bits
• RAM capacity 400 · 4 bits (Including stack and display area)
• LCD controller/driver (Enables to direct drive)
• 8-bit timer, 8-bit timer/event counter and 18-bit time-base timer are incorporated; they are independently controllable.
• Arithmetic and logical operations between the entire RAM area, I/O area and the accumulator by means of the memory mapped I/O.
• Entire ROM area can be referred by the table look- up instruction. Digital Signal Processor (DSP) Block
• Playback mode supporting CAV (Constant Angular Velocity)
• Frame jitter free
• Allows relative rotational velocity readout
• Supports spindle external control
• Wide capture range playback mode
• Spindle rotational velocity following method
• 16K RAM
• EFM data demodulation
• Enhanced EFM frame sync signal protection
• SEC strategy-based error correction
• Subcode demodulation and Sub Q data error detection
• Digital spindle servo
• 16-bit traverse counter
• Asymmetry correction circuit
• Servo auto sequencer
• Digital audio interface output
• Digital peak meter Digital Filter, DAC and Analog Low-Pass Filter Blocks
• DBB (digital bass boost) function
• Digital de-emphasis
• Digital attenuation
• Zero detection function
• 8Fs oversampling digital filter
• S/N: 100dB or more (master clock: 384Fs, typ.) Logical value: 109dB
• THD + N: 0.007% or less (master clock: 384Fs, typ.)
• Rejection band attenuation: –60dB or more
• 112-pin plastic LQFP
• Piggyback package (CXP401Z) available Structure Silicon gate CMOS IC – 1 – E98924-PS Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. CXP402 112 pin LQFP (Plastic)

– 2 – CXP402 58 59 6063 64 6162 7065 XRST RMC PC3 PC2 PC1 PC0 PB3 PB2 PB1 PB0 SEIN CNIN DATO XLTO CLKO MON MDS MDP LOCK VPCO2 VPCO1 VCKI V16M VCTL PCO FILI FILO AVSS CLTV AVDD RF BIAS ASYI ASYO C4M SBSO EXCK 8 91011 1213 14 15 16 17 18 19 20 21 22 2324 25 2623 4 5 1 4954 55 VLC1 VLC2 VLC3 COM0 COM1 COM2 COM3 SEG0 SEG1 SEG2 SEG3 88878685 89 90 95 9491 92 93 LRCK PCMD PCMDI BCK BCKI AVSS AVDD AOUT2 AIN2 LOUT2 AVSS XVSS XTAO XTAI XVDD AVSS LOUT1 AIN1 AOUT1 AVDD AVSS LRCKI 37 36 35 34 3233100 99 98 97 96101102103104105106107108109110111 PA3 PA2 PA1 PA0 SEG 15 SEG 14 SEG 13 SEG 12 SEG 11 SEG 10 SEG 9 SEG 8 SEG 7 SEG 6 SEG 5 SEG 4 TEST1 TEST0 G TO P XPC K R FC K C 2PO XR O F M N T3 M N T1 M N T0 D O U T W FC K VSS VD D VD D VSS C TEST D TEST VSS VD D XRSTO FOK GFS EMPH SCOR 30 315153 40 LC D C ontroller/D river SPC 500 C PU C ore R O M 6K Byte R AM 400 × 4bit T/C R M C Port R ST SC O R EM PH I Servo Auto Sequencer D igital C LV D igital PLL Asym m etry C ollector D /A I/F EFM D em odulator EPR O M C ollector 1-bit D AC D igital Filter Test C ircuit Analog O ut 16K R AM AC D T R M U T LM U T D ATA XLAT C LO K XR ST SYSM PW M I XTSL ASYE SEN S FO K G FS SQ C K SQ SO IN T PY0 PY2 PX0 PX3 PF0 PF1 PF2 PF3 PE0 PE1 PE2 PE3 PD 0 PD 1 PD 2 PY1 SIO I/F O SC PO R T I/F C PU I/F PY3 Block Diagram

– 3 – CXP402 Pin Configuration (Top View) SEIN C N IN D ATO XLTO C LKO VSS VD D M O N M D P M D S LO C K VPC O 2 VPC O 1 VC KI V16M VC TL PC O FILI FILO AVSS C LTV AVD D R F BIAS ASYI ASYO TEST1 TEST0 XRST XRSTO FOK LRCK PCM D PCM DI BCK BCKI GTOP XPCK GFS RFCK C2PO V SS V DD XROF M NT3 M NT1 M NT0 C4M DOUT EM PH W FCK SCOR SBSO EXCK DTEST NC AV SS AV DD AOUT2 AIN2 LOUT2 AV SS XV SS XTAO XTAI XV DD AV SS LOUT1 AIN1 AOUT1 AV DD AV SS V LC1 V LC2 V LC3 COM COM COM COM SEG0 SEG1 SEG2 SEG3 SEG 15 VD D VSS R M C PC 3 PC 2 PC 1 PC 0 C TEST PB3 PB2 PB1 PB0 PA3 PA2 PA1 PA0 SEG 14 SEG 13 SEG 12 SEG 11 SEG 10 SEG 9 SEG 8 SEG 7 SEG 6 SEG 5 SEG 4 LRCKI 88 87 86 858990100 99 98 97 96 95 94 919293101102103104105106107108109110111112 29 30 4039383736353431 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

– 4 – CXP402 Pin Description Symbol I/O Description (Port A) 4-bit I/O port. I/O can be set in a unit of single bits. Pull-up resistor is attached for input. (4 pins) (Port B) 4-bit I/O port. I/O can be set in a unit of single bits. Pull-up resistor is attached for input. (4 pins) (Port C) 4-bit I/O port. I/O can be set in a unit of single bits. Pull-up resistor is attached for input. (4 pins) LCD segment signal output. (16 pins) LCD common signal output. LCD bias power supply. Bias voltage is generated, which is 1/3 the supply voltage due to the internal resistor. (3 pins) SENS input from SSP. Track jump count signal input. Serial data output to SSP. Serial data latch output to SSP. Serial clock output to SSP. Spindle motor ON/OFF control output. Spindle motor servo control. (2 pins) Lock signal output. GFS is sampled at 460Hz and; when GFS is high, this pin outputs a high signal. If GFS is low eight convective samples, this pin outputs low. Wide-band EFM PLL charge pump output. (2 pins) Wide-band EFM PLL VCO2 oscillation input. Wide-band EFM PLL VCO2 oscillation output. Wide-band EFM PLL VCO2 control voltage input. Master PLL charge pump output. Master PLL filter input. Master PLL filter output. Master VCO control voltage input. EFM signal input. Asymmetry circuit constant current input. Asymmetry comparator voltage input. EFM output. (full swing) System reset input. Active at low. I/O I/O I/O Output Output Input Input Output Output Output Output Output (tri-state) Output Output (tri-state) Input Output Input Output (tri-state) Input Output (Analog) Input Input Input Input Output Input PA0 to PA3 PB0 to PB3 PC0 to PC3 SEG0 to SEG15 COM0 to COM3 V LC1 to VLC3 SEIN CNIN DATO XLTO CLKO MON MDP MDS LOCK VPCO1 VPCO2 VCKI V16M VCTL PCO FILI FILO CLTV RF BIAS ASYI ASYO XRST

Reset signal output. Active at low. Focus OK input. Used for SENS output and servo auto sequencer. D/A interface LR clock output. (f = Fs) LR clock input. D/A interface serial data output. D/A interface serial data input. D/A interface bit clock output. D/A interface bit clock input. GTOP output. XPLCK output. GFS output. RFCK output. C2PO output. XRAOF output. MNT3 output. MNT1 output. MNT0 output. 1/4 frequency division output of the oscillation input. (4.2336MHz for 16.3944MHz) Digital Out output. De-emphasis ON/OFF output. High is output for ON; low is output for OFF. WFCK output. Subcode sync detection output. Outputs a high signal when either subcode sync S0 or S1 is detected. Sub P to W serial data output. SBSO serial clock input. Lch analog output. Lch operational amplifier input. Lch LINE output. Rch analog output. Rch operational amplifier Rch LINE output. Remote control receiver circuit input. Connect a crystal for system clock oscillation. When the clock is supplied externally, input it to the XTAI pin and leave the XTAO pin open. No connected. Output Input Output Input Output Input Output Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Output (Analog) Input (Analog) Output Output (Analog) Input (Analog) Output Input Input XRSTO FOK LRCK LRCKI PCMD PCMDI BCK BCKI GTOP XPCK GFS RFCK C2PO XROF MNT3 MNT1 MNT0 C4M DOUT EMPH WFCK SCOR SBSO EXCK AOUT1 AIN1 LOUT1 AOUT2 AIN2 LOUT2 RMC XTAI XTAO NC – 5 –

– 6 – CXP402 Symbol I/O Description Positive power supply. GND. Positive power supply for analog circuit. GND for analog circuit. Positive power supply for oscillation circuit. GND for oscillation circuit. Test for LSI. Connect to GND for normal operation. Input Input Input Input V DD VSS AV DD AV SS XV DD XV SS TEST1 TEST0 DTEST CTEST Notes

• Power supply pins AV DD , AVss, XVDD , XVss, VDD and Vss should process all the pins.
• PCMD is the MSB first, two's complement output.
• GTOP is used to monitor the frame sync protection status. (High: sync protection window open.)
• XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before sync protection.
• XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point coincide.
• The GFS signal goes high when the frame sync and the insertion timing match.
• RFCK is derived from the crystal accuracy, and has a cycle of 136µs (at normal speed).
• C2PO represents the data error status.
• XRAOF is generated when the 16K RAM exceeds the ±4F jitter margin.

– 7 – CXP402 D ata bus Port C data Port C I/O direction R D (Port C ) ∗ Pull-up transistor approx. 50kΩ IP ∗ EM PH I is not Schm itt input. IP Internal circuit Schm itt input Port C 8 pins Hi-Z Hi-Z When reset PA0 to PA3 PB0 to PB3 4 pins PC0 to PC3 RMC XRST SEIN CNIN VCKI FOK LRCKI PCMDI BCKI EXCK 10 pins Hi-Z Ports A, B data Ports A, B I/O direction R D (Ports A, B) D ata bus ∗ Pull-up transistor approx. 50kΩ Input protection circuitIP Input/Output Circuit Formats for Pins Port A Port B Pin Circuit format

– 8 – CXP402 IP ∗ Internal resistor approx. 20kΩ XTAI XVSS XVD D XTAO 4 pins 16 pins VDD level VLC1 = 3/4VDD VLC2 = 2/4VDD VLC3 = 1/4VDD (when pins left open) When reset COM0 COM1 COM2 COM3 3 pins V LC1 VLC2 VLC3 XV DD XTAI XTAO XV SS 4 pins Oscillation VLC 1 VLC 2 VD D VLC 3 Pin Circuit format VC H VC L SEG0 to SEG15 VDD level

– 9 – CXP402 PCO MDP VPCO1 VPCO2 4 pins 1 pin M D S O utput enable MDS IP 6 pins When reset VCTL FILI CLTV RF BIAS ASYI 2 pins AIN1 AIN2 AOUT1 AOUT2 LOUT1 LOUT2 4 pins IP Poly resistor Pin Circuit format

– 10 – CXP402 When reset DATO XLTO CLKO LOCK MON V16M FILO ASYO XRSTO LRCK PCMD BCK GTOP XPCK GFS RFCK C2PO XROF MNT3 MNT1 MNT0 C4M DOUT EMPH WFCK SCOR SBSO Pin Circuit format 27 pins

– 11 – CXP402 Absolute Maximum Ratings Item Supply voltage LCD bias voltage Input voltage Output voltage High level output current High level total output current Low level output current Low level total output current Operating temperature Storage temperature Allowable power dissipation V DD VLC1 , VLC2 , VLC3 VIN VOUT IOH ∑ IOH IOL ∑ IOL Topr Tstg P D –0.3 to +7.0*1 –0.3 to +7.0*2 –0.3 to +7.0*2 –0.3 to +7.0*2 –70 100 –20 to +75 –40 to +125 600 V V V V mA mA mA mA mW Output pin (value per pin) Total of output pins Output pin (value per pin) Total of output pins Symbol Ratings Unit Remarks 1 The potential difference between analog power supplies AVDD , AVss, the oscillation power supplies XVDD , XVss and VDD , Vss should be within ±0.3V. *2 VLC1 , VLC2 , VLC3 , VIN and VOUT should not exceed VDD + 0.3V. Note)Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended conditions. Exceeding those conditions may adversely affect the reliability of the LSI. Recommended Operation Conditions Item Supply voltage VDD VLC1 , VLC2 , VLC3 VIH VIHS VIL VILS VIA Topr LCD bias voltage High level input voltage Low level input voltage Analog input voltage Operating temperature Symbol Min. 3.4 VSS 0.7VDD 0.8VDD –20 5.25 V DD VDD VDD 0.3VDD 0.2VDD VDD +75 V V V V V V V Operation guaranteed range Liquid crystal power supply range* Hysteresis input*2 Hysteresis input*2 Max. Unit Remarks *1 The optimal value depends on the characteristics of the used LCD element. Also, the LCD bias voltage is biased to 1/3 the supply voltage by the resistor of approximately 20kΩ in the LSI. *2 RME, XRST, EXCK, FOK, SEIN, CNIN, VCKI, LRCKI, BCKI, PCMDI pins *3 CLTV, FILI, RF, VCTL, AIN1, AIN2, BAIS, ASYI pins (Vss = 0V reference) (Vss = 0V reference)

– 12 – CXP402

Electrical Characteristics

DC characteristics (Topr = –20 to +75°C, VSS = AVSS = XVSS = 0V reference) Item High level output voltage VOH PA, PB BCKI, C2PO, SBSO, DATO, XLTO, CLKO, PA (V OL only), PB (VOL only), PC, MON, MDS, LOCK, LRCK, PCMD, BCK, GTOP, GFS, RFCK, XROF, MNT3, MNT1, MNT0, DOUT, WFCK, SCOR, MDP, VPCO2, VPCO1, PCO, V16M, EMPH, XPCK, ASYO, C4M, XRSTO, LRCK, PCMD VDD = 4.75V, IOH = –0.1mA VDD = 4.75V, IOH = –2.0mA VDD = 4.75V, IOH = –0.28mA VDD = 4.75V, IOL = 0.36mA VDD = 4.75V, IOL = 6.0mA VDD = 4.75V, IOL = 9.0mA VDD = 5.25V, VIH = 5.25V VDD = 5.25V, VIL= 0.4V 4.25 4.25 4.25 0.2 –0.2 –0.06 0.4 0.4 0.6 –30 –0.2 V V V V V V µA µA mA µA pF V DD = 5.25V VI= 0, 5.25V VDD = 5.0V VLC1 = 3.75V VLC2 = 2.5V VLC3 = 1.25V VDD = 5.25V 16.93MHz self-excited oscillation operation All output pins left open Clock 1MHz 0V for no-measured pins XTAI PA to PC PCMDI, RME, XRST, EXCK, FOK, SEIN, CNIN, VCKI, LRCKI, BCKI, CLTV, FILI, RF, VCTL, AIN1, AIN2, MDP, MDS, VPCO1, VPCO2 COM0 to COM3 SEG0 to SEG15 V DD , AVDD Pins other than VLC1 to VLC3 , COM0 to COM3, SEG0 to SEG15, PA to PC, V DD , VSS , AVDD , AV SS , XVDD , XVSS VOL IIH IILE IIL IIZ Low level output voltage Input current High-impedance I/O leak current Common output impedance kΩ kΩ kΩ mA V DD = 5V, VLC1 , VLC2 , VLC3 pins left openVLC1 , VLC2 , VLC3R B R COM R SEG IDD C IN LCD bias voltage resistance Segment output impedance Supply current Input capacity Symbol Pins Conditions Min. Typ. Max. Unit FILO

– 13 – CXP402 AC Characteristics 1. XTAI pin (1) When using self-excited oscillation (Topr = –20 to +75°C, V DD = AVDD = 5.0V ± 5%) (2) When inputting pulses to XTAI pin (Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%) (3) When inputting sine waves to XTAI pin via a capacitor (Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%) Oscillation frequency fMAX 15 16.93 20 MHz Item Symbol Min. Typ. Max. Unit High level pulse width tWHX 13 500 ns Low level pulse width tWLX 13 500 ns Pulse cycle tCK 26 1,000 ns Input high levelVIHX VDD – 1.0 V Input low level VILX 0.8 V Rise time, fall time tR , tF 10 ns Item Symbol Min. Typ. Max. Unit Input amplitude VI 2.0 VDD + 0.3 Vp-p Item Symbol Min. Typ. Max. Unit tR tF tW H X tW LX tC K VILX VIH X × 0.1 VIH X × 0.9 VIH X XTAI VD D /2

– 14 – CXP402 2. CNIN, EXCK pins (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C) 3. BCKI, LRCKI, PCMDI pins (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C) Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width EXCK frequency EXCK pulse width f CK tWCK tSU tH tD tWL fT fWT 750 300 300 300 750 750 0.65 0.65 MHz ns ns ns ns ns MHz ns Item Symbol Min. Typ. Max. Unit tW C K tW C K 1/fC K tHtSU tW LtD 1/fT tW T tW T tHtSU C LK D ATA XLT EXC K C N IN SU BQ BCK pulse width DATAL, R setup time DATAL, R hold time LRCK setup time tW tSU tH tSU ns ns ns ns Item Symbol Conditions Typ. Min. Max. Unit VD D /2 VD D /2 tW (BC KI) tW (BC KI) tSU (PC M D I) tH (PC M D I) tSU (LR C KI) BC KI PC M D I LR C KI

– 15 – CXP402 1-bit DAC, LPF Blocks Analog Characteristics Analog characteristics (VDD = AVDD = 5.0V, VSS = AVSS = 0V, Ta = 25°C) Fs = 44.1kHz. The total harmonic distortion and signal-to-noise ratio are measured by the circuits shown below. LPF external circuit diagram Block diagram of analog characteristics measurement Item Total harmonic distortion Signal-to- noise ratio Symbol THD S/N Conditions 1kHz, 0dB data Crystal 1kHz, 0dB data (A-filter) 384Fs 768Fs 384Fs 768Fs 0.0050 0.0045 100 100 0.0070 0.0065 Min. Typ. Max. Unit dB Audio Analyzer SH IBASO KU (AM 51A) 100k 22µ 680p 12k 12k 12k 150p AO U T1 (2) AIN 1 (2) LO U T1 (2) Audio AnalyzerC XP402 R ch A Lch B D ATA R F TEST D ISC 768Fs/384Fs (VDD = AVDD = 5.0V, VSS = AVSS = 0V, Topr = –20 to +75°C) Output voltage Load resistance VOUT R L Vrms kΩ Item Symbol Min. Max. 1.23* Typ. Applicable pinsUnit * When a sine wave of 1kHz, 0dB is output. Applicable pins *1 LOUT1, LOUT2

– 16 – CXP402 SO N Y C O D E EIAJ C O D E JED EC C O D E PAC KAG E M ATER IAL LEAD TR EATM EN T LEAD M ATER IAL PAC KAG E W EIG H T EPO XY R ESIN SO LD ER PLATIN G C O PPER ALLO Y PAC KAG E STR U C TU R E 0.65 0.32 ± 0.05 1 28 5784 112 20.0 ± 0.1 22.0 ± 0.2 1.7M AX 1.4 ± 0.1 M D ETAIL A D ETAIL B 0.32 ± 0.05 (0.3) (0.125) 0.145 ± 0.03 (21.0) (0.5) 0° — 10° 0.13 A B 0.1 112PIN LQ FP(PLASTIC ) LQ FP-112P-L01 LQ FP112-P-2020 1.3g S S S 0.1 ± 0.05 0.6 ± 0.15 0.25 Package Outline Unit: mm