CXP-82220 | DigiCamel IC Datasheet

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CXP82220 SONY | Alldatasheet

Document overview

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PDF pages: 21

Technical content

Features

Wide-range instruction system (213 instructions) to cover various types of data — 16-bit arithmetic/multiplication and division/Boolean bit operation instructions
Minimum instruction cycle 400ns at 10MHz operation 122µs at 32kHz operation
Incorporated ROM capacity 20K bytes (CXP82220) 24K bytes (CXP82224)
Incorporated RAM capacity 704 bytes (including fluorescent display area)
Peripheral functions — A/D converter 8 bits, 8 channels, successive approximation method (Conversion time of 32µs/10MHz) — Serial interface SIO with 8-bit, 8-stage FIFO incorporated for data use (Auto transfer for 1 to 8 bytes), 1 channel 8-bit standard SIO, 1 channel — Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer 16-bit capture timer/counter, 32kHz timer/counter — Fluorescent display tube controller/driver Maximum of 384 segment display possible 1 to 16-digit dynamic display Dimmer function High voltage drive output (40V) Incorporated pull-down resistor (Mask option) Hardware key scan function Maximum of 16
8 key matrix compatible — Remote control reception circuit Incorporated noise elimination circuit Incorporated 8-bit, 6-stage FIFO for measurement data — PWM output circuit 14 bits, 1 channel — CTL duty detection circuit — High-speed output circuit Precision of 800ns at 10MHz, 4 outputs
Interruption 19 factors, 15 vectors, multi-interruption possible
Standby mode Sleep/stop
Package 100-pin plastic QFP
Piggyback/evaluation chip CXP82200 100-pin ceramic QFP – 1 – E92235A81-PS Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. CXP82220/82224 100 pin QFP (Plastic) Structure Silicon gate CMOS IC

– 2 – CXP82220/82224 A/D C O N VER TER FD P C O N TR O LLER / D R IVER

14 BIT PW M G EN ER ATO R

SER IAL IN TER FAC E U N IT 1

8 BIT TIM ER /C O U N TER 0

8 BIT TIM ER 1

16 BIT C APTU R E

80 BYTES

(C XP82220) 24K BYTES (C XP82224) C LO C K G EN ./ SYSTEM C O N TR O L R AM

704 BYTES

PORT A PORT B PORT C PORT D PORT E PORT F PORT G PORT H PORT I PA0/AN 0 to PA7/AN 7 T0 to T7 T8/S31 to T15/S24 PD 0/S0 to PI7/S23 V FD P PE6/PW M PE5/C TL PE7/D D O PE4/R M C PB1/C S0 PB3/SI0 PB4/SO 0 PB2/SC K0 PB6/SI1 PB7/SO 1 PB5/SC K1 PE0/IN T0/EC 0 PE7/TO PB0/C IN T PE1/IN T1/EC 1 PA0 to PA7 PC 0 to PC 7 PD 0 to PD 7 PE0 to PE5 PE6 to PE7 PF0 to PF7 PG 0 to PG 7 PH 0 to PH 7 PI0 to PI7

7 PB0 to PB6

– 3 – CXP82220/82224 PE1/EC 1/IN T1 PE2/IN T2 PE3/IN T3/N M I PE4/R M C PE5/C TL PE6/PW M PE7/TO /D D O /AD J PB0/C IN T PB1/C S0 PB2/SC K0 PB3/SI0 PB4/SO 0 PB5/SC K1 PB6/SI1 PB7/SO 1 PC 0/KR 0 PC 1/KR 1 PC 2/KR 2 PC 3/KR 3 PC 4/KR 4 PC 5/KR 5 PC 6/KR 6 PC 7/KR 7 PH 0 PH 1 PH 2 PH 3 PH 4 PH 5 PH 6 T8/S31 T9/S30 T10/S29 T14/S25 T15/S24 PI7/S23 PI6/S22 PI5/S21 PI4/S20 PI3/S19 PI2/S18 PI0/S16 PF7/S15 PF6/S14 PF5/S13 PF4/S12 PF3/S11 PF2/S10 PF1/S9 PF0/S8 PD 7/S7 PD 6/S6 PD 5/S5 PD 4/S4 PD 3/S3 PH7 PA0/AN0 PA1/AN1 PA2/AN2 PA3/AN3 PA4/AN4 PA5/AN5 RST EXTAL XTAL V SS TX TEX PA6/AN6 PA7/AN7 AV REF AV SS PD0/S0 PD1/S1 PD2/S2 PG1/RTO1 PE0/EC0/INT0 PG7 PG5 PG4 PG3/RTO3 PG2/RTO2 PG0/RTO0 V SS NC V DD V FDP T0 T1 T2 T3 T4 T5 T6 4039383736353431 32 33 41 42 43 44 45 46 47 48 49 50 8182838488 87 86 858990100 99 98 97 96 95 94 919293 PI1/S17 T12/S27 T13/S26 T11/S28 PG6 Note)NC (Pin 90) must be connected to VDD. Pin Assignment(Top View)

– 4 – (Port A) 8-bit I/O port. I/O can be set in a unit of single bit . (8 pins) (Port B) 8-bit I/O port. I/O for lower 7 bits can be set in a unit of single bit. Uppermost bit (PB7) is for output only. (8 pins) (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Capable of driving 12mA synk current. (8 pins) (Port D) 8-bit output port. (8 pins) (Port E) 8-bit port. Lower 6 bits are for inputs; upper 2 bits are for outputs. (8 pins) (Port F) 8-bit output port. (8 pins) (Port G) 8-bit I/O port. I/O can be set in a unit of single bit. Data for the lower 4 bits are gated with the contents of RTO or OR-gate output. (8 pins) Analog inputs to A/D converter. (8 pins) External capture input to 16bittimer/counter. Chip select input for serial interface (CH0). Serial clock I/O (CH0). Serial data input (CH0). Serial data output (CH0). Serial clock I/O (CH1). Serial data input (CH1). Serial data output (CH1). Serves as key return inputs when operating key scan with FDP segment signal. FDP segment signal outputs. Inputs for external interruption request. (4 pins) Remote control reception circuit input. Input for CTL duty ditection circuit. 14-bit PWM output. Output for the 16-bit timer/counter rectangular waves, CTU duty detection, and 32kHz oscillation frequuency demultiplication. Outputs for real-time pulse generator (RTG). Functions as high-precision, real-time pulse output port. (4 pins) Symbol I/O Functions PA0/AN0 to PA7/AN7 PB0/CINT PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 PC0/KR0 to PC7/KR7 PD0/S0 to PD7/S7 PE0/INT0/EC0 PE1/INT1/EC1 PE2/INT2 PE3/INT3/NMI PE4/RMC PE5/CTL PE6/PWM PE7/TO/DDO/ ADJ PF0/S8 to PF7/S15 PG0/RTO0 to PG3/RTO3 PG4 to PG7 I/O/ Analog input I/O/Input I/O/Input I/O/I/O I/O/Input I/O/Output I/O/I/O I/O/Input Output/Output I/O/Input Output/Output Input/Input/Input Input/Input/Input Input/Input Input/Input/Input Input/Input Input/Input Output/Output Output/Output/ Output/Output Output/Output I/O/Output I/O External event inputs for timer/counter. (2 pins) Non-maskable interruption request input. FDP segment signal outputs.

– 5 – CXP82220/82224 (Port H) 8-bit I/O port. I/O can be set in a unit of single bit. (8 pins) (Port I) 8-bit output ports. FDP segment signal outputs. (8 bits) Outputs for FDP timing (digit) signals/segment signals. FDP timing signal outputs. FDP voltage supply when incorporated resistor is set by mask option. Crystal connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL; opposite phase clock should be input to XTAL. Crystal connectors for 32kHz timer/counter clock oscillation. Set 32kHz crystal oscillator between TEX and TX. For usage as event input, attach clock source to TEX, and open TX. Low-level active, system reset. NC. Under normal operation, connect to V DD . Reference voltage input for A/D converter. A/D converter GND. Positive power supply. GND. Symbol I/O Functions PH0 to PH7 PI0/S16 to PI7/S23 T8/S31 to T15/S24 T0 to T7 V FDP EXTAL XTAL TEX TX RST NC AV REF AV SS VDD VSS I/O Output/Output Output/Output Output Input Output Input Output Input Input

– 6 – CXP82220/82224 When resetPin Circuit format Input/Output Circuit Formats for Pins IP R D (Port B) D ata bus Port B direction Port B output selection "0" w hen reset SC K in Schm itt input Port B data "0" w hen reset SC K out O utput enable Hi-Z Hi-Z Hi-Z PB0/CINT PB1/CS0 PB3/SI0 PB6/SI1 PB2/SCK0 PB5/SCK1 Port B Port B 2 pins Port A IP Input protection circuit R D (Port A) D ata bus Port A direction Port A data "0" w hen reset Port A input selection "0" w hen reset A/D converter Input m ultiplexer IP R D (Port B) D ata bus Port B direction Port B data "0" w hen reset C IN T C S0 SI0 SI1 Schm itt input PA0/AN0 to PA7/AN7 8 pins 4 pins

– 7 – CXP82220/82224 When resetPin Circuit format IP R D (Port B) D ata bus Port B direction Port B output selection "0" w hen reset Port B data "0" w hen reset SO O utput enable Port B Port C Port E 1 pin High level Hi-Z Hi-Z PB4/SO0 PB7/SO1 1 pin 8 pins Hi-Z PC0/KR0 to PC7/KR7 6 pins PE0/EC0/INT0 PE1/EC1/INT1 PE2/INT2 PE3/INT3/NMI PE4/RMC PE5/CTL Port B IP R D (Port C ) D ata bus Port C direction Port C data "0" w hen reset Key input signal ∗ Large current drive of 12m A possible R D (Port E) IP EC 0/IN T0 EC 1/IN T1 IN T2 IN T3/N M I R M C C TL D ata bus Schm itt input R D (Port B) D ata bus Port B output selection "1" w hen reset Port B data "1" w hen reset SO O utput enable Internal reset signal ∗ Pull-up transistor approx. 10kΩ

– 8 – CXP82220/82224 When resetPin Circuit format IP R D (Port G ) D ata bus Port G direction Port G data "0" w hen reset R TO data "0" w hen reset R D (Port E) D ata bus Port E output selection "1" w hen reset Port E data "0" w hen reset ∗ AD J signal is a frequency dem ultiplication output for 32kH z oscillation frequency adjustm ent. AD J2K can be used for buzzer output. Port E output selection Port E output selection M PX TO D D O AD J16K AD J2K O utput enable "00" w hen reset R D (Port E) D ata bus Port E output selection "1" w hen reset Port E data "0" w hen reset PW M Port E 1 pin High level Hi-Z PE6/PWM PE7/TO/ DDO/ADJ Port G 1 pin 4 pins High level PG0/RTO0 to PG3/RTO3 Port E

– 9 – CXP82220/82224 VFD P R D (Port D , F, or I) D ata bus "0" w hen reset Port D , F, or I data ("0" w hen reset) Segm ent output data O utput selection control signal ∗ H igh voltage drive transistor M ask option Pull-dow n resistor O P 24 pins Hi-Z or Low level (when PD resistance is added) Oscillation When reset PD0/S0 to PD7/S7 PF0/S8 to PF7/S15 PI0/S16 to PI7/S23 T15/S24 to T8/S31 T0 to T7 16 pins 2 pins EXTAL XTAL Hi-Z or Low level (when PD resistance is added) Port D Port G Port H Port F Port I Pin Circuit format VFD P ("0" w hen reset) Segm ent output data O utput selection control signal ∗ H igh voltage drive transistor M ask option Pull-dow n resistor O P IPIPEXTAL XTAL

D iagram show s circuit com position during oscillation.
Feedback resistor is rem oved during stop. Hi-Z 12 pins PG4 to PG7 PH0 to PH7 IP R D (Port G or Port H ) D ata bus Port G or Port H direction Port G or Port H data "0" w hen reset

– 10 – CXP82220/82224 2 pins Oscillation TEX TX IPIPTEX TX

W hen the operation of the oscillation circuit is stopped by the softw are, the feedback resistor is rem oved, and TEX and TX becom e "Low " level and "H igh" level respectively.
D iagram show s circuit com position during oscillation. 1 pin Low level RST M ask option IP Schm itt input Pull-up resistor O P When resetPin Circuit format

– 11 – CXP82220/82224 *1 VIN and VOUT must not exceed VDD + 0.3V. *2 Specifies output current of general-purpose l/O ports. *3 The large current drive transistor is the N-CH transistor of Port C (PC). Note)Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSl. Supply voltage Input voltage Output voltage Display output voltage High level output current High level total output current Low level output current Low level total output current Operating temperature Storage temperature Allowable power dissipation VDD AV SS VIN VOUT VOD IOH IODH1 IODH2 ∑ IOH ∑ IODH IOL IOLC ∑ IOL Topr Tstg P D As P channel transistor is open drain, VDD is reference. All pins excluding display outputs*2 (value per pin) Display outputs S0 to S23 (value per pin) Display outputs T0 to T7, and T8/S31 to T15/S24 (value per pin) Total for all pins excluding display outputs Total for all display outputs Port 1 Large current Port 1 * Total for all output pins Item Symbol Rating Unit Remarks Absolute Maximum Ratings (Vss = 0V reference) –0.3 to +7.0 –0.3 to +0.3 –0.3 to +7.0*1 –0.3 to +7.0*1 VDD – 40 to VDD + 0.3 –15 –35 –40 –100 100 –20 to +75 –55 to +150 600 V V V V V mA mA mA mA mA mA mA mA mW

– 12 – CXP82220/82224 High level input voltage Low level input voltage Operating temperature Supply voltage 5.5 5.5 5.5 5.5 VDD VDD VDD + 0.3 0.3VDD 0.2VDD 0.4 +75 V V V V V V V Item Symbol Min. Max. Unit Remarks 4.5 3.5 2.7 2.5 0.7VDD 0.8VDD VDD – 0.4 –0.3 –20 VIH VIHS VIHEX VIL VILS VILEX Topr High-speed mode Guaranteed operation range Low-speed mode Guaranteed operation range Guaranteed operation range with TEX clock Guaranteed data hold range during stop Hysteresis input*2 EXTAL *3 Hysteresis input*2 EXTAL *3 VDD *1 Value for each pin of normal input ports (PA, PB3, PB4, PB6, PC, PG, PH). *2 Value of the following pins: RST, CINT, CS0, SCK0, SCK1, EC0/INT0, EC1/INT1, INT2, INT3/NMI, RMC, CTL. *3 Specifies only during external clock input. Recommended Operating Conditions (Vss = 0V reference)

– 13 – CXP82220/82224 VDD = 4.5V, IOH = –0.5mA VDD = 4.5V, IOH = –1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL= 0.4V VDD = 5.5V, VIH = 5.5V High level output voltage 4.0 3.5 0.5 –0.5 0.1 –0.1 –1.5 –20 V V V V V µA µA µA µA µA mA mA µA kΩ µA mA µA mA µA µA pF PC EXTAL TEX RST * Item Symbol Pins Conditions Min. VDD IDD1 IOH ILOL IDD2 IDDS1 IDDS2 IDDS3 C IN VOH VOL IIHE IILE IIHT IILT IILR Low level output voltage Input current Typ. 0.4 0.6 1.5 –40 –10 –400 –20 270 –10 100 Max. Unit DC Characteristics

Electrical Characteristics

(Ta = –20 to +75°C, Vss = 0V reference) VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) Supply current*3 Input capacity VDD = 5.5V, VIL= 0.4V VDD = 4.5V, VOH = VDD – 2.5V VDD = 5.5V VOL = VDD – 35V VFDP = VDD – 35V High-speed mode operation (1/2 frequency demultiplier clock) Stop mode VDD = 5.5V, termination of 10MHz and 32kHz crystal oscillation Clock 1MHz 0V for all pins excluding measured pins Display output current I IZI/O leakage current Open drain output leakage current (P-CH Tr in off state) S0 to S23 S24/T15 to S31/T8 T0 to T7 S0 to S23 S24/T15 to S31/T8 T0 to T7 R L VDD = 5V VFDP = VDD – 35V VDD = 5.5V VI= 0, 5.5V Pull-down resistance*2 S0 to S23 S24/T15 to S31/T8 T0 to T7 PA to PC, PE, PG, PH, RST* 100 1.2 PA, PB, PC,PE6, PE7, PG, PH Pins other than S0 to S31, T0 to T7, PB7, PE6,PE7,AVREF , AV SS , VFDP , VDD , VSS Sleep mode *1 RST specifies the input current when pull-up resistance has been selected; leakage current when no resisance has been selected. *2 When incorporated pull-down resistance has been selected through mask option. *3 When all pins are open.

– 14 – CXP82220/82224 *1 tsys indicates the three values below according to the upper two bits(CPU clock selection)of the clock control register (address: 00FEH ). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") EXTAL tXH tXLtC F tC R 0.4V VD D – 0.4V 1/fc /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines External clock EXTAL XTAL 74H C 04 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines C rystal oscillation C eram ic oscillation EXTAL XTAL C 1 C 2 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines 32kH z clock applied condition C rystal oscillation TEX TX C 1 C 2 AC Characteristics (1) Clock timing System clock frequency System clock input pulse width System clock input rise time, fall time Event count input clock pulse width Event count input clock rise time, fall time System clock frequency Event count input clock input pulse width Event count input clock rise time,fall time f C tXL, tXH tCR , tCF tEH , tEL tER , tEF fC tTL, tTH tTR , tTF XTAL EXTAL EXTAL EXTAL EC0 EC1 EC0 EC1 TEX TX TEX TEX MHz ns ns ns ms kHz µs ms Item Symbol Pins Conditions Unit Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock drive Fig. 1, Fig. 2 External clock drive Fig. 3 Fig. 3 V DD = 2.7 to 5.5V Fig. 2 (32kHz clock applied condition) Fig. 3 Fig. 3 Typ. 32.768 Min. 37.5 tsys + 50*1 Max. 200 (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Fig. 1. Clock timing Fig. 2. Clock applied conditions

– 15 – CXP82220/82224 Input mode Output mode Input mode Output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode Chip select transfer mode (SCK0 = output mode) Chip select transfer mode (SCK0 = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock control register (address: 00FEH ). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL. (2) Serial transfer (CH0) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss=0V reference) Item CS0 ﬂ ﬁ SCK0 delay time CS0 › ﬁ SCK0 float delay time CS0 ﬂ ﬁ SO0 delay time CS0 › ﬁ SO0 float delay time CS0 High level width SCK0 cycle time SCK0 High, Low level width SI0 input setup time (for SCK0 ›) SI0 input hold time (for SCK0 ›) SCK0 ﬂ ﬁ SO0 delay time tDCSK tDCSKF tDCSO tDCSOF tWHCS tKCY tKH , tKL tSIK tKSI tKSO SCK0 SCK0 SO0 SO0 CS0 SCK0 SCK0 SI0 SI0 SO0 ns ns ns ns ns Symbol Pin Min. tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200 2tsys + 200 16000/fc tsys + 100 8000/fc – 50 100 200 tsys + 200 100 ns ns ns ns ns ns ns ns ns ns tsys + 200 100 Max. UnitCondition TEX EC 0 EC 1 tEH tELtEF tER 0.2VD D 0.8VD D tTH tTLtTF tTR Fig. 3. Event count clock timing

Fig. 4. Serial transfer CH0 timing C S0 SC K0 0.2VD D 0.8VD D tW H C S tD C SK tD C SKF 0.8VD D 0.2VD D 0.8VD D tKC Y tKL tKH 0.8VD D 0.2VD D SI0 tSIK tKSI Input data tD C SO tKSO tD C SO F O utput data 0.8VD D 0.2VD D SO 0 – 16 –

– 17 – CXP82220/82224 Serial transfer (CH1) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol Pin Min. Max.Condition SCK1 cycle time SCK1 High, Low level width SI1 input setup time (for SCK1 ›) SI1 input hold time (for SCK1 ›) SCK1 ﬂ ﬁ SO1 delay time tKCY tKH , tKL tSIK tKSI tKSO SCK1 SCK1 SI1 SI1 SO1 Input mode Output mode Input mode Output mode SCK1 input mode SCK1 output mode SCK1 input mode SCK1 output mode SCK1 input mode SCK1 output mode 1000 16000/fc 400 8000/fc – 50 100 200 200 100 200 100 Unit ns ns ns ns ns ns ns ns ns ns Note)The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL. Fig. 5. Serial transfer CH1 timing SC K1 SI1 SO 1 tKC Y tKL tKH 0.2VD D 0.8VD D tSIK tKSI tKSO Input data O utput data 0.2VD D 0.8VD D 0.2VD D 0.8VD D

– 18 – CXP82220/82224 (3) A/D converter characteristics VZT*1 VFT*2 tCONV tSAMP VREF VIAN IREF IREFS Ta = 25°C VDD = AVDD = 5.0V VDD = AVss = 0V Operation mode Sleep mode Stop mode 32kHz operation mode AV REF –10 4930 160/fADC *3 12/fADC *3 VDD – 0.5 Item Symbol Pin Condition Min. Typ. Max. Unit BitsResolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time Reference input voltage Analog input voltage AV REF current (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD , Vss = AVss = 0V reference) 150 5120 VDD AV REF 1.0 5050 0.6 LSB mV mV µs µs V V mA µA Analog input Linearity error 00H 01H FEH FFH Digital conversion value VZT VFT Fig. 6. Definitions of A/D converter terms AV REF AN0 to AN7 *1 VZT :Value at which the digital conversion value changes from 00H to 01H and vice versa. *2 VFT :Value at which the digital conversion value changes from FEH to FFH and vice versa. *3 fADC indicates the below values due to ADC operation clock selection (ADCS: Bit 6 of address 00F9H ). During PS2 selection, fADC = fc/2 During PS1 selection, fADC = fc

– 19 – CXP82220/82224 External interruption High, Low level width Reset input Low level width INT0 INT1 INT2 NMI/INT3 RST 8/fc µs µs Item Symbol Pins Condition Min. Max. Unit tIH tIL tRSL (4) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) 0.8VD D 0.2VD D tIH tIL IN T0 IN T1 IN T2 N M I/IN T3 (N M I specifies only for the falling edge) tIL tIH Fig. 7. Interruption input timing tR SL 0.2VD D R ST Fig. 8. RST input timing 0.2VD D 0.8VD D tC TH tC TL C TL Fig. 9. Other timing CLK input High, Low level width tCTH , tCTL CTL Item Symbol Pin Condition Min. Max. Unit ns (5) Others (Ta = –20 to +75°C, VDD = 4.5 to 5.0V, VSS = 0V reference) tsys = 2000/fc tsys + 200

– 20 – CXP82220/82224 Appendix /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines EXTAL XTAL C 1 C 2 (i) M ain clock /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines EXTAL XTAL C 2 (ii) M ain clock /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines TEX TX C 1 C 2 R d (iii) Sub clock C 1 Manufacturer MURATA MFG CO., LTD RIVER ELETEC CORPORATION KINSEKI LTD. CSA4.19MG CSA8.00MG CSA10.0MT CST4.19MGW * CST8.00MTW * CST10.00MTW * HC-49/U03 HC-49/U (-S) Model fc (MHz) 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 C 1 (pF) C 2 (pF) Circuit example (i) (ii) (i) Those marked with an asterisk (*) signify types with built-in ground capacitance (C1, C2). Item Contents Reset pin pull-up resistor High voltage drive output port pull-down Non-existent Non-existent Existent Existent Mask option table Fig. 10. Recommended oscillation circuit

– 21 – CXP82220/82224 Package Outline Unit: mm SO N Y C O D E EIAJ C O D E JED EC C O D E PAC KAG E M ATER IAL LEAD TR EATM EN T LEAD M ATER IAL PAC KAG E M ASS EPO XY R ESIN SO LD ER PLATIN G 42/C O PPER ALLO Y PAC KAG E STR U C TU R E 23.9 ± 0.4 Q FP-100P-L01 100PIN Q FP (PLASTIC ) 20.0 – 0.1 + 0.4 0.15 – 0.05 + 0.1 15.8 ± 0.4 17.9 ± 0.4 14.0 – 0.1 + 0.4 2.75 – 0.15 + 0.35 A 0.65 M0.13 Q FP100-P-1420 1.7g 100 80 51 0.3 – 0.1 + 0.15 D ETAIL A 0° to 10° 0.8 ± 0.2 (16.3) 0.150.1 – 0.05 + 0.2

Product Information

CXP-82220 specifications and overview.

Summary

CMOS 8-bit Single Chip Microcomputer

Description

The CXP82220/82224 is a CMOS 8-bit single chip microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time base timer, capture timer/counter, fluorescent display tube controller/driver, remote control reception circuit, CTL duty detection circuit, 14-bit PWM output, high-speed output circuit and other servo systems besides the basic configurations of 8-bit CPU, PROM, RAM, and I/O port.

Source title CXP-82220 Datasheet(PDF) - Sony Corporation

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