CXL5507M

CXL5507M SONY | Alldatasheet

Document overview

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• PDF pages: 9

Technical content

Features

• Single 5V power supply
• Low power consumption 50mW (Typ.)
• Built-in peripheral circuits Functions
• 453-bit CCD register
• Clock driver
• Auto-bias circuit
• Input clamp circuit
• Sample-and-hold circuit Structure CMOS-CCD Absolute Maximum Ratings(Ta = 25°C)
• Supply voltage V DD 6V
• Operating temperature Topr –10 to +60 °C
• Storage temperature Tstg –55 to +150 °C
• Allowable power dissipation PD CXL5507M 350 mW CXL5507P 480 mW Recommended Operating Condition (Ta = 25°C) Supply voltage V DD 5 ± 5% V Recommended Clock Conditions (Ta = 25°C)
• Input clock amplitude VCLK 0.3 to 1.0 Vp-p (0.5Vp-p typ.)
• Clock frequency f CLK 7.159090 MHz
• Input clock waveform Sine wave Input Signal Amplitude VSIG 500mVp-p (Typ.), 527mVp-p (Max.) (at internal clamp condition) – 1 – E90908A7X-PS Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. CXL5507M/P Blook Diagram and Pin Configuration(Top View) (S/H 1bit) CLK 1 2 3 4 578 CCD (453bit) VGAV DD AB V SS OUTVGB IN Output circuit Auto-bias circuit Timing circuitBias circuit Clock driver Bias circuit (A) Bias circuit (B) Clamp circuit CXL5507M 8 pin SOP (Plastic) CXL5507P 8 pin DIP (Plastic)

Electrical Characteristics

(Ta = 25°C, VDD = 5V, fCLK = 7.159090MHz, VCLK = 500mVp-p, sine wave) See "Electrical Characteristics Test Circuit" – 2 – CXL5507M/P Description of I/O Signals Input signals are low level clamped and output signals are inverted in relation to the input signals. Also, the clamp condition of input signals are controlled by VGB (Pin 2) conditions. Center biased to approx. 2.1V by means of the IC internal resistance (approx. 10kΩ ). In this mode, the input signal is limited to APL 50% and the maximum input signal amplitude is 200mVp-p. C lam p level Input w aveform O utput w aveform Pin Description Pin No. Symbol Description Impedance IN VGB OUT V SS CLK VGA V DD AB Signal input Gate control B Signal output GND Clock input Gate control A Power supply (5V) Auto-bias DC output > 10kΩ at no clamp 40 to 500Ω > 100kΩ 600 to 200kΩ I I O I O O I/O a a b c b b b 350 mA dB dB mVp-p dB Unit NoteMax.Min. Typ.Item Symbol Test condition SW condition a a a b b a a a b b a a a b b b a a b b b a a a b b a c a a a 3 4 5 200kHz, 500mVp-p, sine wave 200kHz ‹fi 2MHz, 150mVp-p, sine wave No signal input No signal input 5-staircase wave (For luminance signals only) IDD GL fg CP SN LIS LIL LIC Supply current Low frequency gain Frequency response S/H pulse coupling S/N ratio Linearity 2.1 2.1 Bias condition V1 (V)

– 3 – CXL5507M/P Notes (1) This is the IC supply current value during clock and signal input. (2) GL is the output gain of OUT pin when a 500mVp-p, 200kHz sine wave is fed to IN pin. GL = 20 log [dB] (3) Indicates the dissipation at 2MHz in relation to 200kHz. From the output voltage at OUT pin when a 150mVp-p, 200kHz sine wave is fed to IN pin, and from the output voltage at OUT pin when a 150mVp-p, 2MHz sine wave is fed to same, calculation is made according to the following formula. Input bias is tested at 2.1V. fg = 20 log [dB] (4) The internal clock component to the output signal during no-signal input and the leakage of that high harmonic component are tested. Input bias is tested at 2.1V. OUT pin output voltage [mVp-p] 500 [mVp-p] OUT pin otuput voltage (2MHz) [mVp-p] OUT pin output voltage (200kHz) [mVp-p] Test value (m Vp-p) (5) Input no signal noise components are tested with the video noise meter at BPF 10kHz to 3MHz. This is calculated from the output gain (GL), at the input of 200kHz, 500mVp-p and according to the following formula. S/N = –20

• Iog [dB] (6) Respective outputs are tested at the input of the 5-staircase waves seen in the figure below (Iuminance signals only) and calculated according to the formula below. (However, output signals become inverted with regards to input.) Noise (mVrms) 0.5
• 10 GL/20

40 IR E

100 IR E

LIS = × 100 [% ]Vs Va LIL = × 100 [% ]Vp Va LIC = × 100 [% ]Vc Va

– 4 – CXL5507M/P (0.5Vp-p typ.) 2fsc (7.159090M H z) sine w ave Clock

– 5 – CXL5507M/P Electrical Characteristics Test Circuit AB VD D VG A C LK 1000p 1000p 3.3µ 0.1µ C LK 2fSC (7.159090M H z) 0.5Vp-p sine w ave IN VG B O U T VSS a b SW 4 a b 1M1k SW 2 b SW 1 c a b d a SW 5 2.1k 2 3 4 567 b c N ote) × 3 BPF N ote) BPF frequency response 3M 7.2M Frequency [H z] 10k SW 3 a 1000p –50 [dB] O scilloscope Spectrum analyzer N oise m eter 200kH z 500m Vp-p sine w ave 200kH z 150m Vp-p sine w ave 2M H z 150m Vp-p sine w ave 5-staircase w ave (Lum inance signals only)

– 6 – CXL5507M/P Application Circuit 1000p3.3µ 0.1µ1µ 2fSC 0.5Vp-p sine w ave 8 1012 2 3 4 Input LPF 2.2k 2.2k 2.2k O utput PN P: 2SA1175 D elay tim e 140ns 1000p 2.2k N PN : 2SC 403 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 7 – CXL5507M/P Example of Representative Characteristics 54.75 0 5.25 54.75 0.5 1.5 –0.5 5.25 54.75 32 5.25 54.75 –1.5 –0.5 –2 5.25 54.75 10 5.25 54.75 50 5.25 Supply voltage [V] Supply current vs. Supply voltage Supply current [m Supply voltage [V] Low frequency gain vs. Supply voltage Low frequency gain [dB] Supply voltage [V] Frequency response vs. Supply voltage Frequency response [dB] Supply voltage [V] Linearity (LIS) vs. Supply voltage Linearity (LIS) [% Supply voltage [V] Linearity (LIC ) vs. Supply voltage Linearity (LIC) [% Supply voltage [V] Linearity (LIL) vs. Supply voltage Linearity (LIL) [%

– 8 – CXL5507M/P 20–20 0 70–10 0 10 30 40 50 60 0.5 1.5 –0.5 20–20 70–10 0 10 30 40 50 60 20–20 70–10 0 10 30 40 50 60 –1.5 –0.5 –2 20–20 70–10 0 10 30 40 50 60 10 20–20 70–10 0 10 30 40 50 60 20–20 70–10 0 10 30 40 50 60 Am bient tem perature [°C ] Supply current vs. A m bient tem perature Supply current [m Am bient tem perature [°C ] Low frequency gain vs. A m bient tem perature Low frequency gain [dB] Am bient tem perature [°C ] Frequency response vs. A m bient tem perature Frequency response [dB] Am bient tem perature [°C ] Linearity (LIS) vs. A m bient tem perature Linearity (LIS) [% Am bient tem perature [°C ] Linearity (LIC ) vs. A m bient tem perature Linearity (LIC) [% Am bient tem perature [°C ] Linearity (LIL) vs. A m bient tem perature Linearity (LIL) [%

– 9 – CXL5507M/P Package Outline Unit: mm SO N Y C O D E EIAJ C O D E JED EC C O D E PAC KAG E STR U C TU R E PAC KAG E M ATER IAL LEAD TR EATM EN T LEAD M ATER IAL PAC KAG E M ASS EPO XY R ESIN SO LD ER PLATIN G 42/C O PPER ALLO Y 8PIN SO P (PLASTIC ) 6.1 + 0.4 – 0.1 5.3+ 0.3 – 0.1 1.85 + 0.4 – 0.15 0.1 + 0.2 – 0.05 0.2 + 0.1 – 0.050.45 ± 0.1 1.27 7.9 ± 0.4 6.9 0.5 ± 0.2 0.24 M 0.1g SO P-8P-L01 SO P008-P-0300 8 5 0.15 SO N Y C O D E EIAJ C O D E JED EC C O D E PAC KAG E STR U C TU R E PAC KAG E M ATER IAL LEAD TR EATM EN T LEAD M ATER IAL PAC KAG E M ASS EPO XY R ESIN SO LD ER PLATIN G C O PPER ALLO Y 8PIN D IP (PLASTIC ) 9.4 – 0.1 + 0.4 2.54 1 4 1.2 ± 0.15 0.5 ± 0.1 3.0 M IN 0.5 M IN 3.7 – 0.1 + 0.4 7.62 6.4 – 0.1 + 0.3 0.25 – 0.05 + 0.1 0° to 15° 0.5g D IP-8P-01 D IP008-P-0300 CXL5507M CXL5507P