CXL5001M

CXL5001M SONY | Alldatasheet

Document overview

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• PDF pages: 8

Technical content

Features

• Low power consumtion 80mW (Typ.)
• Small size package (8-pin SOP, DIP)
• Low differential gain DG = 3% (Typ.)
• Input signal ampiitude 180 IRE (= 1.28Vp-p, Max.)
• Low input clock amplitude operation 150mVp-p (Min.)
• Built-in peripheral circuits (clock driver, timing generator, autobias, and output circuits) Functions
• 680-bit CCD register
• Clock drivers
• Autobias circuit
• Sync tip clamp circuit
• Sample and hold circuit Structure CMOS-CCD Absolute Maximum Ratings(Ta = 25°C)
• Supply voltage V DD 11 V
• Supply voltage V CL 6V
• Operating temperature Topr –10 to +60 °C
• Storage temperature Tstg –55 to +150 °C
• Allowable power dissipation PD CXL5001M 350 mW CXL5001P 480 mW Recommended Operating Conditions Supply voltage V DD 9 ± 5% V VCL 5 ± 5% V Recommended Clock Conditions
• Input clock amplitude V CLK 150mVp-p to 1.0Vp-p (250mVp-p typ.)
• Clock frequency f CLK 10.7MHz – 1 – E50799A78-PS Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. CXL5001M/P CXL5001M 8 pin SOP (Plastic) CXL5001P 8 pin DIP (Plastic)

– 2 – CXL5001M/P Blook Diagram V SS V CL CLK IN AUTO FEED 680-BIT SH IFT R EG ISTER D U TY C O N TR O L C IR C U IT φ1 φ2 AU TO BIAS C IR C U IT C LAM P C IR C U IT OUT C LO C K D R IVER S AM P S/H AM P AM P 678 V DD ref. (1 BIT) φ2φ1 Pin Description Pin No.Symbol Description Impedance [Ω ] V SS VCK CLK VDD GND 5V power supply Clock input 9V power supply > 100k Pin No.Symbol Description Impedance [Ω ] OUT FEED AUTO IN Signal output Feedback DC output Autobias DC output Signal input 600 to 1k > 100k 10k > 100k

– 3 – CXL5001M/P

Electrical Characteristics

(Ta = 25°C, VDD = 9.0V, VCL = 5.0V, fCLK = 10.7MHz, VCLK = 250mVp-p sine wave, See "Electrical characteristics measuring circuit") Item Symbol Measuring condition SW conditionsMeasuring point Min. Typ. Max. Unit 1 2 mA mA dB dB deg Vp-p dB V V V V 1.28 6.5 6.5 3.3 3.7 –2.1 5.0 5.0 2.3 2.7 –3.0 3.5 3.5 1.3 1.7 S a a b a a a a a a a b, c e f d d a 250kHz, 1.28Vp-p, sine wave input 250kHz, 1.28Vp-p, sine wave input IG = 20 log (Output voltage [Vp-p] / 1.28 [Vp-p]) Dissipation at 3.5MHz in relation to 250kHz fG = 20 log (V 3.58MHz/ V250kHz) (Note 1) 5-staircase wave input Y = 140 IRE (=1.0Vp-p) Measure S point with vector scope (Note 2) S: Input = 250kHz, 1.0Vp-p output (Vp-p) N: Input = DC ground output (mVrms) 250kHz, 1.28Vp-p, sine wave input I DD ICL IG fG DG DP VIN-AC S/N VIN-AC VAUTO-DC VFEED-DC VOUT-DC Supply current Insertion gain Frequency response Differential gain Differential phase Allowable input amplitude Noise Output DC voltage

– 4 – CXL5001M/P LPF SW 2 a b VBIAS N ote 3) 0.01µF C LK fC LK = 10.7M H z VC LK = 250m Vp-p sine w ave 0.01µF 0.1µF SW 1 0.1µF 1M Ω 250kH z, 1.28Vp-p sine w ave 250kH z, 300m Vp-p sine w ave 3.58M H z, 300m Vp-p sine w ave 5-staircase w ave G round 250kH z, 1.0Vp-p sine w ave 5.1k BPF N ote 4) V1 V2 Vector scope S VSS VCL CLK VDD IN AUTO FEED OUT C XL5001M /P 5678 42 31 100k Electrical CharacteristicsMeasuring Circuit

– 5 – CXL5001M/P Note 1) Frequency response measuring condition V3.58MHz (Output signal voltage [Vp-p] at 3.58MHz input) V250kHz (Output signal voltage [Vp-p] at 250kHz input) Set Pin 8 (IN) voltage [V] = VIN-DC + 640mV. 3.58M H z, 300m Vp-p sine w ave 250kH z, 300m Vp-p sine w ave 640m V (adjust w ith VBIAS) VIN -D C [V] Note 2) Differential gain and differential phase measuring condition 1H 63.5µs

40 IR E

140 IR E (1.0Vp-p) C hrom a 40 IR E 5-staircase w ave signal D G and D P are m easured at output S point by vector scope. Note 3) LPF frequency response 0 5.8 10.7 Frequency [M H z] –50 [dB] (D elay tim e 140ns) Note 4) BPF frequency response 0 4.1M 10.7M Frequency [H z] –50 [dB] 20050

– 6 – CXL5001M/P Application Circuit L. P. F D elay tim e = 140ns C XL5001M /P 0.01µF C LK fC LK = 10.7M H z VC LK = 250m Vp-p sine w ave 0.01µF 0.1µF C om posite video signal input 0.1µF 1M Ω 5.1k 5678 1H delay signal output 0.01µF 47µF 0.01µF 47µF 2SA1175 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. fG – Frequency response [dB] Frequency response vs. A m bient tem perature –20 Ta – Am bient tem perature [°C ] 0 20 40 60 Input = 300m Vp-p 3.58M H z, sine w ave 0 fG – Frequency response [dB] Frequency response vs. Supply voltage VC L – Supply voltage [V] 4.7 5.0 5.3 Input = 300m Vp-p 3.58M H z, sine w ave fG – Frequency response [dB] Frequency response vs. Supply voltage 8.5 9.0 9.5 Input = 300m Vp-p 3.58M H z, sine w ave VD D – Supply voltage [V] Ta – Am bient tem perature [°C ] –2IG – Insertion gain [dB] Insertion gain vs. A m bient tem perature 0 60 Input = 1.28Vp-p 250kH z, sine w ave –20 20 40 Example of Representative Characteristics

– 7 – CXL5001M/P –2IG – Insertion gain [dB] Insertion gain vs. Supply voltage VC L – Supply voltage [V] 4.7 5.0 5.3 Input = 1.28Vp-p 250kH z, sine w ave IG – Insertion gain [dB] Insertion gain vs. Supply voltage VD D – Supply voltage [V] 8.5 9.0 9.5 Input = 1.28Vp-p 250kH z, sine w ave DG – Differential gain [% D ifferential gain vs. A m bient tem perature –20 Ta – Am bient tem perature [°C ] 20 60 0 40 DG – Differential gain [% D ifferential gain vs. Supply voltage VC L – Supply voltage [V] 4.7 5.35.0 0DG – Differential gain [% D ifferential gain vs. Supply voltage VD D – Supply voltage [V] 8.5 9.59.0 Frequency response 10k Gain [dB] 100k 1M Frequency [H z]

– 8 – CXL5001M/P Package Outline Unit: mm SO N Y C O D E EIAJ C O D E JED EC C O D E PAC KAG E STR U C TU R E PAC KAG E M ATER IAL LEAD TR EATM EN T LEAD M ATER IAL PAC KAG E M ASS EPO XY R ESIN SO LD ER PLATIN G 42/C O PPER ALLO Y 8PIN SO P (PLASTIC ) 6.1 + 0.4 – 0.1 5.3+ 0.3 – 0.1 1.85 + 0.4 – 0.15 0.1 + 0.2 – 0.05 0.2 + 0.1 – 0.050.45 ± 0.1 1.27 7.9 ± 0.4 6.9 0.5 ± 0.2 0.24 M 0.1g SO P-8P-L01 SO P008-P-0300 8 5 0.15 CXL5001M SO N Y C O D E EIAJ C O D E JED EC C O D E PAC KAG E STR U C TU R E PAC KAG E M ATER IAL LEAD TR EATM EN T LEAD M ATER IAL PAC KAG E M ASS EPO XY R ESIN SO LD ER PLATIN G C O PPER ALLO Y 8PIN D IP (PLASTIC ) 9.4 – 0.1 + 0.4 2.54 1 4 1.2 ± 0.15 0.5 ± 0.1 3.0 M IN 0.5 M IN 3.7 – 0.1 + 0.4 7.62 6.4 – 0.1 + 0.3 0.25 – 0.05 + 0.1 0° to 15° 0.5g D IP-8P-01 D IP008-P-0300 CXL5001P