CXL1517M

CXL1517M SONY | Alldatasheet

Document overview

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Technical content

Features

• Single 5V power supply
• Low power consumption (Typ.) CXL1517M 120mW CXL1518M 75mW
• Built-in peripheral circuits
• Built-in CDS (Correlated Double Sampling) circuit Functions
• Clock driver
• Autobias circuit (Center and black)
• Pedestal clamp circuit
• CDS circuit
• Overflow prevention circuit Absolute Maximum Ratings(Ta = 25°C)
• Supply voltage V DD 6V
• Operating temperature Topr –10 to +65 °C
• Storage temperature Tstg –55 to +150 °C
• Allowable power dissipation PD 500 mW Recommended Operating Voltage Range (Ta = 25°C) Supply voltage V DD 4.6 to 5.25 V – 1 – E91777A78-PS Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. CXL1517M/1518M 20 pin SOP (Plastic) Structure CMOS-CCD Item Symbol VL VH fCL fCL Min. VSS 0.7 · VDD Typ. 7.16 4.77 Max. 0.3 · VDD VDD Unit V V MHz MHz Remarks NTSC: 455f H CCIR: 454fH NTSC: 910fH /3 CCIR: 908fH /3 Clock voltage Low Clock voltage High Clock frequency CXL1517M CXL1518M

– 2 – CXL1517M/1518M Block Diagram and Pin Configuration(Top View) 1416 17 1 V DD ABC N V DD ABOVF V DD V GG IN -B IN -A ABBL V SS XDL1 XDL2 V SS V SS CDS CLP A.B. BLAC K C D S O U TPU T C IR C U ITC LP D L C D S O U TPU T C IR C U ITC LP C D S O U TPU T C IR C U ITC LP C LP PU LSE G EN . O VER FLO W PR EVEN TIO N C IR C U IT PO TEN TIAL C O N TR O L C D S TIM IN G G EN ER ATO R 1315 O U T-C O U T-A O U T-B IN -C PG . G EN . PG . G EN . PG . G EN . PR EC H AR G E D R AIND R IVER A.B. C EN TER A (n bit) D L B (n bit) D L C (n + 1 bit)5 10 11 201VSS IN -B ABBL VD D IN -C C LP VD D O U T-C VG G IN -A ABC N VD D XD L1 XD L2 VSS VSS O U T-A C D S ABO VF O U T-B

– 3 – CXL1517M/1518M Pin Description Pin No. Symbol I/O Description Comment VSS IN-B ABBL V DD IN-C CLP VDD OUT-C V GG OUT-B OUT-A CDS V SS VSS XDL2 XDL1 V DD ABCN ABOVF IN-A I O I I O O O O O I I O O I GND Signal input B channel (Y) Autobias DC output for Y signal Power supply Signal input C channel (Y) Clamp pulse input Power supply Signal output C channel Output circuit bias DC output Signal output B channel Signal output A channel DC output for CDS GND GND Clock pulse input 2 Clock pulse input 1 Power supply Autobias DC output for C signal Autobias DC output for overflow prevention circuit Signal input A channel (C) Analog Black level bias Analog Black level bias at no clamp > 100k > 100k Output circuit Output circuit Timing > 100k > 100k Timing Center level bias Center level bias at no clamp > 100k

– 4 – CXL1517M/1518M

Electrical Characteristics

fCL = 7.16MHz (CXL1517M)Ta = 25°C, VDD = 5.0V, VSS = 0V fCL = 4.77MHz (CXL1518M) Item Autobias center level Autobias black level Overflow prevention circuit Autobias level CDS source level Output circuit bias level Current * supply Insertion gain Frequency * response Linearity The insertion gain difference between channels Linearity difference between channels Cross-talk between channels ABCN ABBL ABOVF CDS V GG IDD IG fG Lin. ∆LBC CRT Symbol Test point SW conditions Bias conditions SW1 a a a a a b b b c b b b b b a a a b b b b a a a a a a a to c a to c a to c a to c a a a a a a a a a a b SW2 SW3 SW4 to 6 E1 Min. 4.2 3.9 2.6 1.2 0.3 –4.5 –1.5 –1.8 4.6 4.3 3.0 2.3 0.8 –3.5 –0.4 –0.8 4.8 4.5 3.3 3.5 3.0 V V V V V mA dB dB Typ. Max. Conditions 20 log 20 log Note 1) Note 2) Note 3) Note 4) Ratings Unit CXL1517M CXL1518M CXL1517M CXL1518M Bch fi Cch Output amplitude (mVp-p) Input amplitude (SIN 100kHz, 100mVp-p) A fi V1 B, C fi V2 + 0.25V fl A fi V1 B, C fi V2 + 0.25V Output amplitude (SIN 1MHz, 100mVp-p) Output amplitude (SIN 100kHz, 100mVp-p) * Standard values are different between CXL1517M and CXL1518M.

– 5 – CXL1517M/1518M Notes) 1) Linearity testing For A channel, set input bias to ABCN – 0.2V first, and then set it to ABCN and ABCN + 0.2V. Then input a sine wave of 100kHz and 100mVp-p, and compare the three output amplitudes. For B channel and C channel, set input bias to ABBL + 0.45V first, and then set it to ABBL + 0.25V and ABBL + 0.05V. Then input a sine wave of 100kHz and 100mVp-p, and compare the three output amplitudes. The maximum output amplitude for the respective A, B and C channels is taken as Sout max and the minimum output amplitude as Sout min. The linearity of the respective channels is defined as: Lin. = · 200 [%] 2) Calculation of insertion gain difference As the maximum insertion gain among A, B and C channels is taken as Gmax and the minimum as Gmin, the insertion gain difference between channels ∆G as: ∆G = |1 – 10 ( )|· 100 [%] 3) Calculation of linearity difference Define B channel linearity as LB and C channel linearily as LC we obtain the difference ∆LBC as: ∆LBC = |LB – LC |[%] 4) Cross-talk calculation CRTa :The cross-talk value of A channel when B and C channels are input OUT A-a :The output value of A channel when A channel is input SW3-a, SW4-a, SW5, 6-b OUT A-bc :The output value of A channel when B and C channels are input (Cross-talk component) SW3-a, SW4-b, SW5, 6-a CRTa = · 100 [%] Clock Waveform Timing Sout max – Sout min Sout max + Sout min Gmax – Gmin OUT A-bc OUT A-a 10ns 10% 50% 90% XD L1 (52.5) ∗ 87.5ns (140) ∗ 210ns 10% 50% 90% 10% 50% 90% 10% 50% 90% XD L2 ∗ The value in brackets is for C XL1517M . (52.5) ∗ 87.5ns 10ns 17.5ns 10ns 10ns

– 6 – CXL1517M/1518M 10k 10k10k V2 A1 a a a b b b SW 4SW 5SW 6 N o signal (G N D ) 100kH z, 100m Vp-p sine w ave 1M H z, 100m Vp-p sine w ave ab cSW 1 VD D 3.3k 3.3k 3.3k L.P.F b a c SW 3 16V a bE1 VD D 16V 16V 16V XD L SW 2 16V XD L VD D VD D 2 3 4 5 6 9 10 1112131415161819 VD D 3.3k 3.3k 3.3k 16V 16V 1µ 16V 16V XD L 16V XD L VD D VD D O utput A O utput B O utput C 0.1µ 16V 100p 47µ 16V VD DInput A 4.7µ 16V 100p C LP input VD DInput C VD D 4.7µ 16V 100p 0.1µ 16V Input B 3 4 5 6 10 1112131415161819 972 0.1µ 16V Electrical Characteristics Test Circuit Application Circuit Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 7 – CXL1517M/1518M Package Outline Unit: mm SO N Y C O D E EIAJ C O D E JED EC C O D E SO P-20P-L01 SO P020-P-0300 PAC KAG E STR U C TU R E PAC KAG E M ATER IAL LEAD TR EATM EN T LEAD M ATER IAL PAC KAG E M ASS C O PPER ALLO Y SO LD ER PLATIN G EPO XY R ESIN 0.3g 20PIN SO P (PLASTIC ) 12.45 – 0.1 + 0.4 20 11 0.45 ± 0.1 1.27 101 5.3 – 0.1 + 0.3 7.9 ± 0.4 6.9 0.2 – 0.05 + 0.1 0.5 ± 0.2 0.1 – 0.05 + 0.2 1.85 – 0.15 + 0.4 0.15 0.24 M