CXL1501

CXL1501M SONY | Alldatasheet

Document overview

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• PDF pages: 12

Technical content

Features

• Single power supply 5V
• Low power consumption 225mW (Typ.)
• Built-in peripheral circuits
• Completely adjustment free
• Built-in quadruple progression PLL circuit
• For NTSC signals Functions
• 1H comb filter output
• Dropout compensation (D.O.C) output
• Delay time matching through output (THR)
• PLL circuit (quadruple progression)
• Clock driver
• Autobias circuit
• Sync tip clamp circuit
• Sample and hold circuit Structure CMOS-CCD Absolute Maximum Ratings(Ta = 25°C)
• Supply voltage V DD 6V
• Operating temperature Topr –10 to +60 °C
• Storage temperature Tstg –55 to +150 °C
• Allowable power dissipation PD 500 mW Recommended Operating Conditions (Ta = 25°C) Supply voltage V DD 5 – 5% V Recommended Clock Conditions (Ta = 25°C)
• Input clock amplitude V CLK 0.4 to 1.0 Vp-p (0.5Vp-p Typ.)
• Clock frequency f CLK 3.579545 MHz
• Input clock waveform sine wave Input Signal Amplitude VSIG 571 mVp-p (Max.) – 1 – E71050-PS Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. CXL1501M 30 pin SOP (Plastic)

– 2 – CXL1501M Block Diagram and Pin Configuration (Top View) 2 3 6 7 8 9 10 11 12 13 14 15 1617181920212223242627282930 Phase comparator VSS CCD2 ADJC ABN CCD3 NC VDD VSS NC ABP VGGA YD VSS VGGB Y-YD CCD1 VSS VCO IN PC OUT VDD CLK VSS NC VCO OUT NC ADJY VDD TH VSS VSS D IH + D D Bias circuit (A) Bias circuit (B) VCO 1/4 divider Clock driver Autobias circuit (N) Autobias circuit (P) 4 Output circuit, S/H circuit Output circuit, S/H circuit Output circuit, S/H circuit

– 3 – CXL1501M Pin Description Pin No. Symbol I/O Description V SS CCD2 ADJC ABN CCD3 NC V DD VSS NC ABP VGGA YD V SS VGGB Y-YD V SS VSS TH V DD ADJY NC VCO OUT NC V SS CLK V DD PC OUT VCO IN V SS CCD1 I O O I O O O O O O O O I O I I GND Signal input 2 (Reverse phase signal) Forward phase CCD bias DC output Reverse phase autobias DC output Signal input 3 (Forward phase signal) 5V power supply (For clock driver) GND Forward phase autobias DC output Gate bias (A) DC output D.O.C signal output (Reverse phase signal) GND Gate bias (B) DC output Comb filter signal output GND GND THR signal output (Forward phase signal) 5V power supply (For analog) Reverse phase CCD bias DC output VCO output GND Clock input 5V power supply (For digital) Phase comparator output VCO input GND Signal input 1 (Reverse phase signal) Impedance (Ω ) > 100k (at no clamp) 600 to 2k 2k to 20k > 100k (at no clamp) 2k to 20k 2k to 10k 40 to 500 2k to 10k 40 to 500 40 to 500 600 to 2k 4k to 40k 2k to 5k > 100k > 100k (at no clamp)

– 4 – CXL1501M Item Symbol Test conditions*1 SW conditions Min. Typ. Max. Unit Note Supply current Low frequency gain High frequency gain Frequency response Differential gain Differential phase S/H pulse coupling S/N ratio IDD GLT GLC GLD GHT GHC GHD fT fc fD DGT DGC DGD DPT DPC DPD VPT VPC VPD SNT SNC SND 196.678kHz 500mVp-p sine wave 3.579545MHz 150mVp-p sine wave 196.678kHz ‹fi 3.579545MHz 150mVp-p sine wave 5-staircase wave* 5-staircase wave*7 No-signal input No-signal input*9 a a a a c c c b ‹fi c b‹fi c b‹fi c f f f f f f a a a a a a a a a a a a a a a a b b b b b b a a a a a a a a a a a a a a a a b b b b b b a a a a a a a a a a a a a a a a b b b b b b a a a a b b b b b b a a a a a a b b b a a a a a a a b b b b b b a a a a a a b b b a a a a a a a b b b b b b a a a a a a b b b a a a a b c a b c a b c a b c a b c a b c a b c b b b b b b b b b c c c c c c a a a d d d Bias conditions* 2 (V) VBIAS1 VIT –0.25 VIT –0.25 VIT VIC –0.25 VIC –0.25 VIC VID +0.25 VID +0.25 VID +0.5 –5.0 –6.5 –2.5 –3.0 –4.5 –1.5 –56 –1.0 –2.5 –0.5 350 –52 mA dB dB dB degree mVp-p dB VBIAS2 VBIAS3

Electrical Characteristics

(Ta = 25°C, VDD = 5V, fCLK = 3.579545MHz, VCLK = 500mVp-p sine wave) See the Electrical Characteristics Test Circuit.

– 5 – CXL1501M Item Symbol Test conditions*1 SW conditions Min. Typ. Max. Unit Note Chroma comb depth min. gainC-CD 3.579545MHz 200mVp-p sine wave 3.587412MHz 200mVp-p sine wave d ‹fi e a a a b b b b b Bias conditions*2 (V) VBIAS1 VBIAS2 VBIAS3

– 6 – CXL1501M TH pin output voltage [mVp-p] 500 [mVp-p] Notes) *1 Adjust the output amplitude of the inversion and the non-inversion amplifiers in the signal input block to an equal value, as well as the phase difference to a precise 180°. Also set the clock and input signal frequency accurately.

2 VIT, VIC and VID are defined as follows:

VIT, VIC and VID are input signal clamp levels. They clamps the Video signal sync tip level. They are the pin voltages at no-input signal for pins 30, 2 and 5, respectively. Testing of VIT, VIC and VID is executed with a voltmeter under the following SW conditions: As VIT, VIC and VID differ with each IC, they are to be tested respectively. 3 This is the IC supply current value during clock and signal input. *4 GLT, GLC and GLD are output gains of TH, Y-YD, and YD pins when a 500mVp-p, 196.678kHz sine wave is simultaneously fed to CCD1, CCD2, and CCD3 pins respectively. (Example of calculation) GLT = 20 log [dB] Item VIT VIC VID b b b b b b b b b a a a a a a a a a SW conditions Test point 2 3 4 5 6 7 8 9 10 11 2 5 L1501 Input (CCD1) Input (CCD2) Input (CCD3) VIT VIC VID

– 7 – CXL1501M TH pin output voltage (3.579545MHz) [mVp-p] TH pin output voltage (196.678kHz) [mVp-p] *5 GHT, GHC, and GHD are output gains of TH, Y-YD and YD pins when a 150mVp-p, 3.579545MHz sine wave is simultaneously fed to CCD1, CCD2, and CCD3 pins respectively. Bias at input (V BIAS1, VBIAS2 and VBIAS3) is tested respectively at VIT – 0.25V, VIC – 0.25V and VID + 0.25V. (Example of calculation) GHT = 20 log [dB] 6 Indicates the dissipation at 3.579545MHz in relation to 196.678kHz. From the output voltage at TH, Y-YD and YD pins when a 150mVp-p, 196.678kHz sine wave is simultaneously fed to CCD1, CCD2 and CCD3 pins, and from the output voltage at TH, Y-YD and YD pins when a 150mVp-p, 3.579545MHz sine wave is simultaneously fed to same, calculation is made according to the following formula. The input block bias for V BIAS1, VBIAS2 and VBIAS3 is tested at VIT – 0.25V, VIC – 0.25V and VID + 0.25V, respectively. (Example of calculation) fT = 20 log [dB] *7 The differential gain (DG) and the differential phase (DP), when the 5-staircase wave in the following figure is fed, are tested with a vector scope: CCD3 pin input waveform (the input waveform of CCD1 and CCD2 pins is the inverted waveform of the figure above.) *8 The internal clock component to the output signal during no-signal input and the leakage of that high harmonic component are tested. The input block bias is tested at VITV, VICV, and VID + 0.5V. TH pin output voltage [mVp-p] 150 [mVp-p] 1H 63.56µs 500mV 143mV 357mV 143mV Test value [mVp-p]

– 8 – CXL1501M Y-YD pin output voltage (3.587412MHz) [mVp-p] Y-YD pin output voltage (3.579545MHz) [mVp-p] *9 The noise level of output signal at no-input signal is tested with a video noise meter in the Sub Carrier Trap mode at BPF 100kHz to 4MHz. Vn [Vrms] The signal component is determined either by testing the output voltage (the same test system as that of noise level) at input of 357mVp-p, 196.678kHz, or by performing calculation from the values of GLT, GLC, and GLD in accordance with the following formula. Vs [Vp-p] (Example of Vs calculation) V S-T = 0.357 · 10 (VS-T: TH output voltage) (Example of S/N ratio calculation) SNT = 20 log [dB]

10 C-CD is calculated in accordance with the following formula from the Y-YD pin output voltage when a

200mVp-p, 3.579545MHz sine wave is simultaneously fed to CCD1, CCD2 and CCD3 pins and from the Y- CD pin output voltage when a 200mVp-p, 3.587412MHz sine wave is simultaneously fed to same. The input block bias is set to VIT – 0.3V, VIC – 0.3V and VID + 0.3V, respectively. C-CD = 20 log [dB] 0.4Vp-p to 1.0Vp-p (0.5Vp-p Typ.) fsc (3.579545MHz) sine wave Vn-T (noise component) [Vrms] VS-T (signal component) [Vp-p] GLT CLOCK

– 9 – CXL1501M Application Circuit 1µ1µ 0.01µ3.3µ 2 4 6 7 8 9 10 14 15 17181920212324252627282930 120 82k 4.7µ 0.01µ3.3µ 0.1µ fSC 0.5Vp-p sine wave 1.2k 0.01µ 3.3µ 1.2k 1.2k 1.8k 4fsc 1.8k 2SC403 When using pin 22 (4 × fsc output) Transistor used PNP : 2SA1175 YD output (Reverse phase signal) Y-YD output TH output (Forward phase signal) CCD1 input (Reverse phase signal) CCD2 input (Reverse phase signal) CCD3 input (Forward phase signal) Composite video signal input 11 12 13 2.2µ Signal output Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Electrical Characteristics Test Circuit 1µ1µ 0.01µ3.3µ 2 4 5 6 7 8 9 10 11 12 13 15 1718192021222324252627282930 1 NC ADJC ABN CCD3 NC VDD VSS NC ABP VGGA YD VSS VGGB Y-YD CCD1 VSS VCO IN PC OUT VDD CLK VSS NC VCO OUT NC ADJY VDD TH VSS VSS 120 82k 0.01µ3.3µ 0.1µ2.2µ CLK fSC (3.579545MHz) 0.5Vp-p 1.2k 0.01µ 3.3µ 1.2k 1.2k a c Oscilloscope Spectrum analyzer Vector scope Noise meter LPF ∗1 ×3 BPF a b c d SW7 ab 1MSW6 ab SW5 ab 51k 51k 51k –1 a b SW4 –1 a b SW3 –1 a b SW2 SW1 196.678kHz 500mVp-p sine wave 196.678kHz 150mVp-p sine wave 3.579545MHz 150mVp-p sine wave 3.579545MHz 200mVp-p sine wave 3.587412MHz 200mVp-p sine wave 5-staircase wave a b c d e f 4.7µ SW8 SW9 b 0 6M 14.3M Frequency [Hz] –50 [dB] ∗1) LPF frequency response 0 6M 14.3M Frequency [Hz] –50 [dB] ∗2) BPF frequency response 200 CCD2 VBIAS1V BIAS3 VBIAS2 sine wave

– 10 – CXL1501M Low frequency gain vs. Supply voltage 4.75 5.0 5.25 VDD – Supply voltage [V] Low frequency gain [dB] VDD – Supply voltage [V] High frequency gain [dB] High frequency gain vs. Supply voltage 4.75 5.0 5.25 Frequency response [dB] Frequency response vs. Supply voltage 4.75 5.0 5.25 VDD – Supply voltage [V] Differential gain [%] Differential gain vs. Supply voltage VDD – Supply voltage [V] 4.75 5.0 5.25 02 0 4 0 6 0 Ta – Ambient temperature [°C] Low frequency gain vs. Ambient temperature Low frequency gain [dB] 02 0 4 0 6 0 Ta – Ambient temperature [°C] High frequency gain vs. Ambient temperature High frequency gain [dB]

– 11 – CXL1501M Frequency response (TH, YD Output) 10k Gain [dB] 100k 1M f – Frequency [Hz] 02 0 Ta – Ambient temperature [°C] Frequency response [dB] Frequency response vs. Ambient temperature 40 60 Ta – Ambient temperature [°C] Differential gain [%] Differential gain vs. Ambient temperature 20 40 60 Chroma comb depth min. gain vs. Supply voltage –10 –20 –30 V DD – Supply voltage [V] Chroma comb depth min. gain [dB] 4.75 5.00 5.25 –40 –50 Ta – Ambient temperature [°C] 02 0 4 0 6 0 Chroma comb depth min. gain vs. Ambient temperature –10 –20 –30 Chroma comb depth min. gain [dB] –40 –50 –10 –20 –30 Gain [dB] –40 Chroma comb response (Y-YD Output) 3.57 3.58 f – Frequency [MHz] 3.59

– 12 – CXL1501M Package Outline Unit: mm PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS SONY CODE EIAJ CODE JEDEC CODE

42 ALLOY

30PIN SOP (PLASTIC) 18.8 – 0.1 + 0.4 30 16 1 15 0.45 ± 0.1 1.27 7.6 – 0.1 + 0.3 10.3 ± 0.4 9.3 ± 0.3 0.15 – 0.05 + 0.1 0.5 ± 0.2 0.1 – 0.05 + 0.2 2.3 – 0.15 + 0.4 SOP-30P-L01 SOP030-P-0375 M0.24 0.7g 0.15