CXK77V3211Q SONY | Alldatasheet

Document overview

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Technical content

Features

  • Fast address access times and High frequency operation
  • 5V tolerant inputs except I/O pins
  • A FT pin for pipelined or flow-thru architecture
  • A LBO mode pin as burst control pin (i486/Pentium™ and Linear burst sequence)
  • Single +3.3V power supply
  • Common data inputs and data outputs
  • All inputs and outputs are LVTTL compatible
  • Four Individual BYTE WRITE enables, GLOBAL WRITE and BYTE WRITE ENABLE
  • Three Chip Enables for simple depth expansion
  • One cycle output disable for both pipelined and flow-thru operation
  • Internal input registers for address, data and control signals
  • Self-timed WRITE cycle
  • Write pass through capability
  • High 30pF output drive capability at rated access time
  • A ZZ pin for powerdown
  • 100-lead QFP package for high density, high speed operation – 1 – CXK77V3211Q -12/14 E95721-PS 32768-word by 32-bit High Speed Synchronous Static RAM Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. 100 pin QFP (Plastic) Symbol -12 -14 Access 12ns 14ns Cycle 60MHz 50MHz Access 7ns 8ns Cycle 75MHz 66MHz Flow-through Pipeline +10% – 5%

– 2 – CXK77V3211Q Block Diagram 15 13 15 A1 A0 A1' A0' Byte 1 Write Driver Byte 2 Write Driver Byte 3 Write Driver Byte 4 Write Driver Address Register Mux Mux A1 A0 q0Load Counter Byte 1 Write Register Byte 2 Write Register Byte 3 Write Register Byte 4 Write Register 8 8 32K × 8 × 4 Memory Array Sense Amps 32 32 Enable Register Input Registers Output Buffers Output Registers DQ1 DQ32 POWER DOWNZZ FT OE CE2 CE2 CE BW1 BW2 BW3 BW4 BWE SGW ADSP ADSC LBO ADV CLK A0 to A14

– 3 – CXK77V3211Q Pin Configuration 4039383736353431 32 33 41 42 43 44 45 46 47 48 49 50 81828384 88 87 86 85 899010 099 98 97 96 95 94 919293 1NC DQ17 DQ18 VDD q Vssq DQ19 DQ20 DQ21 DQ22 Vssq VDD q DQ23 DQ24 FT VDD NC Vss DQ25 DQ26 VDD q Vssq DQ27 DQ28 DQ29 DQ30 Vssq VDD q DQ31 DQ32 NC LBO A5 A4 A3 A2 A1 A0 NC NC Vss NC NC A10 A11 A12 A13V DD A14 NC NC NC DQ16 DQ15 VDD q Vssq DQ14 DQ13 DQ12 DQ11 Vssq VDD q DQ10 DQ9 Vss NC VDD ZZ DQ8 DQ7 VDD q Vssq DQ6 DQ5 DQ4 DQ3 Vssq VDD q DQ2 DQ1 NC A6 A7 CE CE2 BW4 BW3 BW2 BW1 CE2V DD CLK SGWBWE OE ADSCADSPV SS ADVA8 A9

– 4 – CXK77V3211Q Pin Description Symbol I/O Description A0 to A14 BW1, BW2, BW3, BW4 CLK CE CE2 CE2 OE ADV ADSP ADSC NC DQ1 to DQ32 BWE SGW FT LBO ZZ V DD VSS VDD q VSS q I I I I I I I I I I I/O I I I I I Supply Supply Supply Supply Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. Synchronous Individual Byte Write Enables: These active LOW inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of CLK. A BYTE WRITE enable is LOW for a WRITE cycle and HIGH for a READ cycle. BW1 controls DQ1 to DQ8. BW2 controls DQ9 to DQ16. BW3 controls DQ17 to DQ24. BW4 controls DQ25 to DQ32. Data I/O are tristated if any of these four inputs are LOW. Clock: This signal latches the address, data, chip enable, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. Synchronous Chip Enable: This active LOW input is used to enable the device and conditions internal use of ADSP. This input is sampled only when a new external address is loaded. Synchronous Chip Enable: This active LOW input is used to enable the device. This input is sampled only when a new external address is loaded. This input can be used for memory depth expansion. Synchronous Chip Enable: This active HIGH input is used to enable the device. This input is sampled only when a new external address is loaded. This input can be used for memory depth expansion. Output Enable: This active LOW asynchronous input enables the data I/O output drivers. Synchronous Address Advance: This active LOW input is used to advance the internal burst counter, controlling burst access after the external address is loaded. A HIGH on this pin effectively causes wait status to be generated (no address advance). This pin must be HIGH at the rising edge of the first clock after an ADSP cycle is initiated if a WRITE cycle is desired (to ensure use of correct address). Synchronous Address Status Processor: This active LOW input interrupts any ongoing burst, causing a new external address to be latched. A READ is performed using the new address, independent of the byte write enables and ADSC but dependent upon CE2 and CE2. ADSP is ignored if CE is HIGH. Power down state is entered if CE2 is LOW or CE2 is HIGH. Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst and causes a new external address to be latched. A READ or WRITE is performed using the new address if all chip enables are active. Power- down state is entered if one or more chip enables are inactive. No Connect: These signals are not internally connected. SRAM Data I/O: Byte 1 is DQ1 to DQ8; Byte 2 is DQ9 to DQ16; Byte 3 is DQ17 to DQ24; Byte 4 is DQ25 to DQ32. Input data must meet setup and hold times around the rising edge of CLK. Byte Write Enable: This active low input enables individual byte to write. Global Write: This active low input enables to write all bytes. Flow Through: This active low input selects flow through output. Linear Burst: This active high input selects interleaved burst sequence. ZZ: This active high input enables the device in powerdown mode. Power Supply: +3.3V Ground: GND Isolated Output Buffer Supply: +3.3V Isolated Output Buffer Ground: GND +10% – 5% +10% – 5%

– 5 – CXK77V3211Q Interleaved Burst Sequence Table First access, latch external address Second access (first burst address) Third access (second burst address) Fourth access (third burst address) A14 to A2 A14 to A2 latched A14 to A2 latched A14 to A2 latched A14 to A2 latched A1 latched A1 latched A1 latched A0 latched A0 latched A0 Operation X...X00 X...X01 X...X10 X...X11 First address X...X01 X...X00 X...X11 X...X10 Second address X...X10 X...X11 X...X00 X...X01 Third address X...X11 X...X10 X...X01 X...X00 Fourth address Address used Interleaved Burst Address Table X...X00 X...X01 X...X10 X...X11 First address Initial WRITE cycle, all bytes Address = A (n – 1), data = D (n – 1) Initial WRITE cycle, all bytes Address = A (n – 1), data = D (n – 1) Initial WRITE cycle, all bytes Address = A (n – 1), data = D (n – 1) Initial WRITE cycle, one byte Address = A (n – 1), data = D (n – 1) All L All L All L One L Initial READ cycle Register A (n), Q = D (n – 1) No new cycle Q = D (n – 1) No new cycle Q = HIGH-Z No new cycle Q = D (n – 1) for one byte L H H H H H H H L L H L Read D (n) No carryover from previous cycle No carryover from previous cycle No carryover from previous cycle Operation BWs Operation CE BWs OE Operation Previous cycle Present cycle Next cycle X...X01 X...X10 X...X11 X...X00 Second address X...X10 X...X11 X...X00 X...X01 Third address X...X11 X...X00 X...X01 X...X10 Fourth address Linear Burst Address Table Pass-Through Truth Table Note) Previous cycle may be either BURST or NONBURST cycle.

– 6 – CXK77V3211Q Linear burst Interleaved burst Function L H or NC LBO Flow-thru output Pipelined output Function L or NC H FT Powerdown to ISB1 Active Function H L or NC ZZ READ READ WRITE byte 1 WRITE all bytes WRITE all bytes Function H H H H L SGW H L L L X BWE X H L L X BW1 X H H L X BW2 X H H L X BW3 X H H L X BW4 Partial Truth Table Absolute Maximum Rating (Ta = 25°C, GND = 0V) Supply voltage Input voltage Power dissipation Operating temperature Storage temperature Soldering temperature · time Item V DD VIN PD Topr Tstg Tsolder Symbol –0.5 to +4.6 –0.5 to 6 (Max.) 1.6 0 to +70 –55 to +150 235 · 10 Rating V V W °C · sec Unit DC Recommended Operating Conditions (Ta = 0 to +70°C, GND = 0V) Supply voltage Input high voltage Input low voltage Item V DD VIH VIL Symbol 3.135 2.0 –0.3 Min. 3.3 Typ. 3.63 5.5 0.8 Max. V V V Unit 1, 2 1, 2 Note Note) 1. All voltage referenced to V SS (GND). 2. Overshoot: VIH ≤ VDD + 2.0V for t ≤ tKC /2. Undershoot: VIL‡ –2.0V for t ≤ tKC /2.

– 7 – CXK77V3211Q DC and Operating Characteristics (VDD = 3.3V , GND = 0V, Ta = 0 to +70°C) Input leakage current Output leakage current Operating supply current Static CMOS supply current Standby current Deselect supply current Output High voltage Output Low voltage ILI ILO IDD -0MHz IDD -66MHz IDD -80MHz IDD1 -0MHz ISB1 ISB2 -0MHz ISB2 -66MHz ISB2 -80MHz VOH VOL VIN = GND to VDD Output disabled, VOUT = GND to VDD Device selected; all inputs ≤ VILor ‡ VIH; cycle time ‡ tKC min, VDD = MAX; outputs open All inputs ≤ 0.2V or ‡ VDD – 0.2V ZZ ‡ VDD –0.2V, All inputs ≤ 0.2V or ‡ VDD – 0.2V Device deselect I OH = –5.0mA IOL = 5.0mA 2.4 210 250 120 140 0.4 µA µA mA mA mA mA V V Item Symbol Test condition Min. Max. Unit +10% – 5% DC and Operating Characteristics for Special Modes-pins These Mode-pin input buffers (FT, ZZ, LBO) have special self-bias circuit to protect against coupling noise when these pins are not connected during normal operations. Mode-pins FT ZZ LBO ‡ VIH + 0.5V < VIH + 0.5V ‡ VIL < VIL < 1µA > 10KΩ to VSS < 1µA > 10KΩ to VDD VIN ILI

– 8 – CXK77V3211Q Item Flow-thru Pipeline Clock to output valid Clock to output invalid Clock to output in Low-Z Clock cycle time Clock to output valid Clock to output invalid Clock to output in Low-Z Clock cycle time Clock HIGH time Clock LOW time Clock to output in High-Z OE to output valid OE to output in Low-Z OE to output in High-Z Setup time Hold time ZZ setup ZZ hold ZZ recovery tKQ tKQX tLZ2 tKC tKQ tKQX tLZ2 tKC tKH tKL tHZ 2 tOE tOLZ 2 tOHZ 2 tS tH tZZS 3 tZZH 3 tZZR Symbol -12 -14 Unit Min. Max. Min. Max. 16.6 3.5 3.5 2.5 0.5 2.5 0.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1. All parameters are specified over the range 0 to 70°C. 2. These parameters are sampled and are not 100% tested. 3. Signal is asynchronous, however, to be recognized on any given clock the signal must meet specified setup and hold times. +10% – 5%

– 9 – CXK77V3211Q I/O capacitance (Ta = 25°C, f = 1MHz) Item Symbol Test condition Typ. Max. Unit Input capacitance I/O capacitance C IN C OUT VIN = 0V VI/O= 0V pF pF This parameter is sampled and is not 100% tested. AC Test Conditions (VDD = 3.3V , Ta = 0 to +70°C) Item Input pulse high level Input pulse low level Input rise time Input fall time Input reference level Output reference level Output load conditions Conditions V IH = 2.8V VIL= 0V tr = 1V/ns tf = 1V/ns 1.4V 1.4V Fig. 1 and Fig. 2 I/O Zo = 50Ω 50Ω VT = 1.4V ∗30pF Output load (1) Fig. 1. I/O ∗5pF 217Ω 295Ω +3.3V Output load (2) Fig. 2. * Include scope and jig capacitance. * Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. * Output load (2) for tLZ and tHZ , tOLZ and tOHZ . +10% – 5%

– 10 – CXK77V3211Q Truth Tables Deselected cycle, power-down Deselected cycle, power-down Deselected cycle, power-down Deselected cycle, power-down Deselected cycle, power-down READ cycle, begin burst READ cycle, begin burst WRITE cycle, begin burst READ cycle, begin burst READ cycle, begin burst READ cycle, continue burst READ cycle, continue burst READ cycle, continue burst READ cycle, continue burst WRITE cycle, continue burst WRITE cycle, continue burst READ cycle, suspend burst READ cycle, suspend burst READ cycle, suspend burst READ cycle, suspend burst WRITE cycle, suspend burst WRITE cycle, suspend burst None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current Operation Address used H L L L L L L L L L X X H H X H X X H H X H CE X X H X H L L L L L X X X X X X X X X X X X CE2 X L X L X H H H H H X X X X X X X X X X X X CE2 X L L H H L L H H H H H X X H X H H X X H X ADSP L X X L L X X L L L H H H H H H H H H H H H ADSC X X X X X X X X X X L L L L L L H H H H H H ADV X X X X X X X L H H H H H H L L H H H H L L BWx X X X X X L H X L H L H L H X X L H L H X X OE L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H CLK High-Z High-Z High-Z High-Z High-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z D D DQ Note) 1. X means "don't care". H means logic HIGH. L means logic LOW. BWx = L means any one or more byte write enable signals (BW1, BW2, BW3, BW4) are LOW. BWx = H means all byte write enable signals are HIGH. 2. BW1 enables writes to Byte 1 (DQ1 to DQ8). BW2 enables writes to Byte 2 (DQ9 to DQ16). BW3 enables writes to Byte 3 (DQ17 to DQ24). BW4 enables writes to Byte 4 (DQ25 to DQ32). 3. All inputs except OE must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 4. Wait states are inserted by suspending burst. 5. For a write operation following a read operation, OE must be HIGH before the input data required setup time and held HIGH throughout the input data hold time. 6. This device contains circuitry that will ensure the outputs will be in HIGH-Z during power-up. 7. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals LOW for the subsequent L-H edge of CLK. Refer to WRITE timing diagram for clarification.

– 11 – CXK77V3211Q Read Timing (Pipeline) /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines tKC tKH tKL /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines tS tH /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines tHtS /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines A2 A3 tHtS /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines tHtS /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines tHtS /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines tHtS (∗3) tHZ tKQ tKQX tOLZ tOHZtOE tLZ tKQ Single READ Burst READ Burst wrap around to its initial state.(∗1) High-Z ADV suspends burst Burst continued with new base address /LiteDiagLines DON'T CARE UNDEFINED Q (A1) Q (A2) Q (A2 + 3) Q (A2) Q (A2 + 1) A1 A4 CLK ADSP BW1 to BW4 CE (∗2) ADV OE Q ADSC ADDR. Deselect cycle *1 Q (A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst address following A2. *2 CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE is LOW. *3 On deselect cycle, Q is tri-stated immediately on the same cycle CE is LOW.

– 12 – CXK77V3211Q Write Timing (Pipeline) /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines tKC tKH tKL /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines tS tH /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines tHtS /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines tHtS /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines tHtS /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines tHtS /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines tS Burst READ High-Z ADV suspends burst /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines DON'T CARE UNDEFINED CLK ADSP CE (∗2) ADV OE /LiteDiagLines /LiteDiagLines/LiteDiagLines ADSC extends burst /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines tHtS tHtS /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines BYTE WRITE signal are ignored for first cycle when ADSP intiates burst ADSC /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLinesBW1 to BW4 (∗4) /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines (∗3) D tH /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLinesD (A1) D (A2) D (A2 + 1) D (A2 + 1) D (A2 + 2) D (A2 + 3) D (A3) D (A3 + 1) D (A3 + 2) Q tOHZ Single WRITE Burst WRITE Extended Burst WRITE A1 A2ADDR. (∗1) *1 Q (A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst address following A2. *2 CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW. *3 OE must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output data contention for the time period prior to the byte write enable inputs being sampled. *4 ADV must be HIGH to permit a WRITE to the loaded address.

– 13 – CXK77V3211Q Read/Write Timing (Pipeline) /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines tKC tKH tKL tS tH tHtS /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines tHtS /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Burst READ High-Z /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines DON'T CARE UNDEFINED CLK CE (∗2) ADV OE ADSC BW1 to BW4 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines D Q (A1)Q tOHZ Single WRITE /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines ADSP /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines tS tH D (A2) Q (A2) Q (A3) Q (A3 + 1) Q (A3 + 2) High-Z Single READ Pass Through READ tKQ tLZ tS tH tOLZ tKQ A1 A2 A3ADDR. /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines (∗1) *1 Q (A3) refers to output from address A3. Q (A3 + 1) refers to output from the next internal burst address following A3. *2 CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.

– 14 – CXK77V3211Q Read Timing (Flow-Thru) /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines tKC tKH tKL /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines tS tH /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines tHtS /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines A2 A3 tHtS /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines tHtS /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines tHtS /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines tHtS tHZ tKQ tKOX tOLZ tOHZtOE tLZ tKQ Single READ Burst READ Burst wrap around to its initial state.(∗1) High-Z ADV suspends burst /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines DON'T CARE UNDEFINED CLK ADSP BW1 to BW4 CE (∗2) ADV OE Q ADSC Q (A1) Q (A2) Q (A2 + 3) Q (A2) Q (A2 + 1) A1ADDR. /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Q (A3) *1 Q (A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst address following A2. *2 CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE is LOW.

– 15 – CXK77V3211Q Write Timing (Flow-Thru) /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines tKC tKH tKL /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines tS tH /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines tHtS /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines tHtS /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines tHtS /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines tHtS /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines tS Burst READ High-Z ADV suspends burst /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines DON'T CARE UNDEFINED CLK ADSP CE (∗2) ADV OE /LiteDiagLines /LiteDiagLines/LiteDiagLines ADSC extends burst /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines tHtS tHtS /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines BYTE WRITE signal are ignored for first cycle when ADSP intiates burst ADSC /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLinesBW1 to BW4 /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines D tH /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLinesD (A1) D (A2) D (A2 + 1) D (A2 + 1) D (A2 + 2) D (A2 + 3) D (A3) D (A3 + 1) D (A3 + 2) Q tOHZ Single WRITE Burst WRITE Extended Burst WRITE A1 A2ADDR. (∗1) (∗4) (∗3) *1 Q (A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst address following A2. *2 CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW. *3 OE must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output data contention for the time period to the byte write enable inputs being sampled. *4 ADV must be HIGH to permit a WRITE to the loaded address.

– 16 – CXK77V3211Q Read/Write Timing (Flow-Thru) /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines tKC tKH tKL tS tH tHtS /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines tHtS /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Burst READ (∗1) High-Z /LiteDiagLines /LiteDiagLines DON'T CARE UNDEFINED CLK CE (∗2) ADV OE ADSC BW1 to BW4 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines D Q (A1)Q tOHZ Single WRITE /LiteDiagLines/LiteDiagLines ADSP /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines tS tH D (A2) Q (A3) Q (A3 + 2) Q (A3 + 3) High-Z Single READ tS tH tOLZ tKQ A1 A2 A3ADDR. /LiteDiagLines /LiteDiagLines/LiteDiagLines Q (A3 + 1) *1 Q (A3) refers to output from address A3. Q (A3 + 1) refers to output from the next internal burst address following A3. *2 CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.

– 17 – CXK77V3211Q ZZ Timing tKC tKH tKL tS tH CLK ADSC Snooze /LiteDiagLines/LiteDiagLinesADSP /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines tZZS tZZH tZZR ZZ /LiteDiagLines /LiteDiagLines/LiteDiagLines

– 18 – CXK77V3211Q Package Outline Unit: mm SONY CODE EIAJ CODE JEDEC CODE PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER QFP-100P-L02 ∗QFP100-P-1420-B 23.2 ± 0.2 DETAIL A (15.4) 0.1 – 0.05 0.25 15.6 ± 0.2 (0.8) 0.9 – 0.15 + 0.131.6 ± 0.2 0.1 0.65 0.1 M0.12 (0.3) 0.32 – 0.07 + 0.08 (0.15)0.17 – 0.03 + 0.04 DETAIL B ∗20.0 ± 0.1 1 30 5180 100 2.75 – 0.15 + 0.35 B A 0° to 10° 100PIN QFP (PLASTIC) 1420 1.7g + 0.15 NOTE: Dimension “∗” does not include mold protrusion.