CXK5T81000ATN SONY | Alldatasheet

Document overview

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Technical content

Features

  • Extended operating temperature range: –25 to +85°C
  • Wide supply voltage range operation: 2.7 to 3.6V
  • Fast access time: (Access time) 3.0V operation -10LLX 100ns (Max.) -12LLX 120ns (Max.) 3.3V operation -10LLX 85ns (Max.) -12LLX 100ns (Max.)
  • Low standby current: 28µA (Max.)
  • Low data retention current: 24µA (Max.)
  • Low power data retention: 2.0V (Min.)
  • Package 8mm · 13.4mm 32 pin TSOP package Function 131072-word · 8-bit static RAM Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. V CC GND CE1 CE2 Row DecoderBuffer I/O Buffer A10 A11 A13 A15 A16 A14 A12 OE WE I/O Gate Column Decoder Memory Matrix 1024 × 1024 I/O1 I/O8 Buffer Buffer Block Diagram Preliminary CXK5T81000ATN 32 pin TSOP (Plastic) CXK5T81000AYN 32 pin TSOP (Plastic)

– 2 – CXK5T81000ATN/AYN Address input Data input output Chip enable 1, 2 input Write enable input Output enable input Power supply Ground No connection Symbol Description Supply voltage Input voltage Input and output voltage Allowable power dissipation Operating temperature Storage temperature Soldering temperature · time V CC VIN VI/O PD Topr Tstg Tsolder –0.5 to +4.6 –0.5* 1 to VCC + 0.5 –0.5*1 to VCC + 0.5 0.7 –25 to +85 –55 to +150 235 · 10 V V V W °C · s Item Symbol Rating Unit Absolute Maximum Ratings (Ta = 25°C, GND = 0V) *1 VIN, VI/O= –3.0V Min. for pulse width less than 50ns. Pin Description A0 to A16 I/O1 to I/O8 CE1, CE2 WE OE V CC GND NC CXK5T81000ATN (Standard Pinout) CXK5T81000AYN (Mirror Image Pinout) A11 A13 WE CE2 A15 VCC NC A16 A14 A12 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A3A4 A12 A14 A16 NC V CC A15 CE2 WE A13 A11 Pin Configuration (Top View) H L L L L H H H H L H H L Not selected Not selected Output disable Read Write High Z High Z High Z Data out Data in I SB1 , ISB2 ISB1 , ISB2 ICC1 , ICC2 , ICC3 ICC1 , ICC2 , ICC3 ICC1 , ICC2 , ICC3 CE1 CE2 OE WE Mode I/O pin V CC Current Truth Table DC Recommended Operating Conditions (Ta = –25 to +85°C, GND = 0V) *2 VIL= –3.0V Min. for pulse width less than 50ns. Supply voltage Input high voltage Input low voltage Item Symbol Min. V CC = 2.7 to 3.6V V CC = 3.3V ± 0.3V Typ. Max. Unit VCC VIH VIL 2.7 2.4 –0.3*2 3.3 3.6 V CC + 0.3 0.4 Min. Typ. Max. 3.0 2.2 –0.3*2 3.3 3.6 V CC + 0.3 0.6 V

– 3 – CXK5T81000ATN/AYN Input leakage current Output leakage current Operating power supply current ILI ILO ICC1 VIN = GND to VCC CE1 = VIH or CE2 = VILor OE = VIH or WE = VIL VI/O= GND to VCC CE1 = VIL, CE2 = VIH VIN = VIH or VIL IOUT = 0mA 10LLX 12LLX –25 to +85°C –25 to +70°C +25°C —51 0 0.48 0.12 1.4 µA mA 25* 35*3 µA µA mA mA mA Item Symbol Min. Typ.*1 Max. UnitTest conditions

Electrical Characteristics

  • DC Characteristics (VCC = 2.7 to 3.6V, GND = 0V, Ta = –25 to +85°C) *1 VCC = 3.3V, Ta = 25°C *2 ICC2 = 30mA for 3.3V operation (VCC = 3.3V ± 0.3V) *3 ICC2 = 40mA for 3.3V operation (VCC = 3.3V ± 0.3V) Average operating current Output high voltage Output low voltage Standby current ICC2 ICC3 ISB1 ISB2 VOH VOL Min. cycle duty = 100% I OUT = 0mA Cycle time 1µs duty = 100% I OUT = 0mA CE1 ≤ 0.2V CE2 ‡ Vcc – 0.2V VIL≤ 0.2V VIH ‡ Vcc – 0.2V CE1 = VIH or CE2 = VIL IOL = 2.0mA 2.4 0.4 V V IOH = –2.0mA CE2 ≤ 0.2V CE1 ‡ Vcc – 0.2Vor{CE2 ‡ Vcc – 0.2V Input capacitance I/O capacitance Item Symbol Test conditions Min. Typ. Max. Unit C IN C I/O pF pF VIN = 0V VI/O= 0V I/O capacitance (Ta = 25°C, f = 1MHz) Note)This parameter is sampled and is not 100% tested.

– 4 – CXK5T81000ATN/AYN AC Characteristics

  • AC test conditions (Ta = –25 to +85°C) TTL C L
  • Test circuit Input pulse high level Input pulse low level Input rise time Input fall time Input and output reference level -10LLX Output load conditions -12LLX V IH = 2.4V VIL= 0.4V tr = 5ns tf = 5ns 1.4V C L*1 = 100pF, 1TTL C L*1 = 100pF, 1TTL Item VCC = 2.7 to 3.6V Conditions VIH = 2.2V VIL= 0.6V tr = 5ns tf = 5ns 1.4V C L*1 = 30pF, 1TTL C L*1 = 100pF, 1TTL VCC = 3.3V ± 0.3V *1 C L includes scope and jig capacitances.

– 5 – CXK5T81000ATN/AYN

  • Read cycle (WE = “H”) *1 tHZ1 , tHZ2 and tOHZ are defined as the time required for outputs to turn to high impedance state and are not referred to as output voltage levels. *2 tWHZ is defined as the time required for outputs to turn to high impedance state and is not referred to as output voltage level.
  • Write cycle Item Symbol Min. Max. Min. Max. -10LLX VCC = 2.7 to 3.6V V CC = 3.3V ± 0.3V -12LLX Unit tRC tAA tCO1 tCO2 tOE tOH tLZ1 tLZ2 tOLZ tHZ1 *1 tHZ2 *1 tOHZ *1 100 100 100 100 120 120 120 120 Min. Max. Min. Max. -10LLX -12LLX 100 100 100 100 Read cycle time Address access time Chip enable access time (CE1) Chip enable access time (CE2) Output enable to output valid Output hold from address change Chip enable to output in low Z (CE1, CE2) Output enable to output in low Z (OE) Chip disable to output in high Z (CE1, CE2) Output disable to output in high Z (OE) ns ns ns ns ns ns ns ns ns ns Item Symbol Min. Max. Min. Max. -10LLX VCC = 2.7 to 3.6V V CC = 3.3V ± 0.3V -12LLX Unit tWC tAW tCW tDW tDH tWP tAS tWR tWR1 tOW tWHZ *2 100 120 100 100 Min. Max. Min. Max. -10LLX -12LLX 100 Write cycle time Address valid to end of write Chip enable to end of write Data to write time overlap Data hold from write time Write pulse width Address setup time Write recovery time (WE) Write recovery time (CE1, CE2) Output active from end of write Write to output in high Z ns ns ns ns ns ns ns ns ns ns ns

– 6 – CXK5T81000ATN/AYN

  • Read cycle (1) : CE1 = OE = VIL, CE2 = VIH, WE = VIH Address tAA tRC tOH Data out Previous data valid Data valid
  • Read cycle (2) : WE = VIH Address tAA tRC tLZ2 tOHZtOE tOLZ CE1 OE Data out High impedance Data valid tCO1 tHZ tLZ1 tHZ1 tHZ2 tCO2CE2 Timing Waveform

– 7 – CXK5T81000ATN/AYN

  • Write cycle (1) : WE control Address tAW tWC tCW tDH tWHZ tDW CE1 WE Data out High impedance Data valid tOW OE Data in tWR tAS tWP (∗1) tCW CE2 (∗2)( ∗2)
  • Write cycle (2) : CE1 control Address OE tWC tAW Data valid tAS tCW tWR1 tWP tDW tDH High impedance CE1 WE Data out Data in tCW CE2 (∗3)

– 8 – CXK5T81000ATN/AYN

  • Write cycle (3) : CE2 control Address OE tWC tAW Data valid tCW tWR1 tWP tDW tDH High impedance CE1 WE Data out Data in tAS tCW CE2 (∗3) *1 Write is executed when both CE1 and WE are at low and CE2 is at high simultaneously. *2 Do not apply the data input voltage of the opposite phase to the output while I/O pin is in output condition. *3 tWR1 is tested from either the rising edge of CE1 or the falling edge of CE2, whichever comes earlier, until the end of the write cycle.

– 9 – CXK5T81000ATN/AYN –25 to +85°C –25 to +70°C +25°C VCC = 2.0 to 3.6V*1 Chip disable to data retention mode Data retention voltage Data retention setup time Recovery time VDR ICCDR1 ICCDR2 tCDRS tR 2.0 0.4 0.48* 3.6 V µA µA ns ns Item Symbol Test conditions Min. Typ. Max. Unit Data Retention Characteristics (Ta = –25 to +85°C) *1 CE1 ‡ Vcc – 0.2V, CE2 ‡ Vcc – 0.2V (CE1 control) or CE2 ≤ 0.2V (CE2 control) *2 VCC = 3.3V, Ta = 25°C Data retention current VCC = 3.0V*1 Data retention waveform

  • Low supply voltage data retention waveform (1) (CE1 contol) VCC VIH VDR CE1 GND tCDRS Data retention mode CE1 ≥ VCC – 0.2V
  • Low supply voltage data retention waveform (2) (CE2 contol) tR Data retention mode tRtCDRS CE2 ≤ 0.2V VCC 2.7V VIL CE2 GND VDR 2.7V

Package Outline Unit: mm CXK5T81000ATN – 10 – CXK5T81000ATN/AYN CXK5T81000AYN SONY CODE EIAJ CODE JEDEC CODE PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING

42 ALLOY

∗8.0 ± 0.1 ∗11.8 ± 0.1 13.4 ± 0.3

1.2 MAX

0.5 0° to 10° 0.05 – 0.05 + 0.1 0.145 A 0.1 DETAIL A 0.2g NOTE: Dimension “∗” does not include mold protrusion. M0.08 0.50.2 32PIN TSOP (PLASTIC) TSOP-32P-L02 TSOP032-P-0813.4-C SONY CODE EIAJ CODE JEDEC CODE PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING ∗8.0 ± 0.1 ∗11.8 ± 0.1 13.4 ± 0.3 0.5 0° to 10° 0.05 – 0.05 + 0.1 0.145 A 0.1 DETAIL A 0.2g NOTE: Dimension “∗” does not include mold protrusion. M0.08 0.50.2 32PIN TSOP (PLASTIC) TSOP-32P-L02R TSOP032-P-0813.4-D