CXK5864BP SONY | Alldatasheet

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Technical content

Features

® Fast access time (Access time) CXK58648SP (XK58648M CXK5864BP/BSP/BM-70L, 70LL 70ns(Max.) 28 pin DIP (Plastic) 28 pin SOP (Plastic) CXKS864BP/BSP/BM-10L, 10LL_ 100ns(Max.) CXKS5864BP/BSP/BM-12L, 12LL 120ns(Max.) @ Low power operation : CXK5864BP/BSP/BM-7OLL, 10LL, 12LL ; Standby/Operation : 5 uW (Typ.) /40mW (Typ.) CXK5864BP/BSP/BM-7OL, 10L, 12L ; Standby/Operation : 10 uW (Typ.) /40mW (Typ.) Single power supply 5V: +5V + 10% Fully static memory «No clock or timing strobe required Function Equal access and cycle time 8,192-word x 8-bit static ®Common data input and output: three state output RAM * Directly TTL compatible : All inputs and outputs * Low voltage data retention : 2.0V (Min.) Structure Available in 28 pin 600mil DIP, 300mil DIP and 450mil SOP Silicon gate CMOS IC Block Diagram Pin Configuration Pin Description (Top View) ot ve ae B= Al2 ate » Bz {1/01 to a Data input output 2 oR weg B+ | CET, CE2 [Chip enable 1, 2 input oe an « o fies [OE [Output enable input | og fier |GND |Ground " = | =a B= [Nc [No conseston — see wo Faves 89720807 - st - 62 -

Absolute Maximum Ratings (Ta = 25°C, GND = OV) Supply voltage Voc Vv Input voltage Vw «| = 05* to Voc+05| Vv [input and output voltage | Vio Vv Allowable power dissipation | Po CARSE64BP/BSP 1.0 lw | xKE@640M * Vin, Vi7o=—3.0V Min. for pulse width less than 5Ons. Truth Table w [x [x x | Not seed | Hoh 2 ts te | [LH [ww | Outpat aeabie | Woh 2] ens ber | ee X:"H” or “L" DC Recommended Operating Conditions (Ta=0 to + 70°C, GND =OV) 5 | [tom | Smbot] Min] Typ] Max. _[ Un 45) 80 v theater vom [wef cee} ee | * Vi =-3.0V Min. for pulse width less than Ons. = 63 -

SONY.” 868878578

Electrical Characteristics

DC and operating characteristics (Vec = 5V + 10%, GND = OV, Ta=0 to + 70°C) | Win | Ty9 | Max | Vizo=GND to Veo Output leak current ho | CET =Vin or CE2=Vu or 500 | nA lour = OmA cues ns lea Duty ='100%, tour = Oma 50 | ma cE2 5 0.2V =L 60 | iae[CEt= vn or Gez=ve sp — | 01 | 2 | ma * Veo = BV, Ta = 25°C Pin capacitance (Ta = 25°C, f= 1MHz) Item Symbol | Test conditions Note) This parameter is sampled and is not 100% tested. AC characteristics @ AC test conditions (Vcc =5V + 10%, Ta=0 to + 70°C) Input pulse high level Vin = 2.2V Input pulse low level Vu =08V Input rise time _ ~__[tr=5ns : Input fall time tf = ns me Input and output reference level | 1.5V a Te ot * Ci includes scope and jig capacitances. — 64 -

@Read cycle [Min [Max | Min. Max | Min | Mos | Feed oyse time [we | 70 | — | 100) —] 120] — Tae | Address access time — | tux | —] 70 | —]J 100 | — | 120 | ns | Chip enable access time (CET, CE2) Ne =| || 100 | — [120 | ns | Output enable to output valid tor | | 35 | —| 50° ao Output hold from address change tow —T 10 | — Chip enable to output in lowZ | tir el — Tio !/— [10 || | (CEl, CE2) tuzz | amen fe Ts Ts |=[5 [= L @E) Chip disable to output in high Z ‘tHz1* | fice nee | ee fe jm fo slo | s [a Eee CEE EICICS % thai, tiza and ton are defined as the time at which the outputs become the high impedance state and are not referred to output voltage levels. eWrite cycle ttem Symbol -— Unit Min. Min. eave —— SE | Bl [Adress vali to end of wits | tw | 60 || 80 |—] a5 |—| ne] [chip enatio to end of wito | ow | 0 |—] 00 |—| e5 |—|re | [bets to wie tine oveing | tw 20 |—| © | —] 0 |—| re] [Bata hott trom wite me | m| 0 || 0 |—] 0 [—| ne [write pulse width | tw | 40 [— | 60 | 70 | — | os | [Adsross setup tne Siw | 0 [| 0 [| 0 [| oe | Pwrteroovery tne WE) we | 0 [| 0 [—T 0 [— | ne | Output active from end of write | tow 5 {—!s5 |—|s| “ns Write to output in high Z| twa* | O | 30 | 0 | 35 | 0 | 45 | ns | * twz is defined as the time at which the outputs become the high impedance state and are not referred to output voltage levels, - 65 -

Read cycle (1) : CET = OE = Vi, CE2= Vin, WE = Vin @ Read cycle (2) : WE = Vin ew XA ALLL cee LL /* cor EE e XA XLLLN oe Ht . ‘High impedance NZAZAN Write cycle (1) : WE control id AKNANNNNANNYSYSS ce LH YX oun OOOO "i manne S vo

SONY (CxXKS8848°/BSP/8M Write cycle (2) : CET control Aecrass o us ——— tens (02) a ce we tom ioe Ome out High impedance: © Write cycle (3) : CE2 control . CN e KANANANNNSY SKS S| eo NIANYXS AKL cea m \\K\\WK LLL ata oy | igh necanee Note) *1. Write is executed when both CET and WE are at low and CE2 is at high simultaneously. *2. twa is tested from either the rising edge of CET or the falling edge of CE2, whichever comes earlier, until the end of the write cycle. *3. Do not apply the data input voltage of the opposite phase to the output while the |/O pin is in output condition. - 67

SONY oxKS86¢8P/857 70M ees BBB’ BSP'OM Data Retention Characteristics (Ta=0 to+70°C) mbol est conditions Init Data retention are fas] — [os en] — los) fem [ova EES os eT Data retention Vee = 3.0V w lccore | Vec = 2.0 to 5.5V,*! uA Data retention | Chip disable to data ns setup time ORS | retention mode [Recovery we fm fas] —] Joe fn | * 1, CET 2 Vec ~ 0.2V, CE22 Vee — 0.2V [CET Control] or CE2$0.2V [CE2 Control] * 2. tac: Read cycle time Data Retention Waveform 1, CET control teons Data retention mode te Vee —S—} cel CEI 2 Vec-0.2V GND>+ 2-00 222 nnn sonree monn ennennnne vee eenec ee ceee cee ee eee 2. CE2 contro! v, Data retention mode AV oes yp CE2 OAV oo non nnn ag oat ON a SSeS - 68 -

SONY : jive Characteristics sy eran va not enpr Example of ane na ; J re Cech pea \\ce, |e = 12 ae i Ef PH ; oT AT ARTS rae i | | CR... 741 | fo | eos : Try i a reece EE rT LL r io L 1 i. Ft “° ° Ta- Ambient temperature - “ me Access time vs. Load capacitanc: Voc — Supply vol ; | — oe ; FH Mszeueas(m pate 2oza : arn cae PO ‘FEO : ATH pers ae ann it TTT} a ceseseee ee 8 ie i Takeo . SS se ‘Supply voltage j a ae he Po j HEE . oH PCP oe Poe | i LA tan, tc01, t002 PSS Poe - : SS peceseae i CCAS aeene aaa im ~ 3 ° Ta— Ambient temperature (°C)

SONY (CXKS5864BP//BSP/BM ‘Standby current vs. Supply voltage ‘Standby current vs. Ambient temperature > = 20) a a = 7 pote Ie : A PTO PCo-T To att

3 Le PZT

8B 20 3,0 40 $0 60 025 20 40 60 80 Vcc — Supply voltage (V) Ta— Ambient temperature (°C) Input voltage level vs. Supply voltage: Standby current vs. Ambient temperature 12 14) sCLELIELL ,CLELIIL cc oes] PRESS Same eS PCCereT PCCCRRER Le i CEP Peo Pee

2 CEE 1 CCE

45 475 50 525 55 ° 20 40 60 80 Vec ~ Supply voltage (V) Ta~ Ambient temperature (°C) Output high current vs. Output high voltage Output low current vs. Output low voltage P ; PCLT pL eT

2 Oe coer

eee 2 3 4 Ss ° Q2 04 06 os Vox — Output high voltage (V) Vou — Output low voitage (V) - 70 -

SONY (CxK58648P//BSP/BM Package Outline Unit : mm CXK5864BP 28 pin DIP (Plastic) 600mil 4.29 z ores? Bi ‘ asel i Fics as ast z ceed A Gere timeaee) CXKS864BSP 28 pin DIP (Plastic) 300mil 2.09 a asittf z 4 5 sl i a4 - oss a3 5. tos Ht [Sony wave[O1P-2ee-06 | 3] [eras wueleoieeze-r-o900-1] ears Gore cooelwo-p5@=a8 <1] “im CXK5864BM 28 pin SOP (Plastic) 450mil 0.7a soottt aatlts wes) | | Lostis ae J | Fy CUUERT THERESE I wwe] Ear axstits | ce Wn (7-1 o - 71 -