CXK5863AP-20

CXK5863AP SONY | Alldatasheet

Document overview

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Technical content

SONY. CXK5863AP/Ad 20/25/00 8192 word x 8-bit High Speed CMOS Static RAM Description . CXK5863AP CXKS5863AN CXK5863AP/AJ are 65,536 bits high speed 28 pin DIP (Plastic) 28 pin SOJ (Plastic) CMOS static RAMS organized as 8,192 words by B-bits and operate from a single 5V supply. These devices are suitable for use: in high speed applications such as cash memory. , Features Y Fast access time 20ns/25ns/30ns (Max.) Low power operation 250mW (Typ.) Single + 5V supply : 5V + 10% Fully static memory"-No clock or timing Structure strobe required Silicon gate CMOS IC Equal access and cycle time. Common data input and output three state Function output. 8192 word x 8-bit static RAM Directly TTL compatible all inputs and outputs. Full CMOS. Compatible with various types of packages CXK5863AP 300mil 28pin DIP package CXK5863AJ 300mil 28pin SOJ package Block Diagram Pin Configuration Pin Description : (Top View) Symbol| Description oem ad Ip.. [AOI |Address input 10 “ ow @ in 1 - — “o | owes eo PBccz 01 to Data input output “ Mo of pas 1708 ae aes! Bas CET, [Chip enable 1, 2 - | Pa Ba. [CE2 _ input ato wn tmnc “a Ber to od Face +5V Power supply cor a Co ae Br [GND [Ground * P| od FB vs NC. Non connection £89704A02 - ST AT ~ 82 -

SONY: OXKS6AP AJ See em Absolute Maximum Ratings (Ta = 25°C, GND=0v) Supply voltage = 0.5* to +7.0 Vv Input and: output voltage Lita Soe aaeencs | mop ees te * Voc, Vin, Vio=— 3.5V Min. for pulse width less than 20ns. Truth Table Mode 1/01 to 1/08 | Voc Current H | x | x | x [| Not selected | High Z Iser, [582 “x | ut |x [| x | Not selected “High Z Isar, Ise2 tu [-H | | H | Output disable | High Z| ‘tect, ca uf H Read “Data out leer, loca x: "Hor “L” DC Recommended Operating Conditions (Ta=0 to + 70°C, GND= OV) [tem Symbot | Min. | Typ. [Max | Unit | [Supeiv vote | ve | 45 | 80 | 55] v | 5 | [Inout Figh votes | vm | 22 | — | Veroa|v | [Inout tow votase [ve | -0as | — | oa Tv] * Vi_=—3.0V Min. for pulse width less than 20ns. wees — 83 -

SONY. CXKSBB3AP/AL

Electrical Characteristics

DC and operating characteristics (Vec = 5V + 10%, GND = OV, Ta=0 to + 70°C) ~20 = 25/- 30 Item Symbol Test condition — ~ — Unit Input leakage current | lu | Vin=GND to Veo | -1|——| 1 | -1 =| wa Vizo= GND to Vee, Output leakage ho | CET=Vm or CE2=Vn | -1|—/ 1 —] 1 }ua or OE = Vix or WE=Vu | | | CET = Vu, CE2= Vin, | Qpereting power loc! | Vin= Vix or Vit, —/ 50 | 80 50 | 80 | mA pely | four = OMA, | | , “TCyle=Min SSS T_T Average operating lece | Duty = 100%, —| 95 | 130 70 | 90 | mA current | tour = OmA | CET & Voc - 0.2V or | | 81 | Vin & Voc ~ 0.2V or | | Standby current | Vins 02V | | CET = Vin or CE2=Vn. | _ _ Ty. 'se2 | Viw= Vi or Vin - 25 | 10 [25 mA Output high voltage | Vow | lox =~ 4.0mA\\ 24 24|—|—jv Output low voitage | Vo. | lo. =8.0mA — —[—Toal v * Veo = 5V, Ta = 25°C (40 capacitance (Ta = 25°C, f= 1MHz) Item —_| Symbol | Test conditions Max, Input capacitance | Cn | Vin=O0V 7 [170 espscienee | Go |Wwo=ov | — 7 | oF | Note) This parameter is sampled and is not 100% tested. AC characteristics AC test conditions (Voc = 5V + 10%, Ta=0 to + 70%) Output Load (1) Output Load (2) “* Input pulse high level Vin = 3.0V [input rise me [= Sno | , 7 ” Sa Input and output 15V reference level Output load conditions | Fig 1 *2 for tu, tiza, tov, tHz1, taza, tonz, tow, twuz Fig. 1 - 84 -

SONY: XBR ZA 1) Read cycle Se Read cycle time we | 20 |] 25 |—| 30 | —| os | Address access time ta |—| 20 |—J 25 |—| 20 | ns | | Chip enable access time (CET) | teos__ || 20 |— | 25 [—| 30 | ns | Chip enable access time (CE2) tooe | —| 20 |—| 25 | —| 30 | ns | Output enable to output valid tor [| —]| 10 [—] 12 [—] 12 | os | Output hold from address change | tox =| 5 |—| 5 |—| 5 |——T ns Chip enable to output in low Z tu, I—| ns (CET, CE2) tu2* Chip disable to output in high Z j tezr*, ° 12 ns (CET, CE2) Ltee* | [one deabe io ovina mn Hoh 2H [wer [Ob e | 0] i] oo] mw | Chip enable to power up time (CET, CE2) | teu = Chip disable to power down time t (CET, CE2) ° ia 2) Write cycle i] _ Write cycle time — Ftne 20 | — | 28 |] 30 [Tne | | Address valid to end of wite | taw | 15 [| 20 |—/ 20 |—| ns | [ip enable to end ot wite Tew | 18. |= 20. | —| 20 [—| ne | | Data to write time overlap | tow | 10 |] 12 || 12 |] ns | | Data hold from write time tom | 0 [| 0 |) 0 [=I os | | Write pulse width ftw | 5 |] 20 || 20 |] rs | [Address set up tine tw [0 [=| 0 |—| 0 |—[ re | | Write recovery time (WE) tte | 0 || 0 || 0 [I os Write recovery time (CET, CE2) wwi_| 0 [lo [Jo [J ne Output active from end of write tow* | s |—|] [—| Wite 10 output in Figh Z lowe? [oft Lo [a2 | % Transition is measured +500mV from steady voltage with specified loading in Fig. 1-(2). This parameter is sampled and is not 100% tested. 85 -

SONY: CXKS883AP/AS Timing Waveform 1) Read cycle Read cycle (1) : CE1 = OE = Vu, CE2 = Vin, WE = Vin wee tOH © Read cycle (2) : WE= Viv te :OMMA tco1 tHZ1 ce2 LLL 2 YAN oe WANA wu Date sgn impedance KOS XK ov vai] vee nn —— , i si 2) Write cycle Write cycle (1) : WE control wo oe \\AAAAAAMAASANSA cer {ZF tow SANA TAS ‘we we ENN a - 86 -

SONY: CXKSBESAP/AS Write cycle (2) : CET control we ses —_ taw AS: tow twat [oy cez LLL JANA twe we XAAANA ALLL — tow 4 t0H Dots ou SOO ran impesance Write cycle (3) : CE2 control we oe AARAMAAAAAAMAYAR e Sb 5 | . : — ~ we KASS ALLL tow btn Date out rare NST igh impedance During 1/0 pins are in the output state, the data input signals of opposite phase to the output must not be applied. a _ 87 -

SONY: ‘CXKSBBSAP/Ad Package Outline Unit: mm CXK5863AP 28pin DIP (Plastic) 300mil 2.09 asic 33 fy ee a {less 233 Pies 3)"Q) 201 Z

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