CXK58256P-12L

CXK58256 SONY | Alldatasheet

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32K-word X 8 bit High Speed CMOS Static RAM Preliminary Description Package Outline Unit:_mm The CXK58256P/M is a 262,144 bits high speed cxksa2ser 28 Pin DIP CMOS static RAM organized as 32,768 words by 8 bits and operates from a single 5V supply. sot 2 The CXK58256P/M is suitable for use in high ft cooscenencnit speed and low power applications in which ° o_o . Sito 10° battory back up for nonvoltiliy is required. oO Features ai iD + Low power standby: 10uW(Typ.)—L-version S50pW(Typ.)—Standard Version Fa + Low power operation:40mW(Typ.)—L-version 3 50mW{Typ}-Standard Version + Fast access time: 100ns/120ns/150ns (Max.) es A + Single +5V supply aa + Fully static memory... No clock or timing pip-2er-04 strobe required + Equal access and cycle time cxksazeem ye PmurP + Common data input and output 3-state output + Low voltage data retention: 2.0V (Min.) snot is Directly TTL compatible: All inputs and lrvpougepeaaanit outputs 4 AORH ROAR AT} 3 tie gees. || | 32,768-word X 8 bit static RAM a | 4 THOOUOHOAOD Silicon gate CMOS IC Block Diagram comrrry om ep wep-20°-L05 ated TP eo a * a] Note) All Typical values are measured under the ae Tie | conditions 7 Vec=5.0V and Ta=25°C. —82-

(CXK6E256°/M SONY. Pin Configuration (TOP VIEW) neol +e AO tots Addhess input | arg — as Bas 1/01 to 1/08] Data Input Output me B a wa Bs | CE | Chip Enable input ag OE | WE | Write Enable input aw plato Output Enable Input xg Ba [08 [oun : se Bice Power Supply 02 31/06 vos fa 1/05 onoly (9/04 Absolute Maximum Ratings (Ta=25°C, GND=0V) Power Supply Voltage =0.5 t0 +7.0 Input Voltage Vin (Note) 0.6 to Vec+0.5 Input and Output Voltage Wo (Note) =0.5 to Vect+0.5 Allowable Power Dissipat cxxsezsep | 0 | jlowable Power Dissipation “oe CXK58256M Note) During transitions, the inputs may undershoot to —3V for period less than 5Ons. Truth Table [ce | oe [We | Mode | vo1w vos [ie] # |r| Oupur Osebie | High 2 | ec Teer] pepe fw [pea [pou [tect ce | Le [| x {it | wie [bin [tec tea _—| Note) X:“H” or “L” DC Recommended Operating Conditions (Ta=0 to +70°C, GND=0Vv) [tem Symbot [min [ typ. [Max | Unit | Power Supply Voroge | vec | 45 | so] 55 | v | Note) During transitions, the inputs may undershoot to —3V for period less than 50 ns. ~ 83 —

(©XK68256°/ SONY. DC and Operating Characteristics (Vec=5V410%, GND=OV, Ta=0 to +70°C) Symbol| Test condition 10/12/15 ~10V/12V15L [meee ea eae Le frowme ff | fl | Vi0=GND to Voi Said 2eooeoo or WE=ViL eer | [e]*|-|e] em Vin=ViH_ or Vit, Operating Power lour=OmA Vin=0.2V 7 or Vec—0.2V Operating Duty=100% Current lour=OmA | sey or i feeesone |= far | = foal [a [ison [ce-vm | = [oa] 3 | - [oa] 2 | ma | utput High omen" | vor fow-noma [2a | = | - | ae] =| = |v | Ww frome” | ve [warm [= | = [oe] = | = foe] v Capacitance {Ta=25°C, f=1 MHz) [tem | Teatconaivon] Symbot_[ win [Max [Unit | [input Cepactence | vwrov | ow [| - | 8 | oF | [inpwvOuputCepeciancs | worov | cm | =| 6 | oF | Note) This parameter is sampled and is not 100% tested. AC Characteristics + AC Test conditions (Vcc=5V+10%, Ta=0 to +70°C) [mm | Condition | [input Rise Time =i ans =| [input Fal Time =i ene | * Cu includes scope and jig capacitances. — 84—

omer ss—<CSsSSC‘CSSCSCSsi‘(CSC‘#WSSOONNS (1) Read Cycle CXK58256P/M | CXK58256P/M] CXK58256P/M ___ >See [Read Cycle Time | tee (| too | - | 120 | - | 150 | - | ns | [Aasross Access Time | wa | - | 100 | - | 120 - | 160 | vs | [Chip Enobie Access Time (@&| | eo | = | 100 | - | 120] - | 150] ne | [Output Enable to Output Valid [toe | - | so | - | 60 | = | 70 | ns | [Output Hold from Address Change| ton | 10 | - | io | - | to | - | ns | [Chip Enable to Outputintow2(c&| wz | 10 | - | 10 | - | to | = [ns | emerge fem | | fe |e | Le in Low Z (OE) in High Z (CE) in High Z (OE) (2) Write Cycle | SSeS Symbol | _—10/10L =12/12L =15/15L__| unit [write Cycle Time | twe | 100 | = | 120 | =| 160 [= ns | [Address Valid to End of write | ww | eo | — | 100 | - [100 | - | ns | [Chip Enable to End of Write | tew | 0 | - | 100 | — | 100 | — | ns | [oats 10 Wie Time Overy | ww | 40 | - | so | - | 0 | - | ne | [Osta Hold from Write Time | tom [| o [| - [| o | = [oo | = [ns | [Write Pulse width | twe | 70 | - [ eo | = | 90 | = | ns | [Address Set up Time | ws | 0 | = | o | = [oo | = [os | [Write Recovery Time (WE) | twa | o | - [| o | = | o [ = [ns | [Write Recovery Time (ce) | wm | 0 | - | o | - | o | = | as | [Output Active from End of Write | tow | 10 | - | 10 | - [10 | = | ns | [Write to Output in High Z| wwe | = [ 30 | = | 30 [ = | 40 | ns | 85 — ee

(CXK58256°/M SONY: Timing Waveform (1) Read Cycle * Read cycle No. 1 (CE=OE=Vi, WE=Vin} tac Address tAa ‘OH Dae Previous data valid Data valid + Read cycle No. 2 [WE=Vin] tAA = INN ALLL tco tz tz | me \\A\\S. ALLL own — : pete (2) Write Cycle * Write cycle No. 1 [WE control] ‘we acre a, saw WR m XYAAAAAAAAAAAAA we =o tOH in a, we kw Dour High impedance — 86 —

(CXKBB256°/M SONY. * Write cycle No. 2 [CE control] two sim co tas tcw a = mi to °* | a= oon SO ae igh impedance During I/O pins are in the output state, the data input signals of opposite phase to the output must not be applied. | -87— een pecans

i — (CxKS8256P/M SONYe Oxmeerrm Data Retention Characteristics (Ta=0 to 70°C) CXK58256P/M CXK58256P/M Item Test condition -10/12/15 =10LW/12Y15L Data Retention fam [wm || 0 [20] 20 [20 sol ss | Data Retention | tccom |veowaov "1 | — | 6 | soo[ - | 1 | so | pa | Data Retention Chip disable to Set up Time data retention mode| [Recovey Time | w_| fer = [= [wera] — [Poe | *7 1) CE=Vcc—0.2V *2 trc : Read Cycle Time Data Retention Waveform | tcons Data retention mode ta Vee —-— = Eve 02V GND -= = 22-22 = no anne eee mene eee tenet ces neces EE — 88 —