CXK1012P SONY | Alldatasheet
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SONY. CXK1012P 1024 -bit (128word x 8bit ) Non-volatile Memory TO rr. 2S eee Description Package Outline Unit: mm The CXK1012P is an electrically erasable 8 Pin DIP and programmable £7PROM of 128vordx 8 bit FS structure. It employg aon-volatile magry | a transistors of the HNOS type. For the bal Ei Input/Output, serial transmission of the 4 Fe | S10" data is executed. The built-in charge pump peal circuit permits all operations with a mere SV power supply, With the built-in timer a external parts are not required anymore, ac | while Erasure and Write are conducted { a t automatically.It is most suitable for the stall Fi non-volatile channel memory of electronic 2 tuners, for use instead of DIP switching as well as with the setting of various fixed numbers, or for the read only memory system necessary to rewrite immediately on the field, ee 89,.T.27 Features a, * Single SV poner supply + 128 word x 8 bit of full decoding structure + Serial data transmission + Rewritable in 1-word unit and in one chip * Memory retention time of more than l0years with no power supply + Number of erasures and writings: more than 10° times + TTL IC direct drive is possible . . -oOOoT7T or low power consumption (35 ml Typ.) ZB: furs SOs. Fh: Fire St. CHPC Structure P-channel MNOS IC
D Using internal timer circuit (In the example a serial port is used. A general port may also be used. It is also possible to refrain from using BUSY pin.) | Veco 59) (7) ry hice b CoE Vee Sie poe C] SK OD Cj SK Bsy 9 sin | ae C] Db OD (_} DI oe ft Cy })) ae L} 90 ao Cj LI C LJ a 2) Using external control OJ Ce Cy Micro 5 Co Vee om oh Cj sax 5 Cj sor Bsy sa | | Cj db pO {| DE ix ml = p—f Cf 1) ie (| Do aD (I CI 1 Cy tJ 7
SONY. aC SSONY: Input/Output Timing Chart INPUT HODE t toe tps tox. tos 008 (Les Bia) "hin EE} unrelated to Hl and L. te (es Max) te (Luss Max)
0 VALID
t a) tos too. (4 us Max) CE TIMING 1 OR HODE) . texs, L . . (us Min) tees<-Gus Hin) cexs KOU Hin) [om | VALID CE TIMING 2 (DW. ALDH ODE, INTERNAL TIMER) tees¢ Gus Mind teenie Gus Min) [om VALID iF Sk LEE 1 2/ (NE | Mee _ Hiz Hiz BUSY t (i0es Hed oh ter : (Q00ns Max) CE TIMING 3 (DH, ALDH MODE, EXTERNAL CONTROL) a tees te Gus Hin) ~feeenste-C00es Hin) « Y | VALID i #£ (ms Typ) (20ms Typ)
=} Ff ai A = J z 2 ' = 2 ' Z| t t < a if = = = i= ' wij I 5 2 1587: arfllla aA bo RF ag se F 8 Ey
a t—“_SSS SON'S Pin Description [ No. _| Type Description ii [ w fla | Chip enable input pin [2 [i | sx | Sync clock input pin (3 [ m fo | Data input pin [4 | or | bo | Data output pin [5 | Power | cxd | Power supply pin (Normally OV ) [6 | IN Oscillation pin When using internal circuit, Open or fixed to Vee) Hee BUSY signal output pin [8 | Power] Vee _| Power supply pin (Normally +5V ) Electrical Characteristics ll, (Ta=-40 to +85°C, Vee=5V +10%, GND-0V) Ce loput pull-up current | tw [08,S0KDI.080 | ViveoV —_[-80 |-60_|-180| wa | Pata] ie legal Tes fo asa fart ba [ tous 1.608 [| toa Tv | Output voltage“High"level 2 | Vous | BUSY. Ton= -4004A j24{ | |v | Output vol tage“Low"level 2 | vous [BEY] lou 400n% I | pet | *1. Including during Erase and trite. 42. See Fig.2.
CXK1012P SONY. top Temperature Characteristics BUSY Pin Output Delay Characteristics Su Toh ty 7 2 ce SCTE Pope er gee Et peer Pitty Fig.1 7c cry 10 (ms) Fig.2 DO Pin Output Characteristics (Typ.) 18 18 ee th lege | | TT | (CET nS PLY be | NIN LIZZ aan ot LK 1 AA n/m Pat LVN TI Sa ~ os \\__K , AH tT TA oe Vit ty titty ° 1 2 3 4 s 6 Fi ° 1 2 3 a s 6 Vor (¥) isd Vox (V) Supply Current Temperature Characteristics FP) SE gf. “0 Bee Ta-Ambient Temprature(‘C) Fie.d
Electrical Characteristics 2 = (faz-40 to +85, VeceSV +10%, GND=0V) [owes [ernie Yin vs Je lst pte with te otek alee with Pty Po [eta iat set tie Py [a al apt Be ie Pw [oe tes [ [hin enable tid tine 1 [teow fs [Ship ele totd tne 2 [terse] to] fr] [tock et wp tine [tes [5 [Data delay tie [tog [00 <f0HF Pt | BIST output delay tine’ | tae [OSH RIOKO—S*dYCSCSC | [Mondor of ead | We [Refresh reriod «dA P| ti [Proeren tine | tee [During intemal tiner usage i |__| @ 100 [as _| Brasure tine 100 iit tine Fis [Paring exert control” 6 | 1100 [as] teory retention tine T [ ton [After rewiting 10° tines.store at ToS | 10] | [year fermen | emer cesnsef | | fe *1. Including the value when Ta= 25 (See fig.1) +2, Usage of ranges ty to tw (16 to 100ms) presents no problem for Erasure and Krite in functions #3, See Fig.2. Command Table [wm [xe [2 [Wi | operational Coma] Foo [0 )0 [Wo pertin Fo [0 [a [0 |v: tery Write fo fa [oo [aie tye wite | es Ht [0 | 0 [0 |teceaiin Pro [1 [0] oe tery Bead [1 [1 | 0 [0 | test mode, Usage forbidden [1 [1 [1 | 0 [fest mode, Usage forbidden peta de [a | Test mode,Usage forbidden
Description of Circuit Operations 1) Timing At the rise tine of Sync clock (SCK),data is taken in from D1 and with the fall time,data is output from DO. Input data should be stabilized ,from Stkerise time and before 1 gs, 2) DR:Data Read (Memory Read) CE is set to L and then the first.clock is input after Sus. By entering address data (AT to Al) and mode data (M4 M3 M2 M1=1010), from the 17th clock and in synchronization with the fall time, D7 D6 through DO are output in the respective order. When the rise time of the 24th clock has taken place,set CE to H after Sys. 3) DW:Data Write (Hemory Write) CE is set to L and then the first clock is input after Sus. By entering Address data (AT to Al), mode data (M4 M3 M2 H1=0010)and Data (D7 to DO), from the rise time of the 24th clock,Erasure and Write are performed automatically. As BUSY pin outputs L during Erasure and Write and H at the completion of Write, set CE to H following H output and after Sys. When BUSY pin is not in use, set CE to H after 100ms( tye Hax.) 4) ALDH: All Byte Data Write By entering Mode Data (M4 M3 M2 H1=0100),Write operation of the same data (D7 to DQ) is carried out simultaneously to all addresses. CE timing and BUSY output are the same as in above article 3). 5) Electrical control of Erasure and Write Erasure and Write pulses are generated by the built-in C and R, However, external control is also possible, By setting OSC pin to L in DW or ALDH modes, Erasure and Write control are possible through the usage of ‘SCK pin. Erasure is carried out during te (20ns Typ.) and write during tw (20ms Typ.). By setting SCK pin to H after the lapse of tw ,write complete pulse is generated. However the actual completion takes place about 50 us after the pulse generation, (5Ozs Typ, 100zs Hax.) At that time BUSY pin changes from L to H. Over 5us after it has turned to H, set CE pin to H. Hhen BUSY pin is not in use,after SCK pin has turned from L to H (tw )by over 100xs,set CE to H.
CXK1012P SONY, Absolute Maximum Ratings (GND= (QV) + Supply vol tage Vee —0.3 to +7.0 OV + Input vol tage Vix —0,.3 to Vec +0.3 V + Operating temperature Topr —40 to +8 Storage temperature Tstg —55 to +150 Recommended Operati ng Conditions (fa--40 to+85t, GND-0V) + Supply vol tage Vee 4.5 to 5.5 v + Clock frequency ferx oc to 100 kHz * High level input voltage Vinw 0.7 Vee to Vee v * Low level input voltage Vint 0 to O.3 Vee v Block Diagram and Pin Configuration cuG ceQ) japoeess} | i2gi0e0 x gert PUMP (@) vee oeDoDeR MNOS MEMORY 7 TiMR __ ‘SCK (2) (7) BUSY ‘ADDRESS TIMING Cort) po @) ad 3 (5) cnb ‘OUTPUT BUFFER
CXK1012P SONY: 6) Usage of ALDH mode H, Write is carried out to the Memory elements according to the [Erase |—>[trite | cycle, During normal write procedures (DH mode),as write is executed for all the 128 address, 128 X top (or te + tw )=5.12sec (Typ.) amount of time is necessary. With the CXK1012P, f[Rrasure state J and [Data"0” | are made to correspond.Once “0”has been written into all addresses (Erasure state), by writing data into each address, the Program time can be shortened. ALDW Mode, D7 D6 -----+-- DO=00 ----- 0 te =20ms, ty =20ms DW Hode, AT ----- AL,D7 ----- DO (Each address, Data) te =Ims(Hin,), tw =20ms In this case, the program time becomes, (20ms +20ms) +128 X (lms +20ms) = 2.73sec