CXG7001FN

CXG7001FN SONY | Alldatasheet

Document overview

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Technical content

Features

• Operates at a single positive power supply: V DD = 3V  Small mold package: 26-pin HSOF <Power amplifier/antenna switch transmitter block >  Low current consumption: IDD = 150mA (POUT = 20.2dBm, f = 1.9GHz)  High power gain: Gp = 39dB Typ. (POUT = 20.2dBm, f = 1.9GHz) <Antenna switch receiver block/ low noise down conversion mixer>  Low current consumption: I DD = 5.5mA Typ. (When no signal)  High conversion gain: Gc = 20.5dB Typ. (f = 1.9GHz)  Low distortion: Input IP3 = –13dBm Typ. (f = 1.9GHz)  High image suppression ratio: IMR = 40dBc Typ. (f = 1.9GHz)  High 1/2 IF suppression ratio: 1/2IFR = 44dBc Typ. (f = 1.9GHz)

Applications

Japan digital cordless telephones (PHS) Structure GaAs J-FET MMIC Absolute Maximum Ratings <Power amplifier block>  Supply voltage V DD 6V  Voltage between gate and source VGSO 1.5 V  Gain control voltage VPCTL 2.5 V  Drain current I DD 550 mA  Allowable power dissipation PD 3W <Switch block> Control voltage V CTL 6V <Front-end block>  Supply voltage V DD 6V  Input power P RF +10 dBm <Common to each block>  Channel temperature Tch 150 °C  Operating temperature Topr –35 to +85 °C  Storage temperature Tstg –65 to +150 °C Recommended Operating Conditions <Common to each block>  Supply voltage V DD 2.7 to 3.3 V <Power amplifier block>  Gain control voltage VPCTL to VDD –1.0 V <Switch block>  Control voltage (H) V CTL (H) 2.9 to 3.3 V  Control voltage (L) V CTL (L) 0 to 0.2 V

– 2 – CXG7001FN Block Diagram and External Circuit Pin Configuration 30pF 2.2nH PIN 18nH1nF 1nF VDD 1 18nH1nF 30pF VDD 2 82nH 1nF 5pF 100pF 1.8nH10nF VDD 3 VCTL 2 VDD (IF AMP , MIX) (POUT ) (TX) 1pF 100pF IFOUT 30pF 100nF 13pF 10pF10nH 6.8nH (RFIN) (RX) VDD (LO AMP) LO IN VCTL 1 30pF 2.2nH 3.9nH VDD (RF AMP) 1nF18pF 1nF13pF 1314 ANT 100pF 1kΩ (VGG 1) VP CTL VGG 2 VGG 1 VP CTL VGG 2 POUT Tx V CTL 1 ANT GND GND V DD (RF AMP) GND V DD (LO AMP) LO IN PIN GND VDD 1 VDD 2 VDD 3 GND R X VCTL 2 RF IN CAP GND CAP IFOUT /VDD (IF AMP , MIX) 1 1314 26 pin – HSOF (Plastic)

– 3 – CXG7001FN Pin Description Pin No. Symbol LO IN VDD (LO AMP) GND V DD (RF AMP) GND GND ANT V CTL 1 TX POUT VGG 2 VP CTL VGG 1 PIN GND VDD 1 VDD 2 VDD 3 GND R X VCTL 2 RF IN CAP GND CAP IF OUT /VDD (IF AMP , MIX)

Description

LO signal input. LO AMP V DD . GND. RF AMP V DD . GND. GND. Antenna switch. Either ANT -Tx or ANT -Rx is depending on whether the setting is VCTL1 or VCTL 2. Antenna switch control Pin 1. Tx. Input the signal into the antenna switch when ANT -Tx. Power amplifier output. Power amplifier (the final-stage FET) gate voltage adjustment Pin 2. The first-stage FET control pin for the power amplifier. Power amplifier (the first-stage FET, the second-stage FET) gate voltage adjustment Pin 1. Signal input into the power amplifier. GND. Power amplifier (the first-stage FET) V DD 1. Power amplifier (the second-stage FET) VDD 2. Power amplifier (the final-stage FET) VDD 3. GND. Rx. Output ANT input signal into Rx when ANT -Rx. Antenna switch control Pin 2. RF signal input. Connector for the external capacitor. Connected to LNA FET source. Self-vibration frequency becomes 1.9GHz by this capacitor (Typ. 13pF). GND. Connector for the external capacitor. IF AMP distortion is corrected by this capacitor. IF output and IF AMP , MIX V DD .

– 4 – CXG7001FN

Electrical Characteristics

1. Control Pin Logic for Antenna Switch Conditions of control pins VCTL 1 = 3V, VCTL 2 = 0V VCTL 1 = 0V, VCTL 2 = 3V ANT – TX ON OFF ANT – RX OFF ON 2. Power Amplifier Block + Antenna Switch Transmitter Block These specifications are those when the Sony's recommended evaluation board, shown on page 7, is used. Unless otherwise specified: VDD = 3V, VPCTL = 2V, VCTL 1 = 3V, VCTL 2 = 0V, IDD = 150mA, POUT = 20.2dBm, f = 1.9GHz, Ta = 25°C UnitItem Current consumption Gate voltage adjustment value Output power Power gain Adjacent channel leak power ratio (600 ± 100kHz) Adjacent channel leak power ratio (900 ± 100kHz) Occupied bandwidth 2nd-order harmonic level 3rd-order harmonic level Measured with the ANT pin Measured with the ANT pin Measured with the ANT pin Measured with the ANT pin Measured with the ANT pin Measured with the ANT pin Measurement conditions mA V dBm dB dBc dBc kHz dBc dBc Symbol I DD VGG POUT G P ACPR600kHz ACPR900kHz OBW 3. Antenna Switch Receiver Block + Low Noise Down Conversion Mixer Block These specifications are those when the Sony's recommended evaluation board, shown on page 7, is used. Unless otherwise specified: VDD = 3V, VCTL 1 = 0V, VCTL 2 = 3V, RF1 = 1.90GHz/–35dBm, LO = 1.66GHz/–15dBm, Ta = 25°C UnitMax. 7.5 5.5 –37 Typ. 5.5 20.5 4.2 –13 –42 Min. –17.5 Item Current consumption Conversion gain Noise figure Input IP3 Image suppression ratio 1/2 IF suppression ratio 2 × LO–IF suppression ratio 2 × LO+IF suppression ratio LO to ANT leak When no signal When a small signal When a small signal RF2 = 1.42GHz/–35dBm RF2 = 1.78GHz/–35dBm RF2 = 3.08GHz/–35dBm RF2 = 3.56GHz/–35dBm Measurement conditions mA dB dB dBm dBc dBc dBc dBc dBm Symbol I DD G C NF IIP3 IMR 1/2IFR P LK ∗1 Conversion from IM3 suppression ratio during FR1 = 1.9000GHz/–35dBm and FR2 = 1.9006GHz/–35dBm input. Max. 0.60 –55 –60 275 –25 –25 Typ. 150 0.25 –63 –70 250 Min. 0.04 20.2

– 5 – CXG7001FN Example of Representative Characteristics 1. Power Amplifier + Antenna Switch Transmitter Block (f = 1.9GHz, Ta = 25°C) POUT , ACPR600kHz vs. PIN PIN – Input power [dBm] POUT – Output power [dBm] ACPR600kHz – Adjacent channel leak power ratio [dBc]–40 –35 –30 –25 –20 –15 –10 –70 –65 –60 –55 –50 –45 –40 VDD – Supply voltage [V] POUT – Output power [dBm] –70 –65 –60 –55 –50 –45 –40 POUT ACPR600kHz ACPR600kHz VDD = 3V, VPCTL = 2V, VGG = const., VCTL 1 = 3V, VCTL 2 = 0V IDD = 150mA (@POUT = 20.2dBm), PIN = var. VDD = 3V, VPCTL = var., VGG = const., VCTL 1 = 3V, VCTL 2 = 0V IDD = 150mA (@VPCTL = 2V), PIN = var., POUT = 20.2dBm Gp, ACPR600kHz vs. VPCTL VP CTL – Gain control voltage [V] G p – Power gain [dB] –70 –65 –60 –55 –50 –45 –40 G P ACPR600kHz POUT VDD = 3V, VPCTL = 2V, VGG = var., VCTL 1 = 3V, VCTL 2 = 0V IDD = var., PIN = var., POUT = 20.2dBm Gp, ACPR600kHz vs. IDD VDD = var., VPCTL = 2V, VGG = const., VCTL 1 = 3V, VCTL 2 = 0V IDD = 150mA (@VDD = 3V, POUT = 20.2dBm), PIN = –19.3dBm POUT , ACPR600kHz vs. VDD IDD – Current consumption [mA] G p – Power gain [dB] ACPR600kHz – Adjacent channel leak power ratio [dBc]100 120 140 160 180 200 220 –70 –65 –60 –55 –50 –45 –40 G P ACPR600kHz

– 6 – CXG7001FN 2. Antenna Switch Receiver Block + Low Noise Down Conversion Mixer (Ta = 25°C) G C , NF vs. PLO PLO – Local input [dBm] G C – Convertion gain [dB] 4.00 4.25 4.50 4.75 5.00 5.25 5.50 VDD = 3V, VCTL 1 = 0V, VCTL 2 = 3V, RF = 1.90GHz/small signal, LO = 1.66GHz VDD = 3V, VCTL 1 = 0V, VCTL 2 = 3V, RF = 1.90GHz/–35dBm, LO = 1.66GHz VDD = 3V, VCTL 1 = 0V, VCTL 2 = 3V, RF1 = 1.9000GHz, RF2 = 1.9006GHz, LO = 1.66GHz/–15dBm POUT , PIM3 vs. PIN PIN – RF input power [dBm] POUT – IF output power, PIM3 – 3rd-order intermodulation distortion power [dBm] –100 –80 –60 –40 –20 Input IP3, PLK vs. PLO PLO – Local input [dBm] Input IP3 [dBm] –22 –20 –18 –16 –14 –12 PLK –10 PLK – LO to ANT leak level [dBm] NF – Noise figure [dB] –60 –55 –50 –45 –40 –35 –30 POUTG C NF PIM3 Input IP3 Input IP3

– 7 – CXG7001FN Recommended Evaluation Board Enlarged Diagram of External Circuit Block VDD _LO VDD _LNA VDD _IF Via Hole Via Hole VCTL 2 VGG LO IN ANT Glass fabric-base epoxy board (4 layers) Thickness between 1 and 2: 0.2mm Dimensions: 50mm × 50mm IF OUT PAIN VCTL 1 VP CTL VDD _PA VDD (PA) VDD (IF) VDD (LO) VDD (LNA) VCTL 2V CTL 1V P CTL VGG R1 = 1k L1 = 1.8nH L2 = 2.2nH L3 = 3.9nH L4 = 6.8nH L5 = 10nH L6 = 18nH L7 = 82nH C1 = 1pF C2 = 5pF C3 = 10pF C4 = 13pF C5 = 18pF C6 = 30pF C7 = 100pF C8 = 1nF C9 = 10nF C10 = 100nF C8 C8 C10

– 8 – CXG7001FN SONY CODE EIAJ CODE JEDEC CODE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY PACKAGE STRUCTURE 0.06g HSOF-26P-01 HSOF 26PIN (PLASTIC) B 0.4 3.8 ± 0.05 4.4 ± 0.1 0.07M ∗5.6 ± 0.05 1 13 1426 A S A S 0.9 ± 0.1 0.08 S (1.5) (0.7)0.5 0.2 4.4 0.2 4.2 5.5 0.4 (1.75) 0.45 ± 0.15 NOTE: Dimension “∗” does not include mold protrusion. 0.14 – 0.03 DETAIL B 0.2 0 + 0.05 (0.2) 0.2 ± 0.05 Solder Plating + 0.05 LEAD PLATING SPECIFICATIONS ITEM LEAD MATERIAL COPPER ALLOY SOLDER COMPOSITION Sn-Bi Bi:1-4wt% PLATING THICKNESS 5-18µm SPEC. Sony Corporation Package Outline Unit: mm