CXG1192UR

CXG1192UR SONY | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 5

Technical content

Features

• Insertion loss (Tx) 0.25dB typical at 34dBm (GSM900) 0.35dB typical at 32dBm (GSM1800)  3 CMOS compatible control lines  Small package size: 18-pin UQFN (2.5mm × 3.5mm × 0.6mm (Max.))

Applications

Quad-band handsets using combinations of GSM850/900/1800/1900 Structure GaAs JPHEMT MMIC Absolute Maximum Ratings  Bias voltage V DD 7V (Ta = 25°C)  Control voltage Vctl 5V (Ta = 25°C)  Input power max. (Tx1) 37dBm (Ta = 25°C)  Input power max. (Tx2) 35dBm (Ta = 25°C)  Input power max. (all_Rx) 13dBm (Ta = 25°C)  Operating temperature Topr –30 to +85 °C  Storage temperature Tstg –65 to +150 °C GaAs MMICs are ESD sensitive devices. Special handling precautions are required. E04322-PS Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 2 – CXG1192UR Block Diagram Pin Configuration F10 Rx1 Rx2 Rx3 Rx4 Ant1 Tx1 Ant2 Tx2 16 17 18 9 8 7

10 GND

V DD CTLC CTLB CTLA Tx1 GND Ant1 GND Ant2 NC Tx2 NC Truth Table F10 ON ON ON ON ON OFF ON ON ON ON OFF ON ON OFF OFF OFF OFF ON OFF OFF OFF OFF ON OFF OFF ON OFF OFF OFF OFF ON ON ON OFF ON ON ON ON OFF ON ON ON OFF OFF OFF ON OFF OFF OFF OFF ON OFF OFF OFF ON OFF OFF OFF OFF OFF CTLC L H L H CTLB L H H L L H CTLA H H L L L L Path ANT1 – Tx1 ANT2 – Tx2 ANT1 – Rx1 ANT1 – Rx2 ANT2 – Rx3 ANT2 – Rx4

– 3 – CXG1192UR Electrical Characteristics (Ta = 25°C) Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dBm dBm dBm dBm dBm dBm µA mA µs Max. 0.40 0.50 0.65 0.65 0.85 0.85 –30 –32 –29 –37 0.23 Typ. 0.25 0.35 0.50 0.50 0.70 0.70 1.2 –36 –37 –32 –40 0.15 Min. Conditions ∗3, ∗4 ∗3, ∗4 ∗5, ∗6 ∗5, ∗6 ∗3, ∗4 ∗3, ∗4 ∗5, ∗6 ∗5, ∗6 Vctl = 2.8V VDD = 2.8V Path ANT1 – Tx1 ANT2 – Tx2 ANT1 – Rx1 ANT1 – Rx2 ANT2 – Rx3 ANT2 – Rx4 Tx1 – Rx1 Tx1 – Rx2 Tx2 – Rx3 Tx2 – Rx4 Rx1 – Tx1 Rx2 – Tx1 Rx3 – Tx2 Rx4 – Tx2 Tx1 – Ant1 Tx2 – Ant2 Tx1 – Ant1 Tx2 – Ant2 Symbol IL ISO. VSWR 2fo 3fo 2fo 3fo P1dB Ictl I DD Swt Item Insertion loss Isolation VSWR Harmonics∗ 1dB compression input power Control current Supply current Switching speed Electrical Characteristics are measured with all RF ports terminated in 50Ω . ∗ Harmonics measured with Tx inputs harmonically matched. We recommend the use of harmonic matching to ensure optimum performance. ∗1 Power incident on Tx1, Pin = 34dBm, 824 to 915MHz, VDD = 2.4V, Tx1 enabled ∗2 Power incident on Tx2, Pin = 32dBm, 1710 to 1910MHz, VDD = 2.4V, Tx2 enabled ∗3 Power incident on Ant, Pin = 10dBm, 869 to 894MHz, VDD = 2.4V, Rx1 or Rx2 enabled ∗4 Power incident on Ant, Pin = 10dBm, 925 to 960MHz, VDD = 2.4V, Rx1 or Rx2 enabled ∗5 Power incident on Ant, Pin = 10dBm, 1805 to 1880MHz, VDD = 2.4V, Rx3 or Rx4 enabled ∗6 Power incident on Ant, Pin = 10dBm, 1930 to 1990MHz, VDD = 2.4V, Rx3 or Rx4 enabled DC Bias Condition (Ta = 25°C) Item Vctl (H) Vctl (L) V DD Min. 2.0 2.4 Typ. 2.8 2.8 Max. 3.6 0.4 3.6 Unit V V V

– 4 – CXG1192UR When using this IC, the following external components should be used: C RF : This capacitor is used for RF decoupling and must be used all applications. Cbypass: This capacitor is used for DC line filtering. 100pF is recommended. Recommended Circuit Cbypass Cbypass C RF C RF C RF C RF C RF Cbypass C RF C RF 16 17 18 9 8 7 GND Rx4 Rx3 Rx2 Rx1 NC Cbypass 10VDD CTLB CTLACTLC Tx1 GND Ant1 GND C RF 4Ant2 NC Tx2 NC

– 5 – CXG1192UR Package Outline Unit: mm Sony Corporation LEAD PLATING SPECIFICATIONS ITEM LEAD MATERIAL COPPER ALLOY SOLDER COMPOSITION Sn-Bi Bi:1-4wt% PLATING THICKNESS 5-18µm SPEC. PIN 1 INDEX C

0.1 S A-B

0.5

0.05 M S C

C A-B S 18PIN UQFN (PLASTIC) x 4 TERMINAL SECTION 3.5 1015 18 7 2.5 1.1 0.4 ± 0.1 0.55 ± 0.05 8-C0.1 A B Note:Cutting burr of lead are 0.05mm MAX. 0.05 S + 0.09 0.24 – 0.03 S Solder Plating 0.24 2.1 4-R0.2MAX0.02 0.02g SONY CODE EIAJ CODE JEDEC CODE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL EPOXY RESIN SOLDER PLATING COPPER ALLOY PACKAGE STRUCTURE UQFN-18P-01 PACKAGE MASS