CXG1188UR SONY | Alldatasheet

Document overview

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Technical content

Features

‹ Low insertion loss: 0.30dB@900MHz, 0.45dB@1900MHz ‹ High linearity: IIP3 = 65dBm (Typ.) ‹ 1 CMOS compatible control line Package Small package size: 12-pin UQFN Structure GaAs J-FET MMIC Absolute Maximum Ratings (Ta = 25°C) Š Bias voltage V DD 7V Š Control voltage Vctl 5 V Š Operation temperature Topr –35 to +85 °C Š Storage temperature Tstg –65 to +150 °C

  • 2 - Block Diagram and Recommended Circuit When using this IC, the following external components should be used: CRF: This capacitor is used for RF decoupling and must be used for all applications. Cbypass: This capacitor is used for DC line filtering. 100pF is recommended. Truth Table DC Bias Conditions (Ta = 25°C) Cbypass (100pF) CRF CRF RF1 GND CTLGNDVDD GND RF4 GND GND 11 12 F3 F1 GND RF2 CRF RF3 CRF 8 2 6 5 4 CTL ON state OFF state F1 F2 F3 F4 L RF1 – RF2, RF3 – RF4 RF2 – RF3, RF4 – RF1 ON OFF ON OFF H RF2 – RF3, RF4 – RF1 RF1 – RF2, RF3 – RF4 OFF ON OFF ON Item Min. Typ. Max. Unit Vctl (H) 2.0 3.0 3.6 V Vctl (L) 0 — 0.4 V VDD 2.7 3.0 3.6 V
  • 3 -

Electrical Characteristics

(Ta = 25°C) *1 Pin = 25dBm, 0/3V control, VDD = 3.0V, 900MHz *2 Pin = 25dBm (900MHz) + 25dBm (901MHz), 0/3V control, VDD = 3.0V *3 Pin = 25dBm, 0/3V control, VDD = 3.0V, 1.9GHz *4 Pin = 25dBm (1.9GHz) + 25dBm (1.901GHz), 0/3V control, VDD = 3.0V Pin Description Item Symbol Condition Min. Typ. Max. Unit Insertion loss IL 900MHz 0.30 0.55 dB 1.9GHz 0.45 0.70 dB Isolation ISO. 900MHz 18 21 dB 1.9GHz 14 16 dB VSWR VSWR 50 Ω 1.2 — Harmonics 2fo *1 –75 –60 dBc *3 –75 –60 dBc 3fo *1 –75 –60 dBc *3 –75 –60 dBc Input IP3 IIP3 *2 55 65 dBm *4 55 65 dBm 1dB compression input power P1dB V DD = 2.8V 32 35 dBm Switching speed TSW 1 5 µs Bias current I DD VDD = 3.0V 55 130 µA Control current Ictl Vctl (H) = 3.0V 40 100 µA Pin No. Symbol Description

1 GND Control signal input

2 RF1 RF signal input

4 RF2 RF signal output

6 RF3 RF signal input

8 RF4 RF signal output

11 GND GND

12 CTL Control signal input

  • 4 - Sony Corporation Package Outline (Unit: mm) PIN 1 INDEX C

0.1 S A-B

0.4

0.05 M S C

C A-B S 0.05 S MAX0.02 + 0.09 12PIN UQFN㧔PLASTIC㧕 0.25 – 0.03 + 0.09 0.14 – 0.03 x 4 2.0 1 3 9 7 2.0 S 0.4 ± 0.1 غ0.6 0.55 ± 0.05 4-R0.2 A B 0.25 0.14 0.07 0.18 SONY CODE EIAJ CODE JEDEC CODE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.01g PACKAGE STRUCTURE UQFN-12P-01 PACKAGE MASS TERMINAL SECTION Note:Cutting burr of lead are 0.05mm MAX. Solder Plating Thermal Die Pad LEAD PLATING SPECIFICATIONS ITEM LEAD MATERIAL COPPER ALLOY SOLDER COMPOSITION Sn-Bi Bi:1-4wt% PLATING THICKNESS 5-18µm SPEC.