CXG1117K SONY | Alldatasheet

Document overview

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  • PDF pages: 6

Technical content

Features

  • Single power supply operation: V DD1 = VDD2 = 3.5V (High mode), 1.7V (Low mode), V GG = 2.95V  Ultrasmall package: 0.065cc (6.2mm × 6.2mm × 1.7mm)  High efficiency: ηadd = 36.5% (@900MHz, POUT = 27.5dBm)  Output power (high/low mode switching supported): POUT ≤ 19dBm: Low mode (VDD1 = VDD2 = 1.7V) POUT = 19 to 27.5dBm: High mode (VDD1 = VDD2 = 3.5V)  Gain: Gp = 26dB (@900MHz)

Applications

Power amplifier for JCDMA system cellular phones Structure p-Gate HFET module Recommended Operating Conditions VDD = 3.3 to 4.2V (High Mode) 1.7V (Low Mode) V GG = 2.95V±1% Absolute Maximum Ratings  Operating case temperature Tcase –30 to +85 °C  Storage temperature Tstg –30 to +125 °C  Bias voltage V DD1 , VDD2 6V  Bias voltage V GG 3.3 V (VDD1 = VDD2 = 3.5V)  Input power P IN 8 dBm GaAs module is ESD sensitive devices. Special handling precautions are required.

– 2 – CXG1117K package Outline/Pin Configuration Front Back

6 VGG1PIN

7 GND

8 GND

5 GND

4 POUT

1 PIN6VGG

9 GND 2 VDD1

3 VDD2

– 3 – CXG1117K Electrical Characteristics (ZS = ZL = 50Ω , IS-95 Modulation, T a = 25°C) POUT = 27.5dBm, VDD = 3.5V , VGG = 2.95V POUT = 14dBm, VDD = 1.7V , VGG = 2.95V POUT = 27.5dBm, VDD = 3.5V , VGG = 2.95V POUT = 27.5dBm, VDD = 3.5V , VGG = 2.95V , ±900kHz offset, 30kHz band width POUT = 27.5dBm, VDD = 3.5V , VGG = 2.95V , ±1.98MHz offset, 30kHz band width POUT = 19dBm, VDD = 1.7V , VGG = 2.95V, ±900kHz offset, 30kHz band width POUT = 19dBm, VDD = 1.7V , VGG = 2.95V, ±1.98MHz offset, 30kHz band width POUT = 27.5dBm, VDD = 3.5V , VGG = 2.95V VDD = 3.5V , VGG = 2.95V VGG = 2.95V , POUT ≤ 27.5dBm VDD = 3.5V → 1.7V VGG = 2.95V , POUT = 17dBm POUT = 27.5dBm, VDD = 3.5V , VGG = 2.95V Item Frequency Current consumption 1 Current consumption 2 Gain ACPR1 (High mode) ACPR2 (High mode) ACPR1 (Low mode) ACPR2 (Low mode) 2nd, 3rd harmonics Input VSWR Gate current Gain deviation for bias variation Gain deviation within band Conditions Min. 887 Ty p. 440 105 –51 –59 –53 –60 –40 1.3 2.5 1.2 Max. 925 475 125 –45 –56 –45 –56 –30 2.5 4.5 Unit MHz mA mA dB dBc dBc dBc dBc dBc mA dB dB

– 4 – CXG1117K Recommended External Circuit GND GND GND GND C2 C3 VGG C1: 0.1µF C2: 1µF C3: 10µF R: 5.1Ω L: 6.8nH C2 C1 POUT PIN VDD1 C3 C2 C1 VDD2 RL Recommended Evaluation Board Board material: Glass fabric-base epoxy Size: 40mm × 50mm × 0.6mm Relative dielectric constant: 4.6 Front Back GND POUT GND GND VGG VDD2 VDD1 PIN GND C1C2 RL

– 5 – CXG1117K Example of Representative Characteristics Conditions:f = 900MHz VDD1 = VDD2 = 3.5V , VGG = 2.95V T a = 25°C POUT vs. PIN PIN [dBm] POUT [dBm] –18 ACPR2 vs. POUT POUT [dBm] ACPR2 [dBc] –56 –58 –60 –62 –64 –66 –68 –70 –72 –74 –76 –78 –80 ACPR1 vs. POUT POUT [dBm] ACPR1 [dBc] –34 –36 –38 –40 –42 –44 –46 –48 –50 –52 –54 –56 –58 –60 –62 –64 Gain vs. POUT POUT [dBm] Gain [dB] 28.0 27.5 27.0 26.5 26.0 25.5 25.0 24.5 24.0 23.5 23.0 22.5 22.0 IDD vs. POUT POUT [dBm] IDD [mA] 650 600 550 500 450 400 350 300 250 200 150 100 10 12 14 16 18 20 22 24 26 28 30 32 8 10 12 14 16 18 20 22 24 26 28 30 32 8 10 12 14 16 18 20 22 24 26 28 30 32 8 10 12 14 16 18 20 22 24 26 28 30 32

– 6 – CXG1117K Sony Corporation Package Outline Unit: mm SONY CODE EIAJ CODE JEDEC CODE PACKAGE MATERIAL TERMINAL TREATMENT TERMINAL MATERIAL PACKAGE MASS CERAMIC SUBSTRATE NICKEL PLATING PACKAGE STRUCTURE GOLD PLATING 8PIN LCC (Ceramic) ∗ 6.2 ± 0.3 3.8 0.9 1.6 1.9MAX X R0.2 DETAIL Y-Y DETAIL X PIN 1 INDEX 6.0 SOLDERING POINT 0.15 SOLDERING POINT COAT TERMINAL Y Y R0.2C0.1 0.15 0.1 S S COAT TERMINAL LCC-8C-601 1.7 0.8g 0.6 ± 0.2 Dimension " ∗"dose not inculude cutting burr. 6.7MAX 1.1 ± 0.2 0.15 1.7 ± 0.1 3.4 ± 0.15 5.3 5.8 0.1 0.2 0.015MAX