CXG1092N SONY | Alldatasheet

Document overview

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Technical content

Features

  • 4 CMOS compatible control lines
  • Standby control
  • 34.5dBm power handling at 5.0V (GSM900)
  • Low second harmonic < –36dBm at 34.5dBm
  • Small package size: 20-pin SSOP (6.4 × 5.0 × 1.25mm)

Applications

Triple-band handsets using combinations of GSM900/DCS1800/PCS1900 and DECT Structure GaAs J-FET MMIC (The Sony JFET process is used for low insertion loss.) – 1 – E99Z07-PS Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. CXG1092N 20 pin SSOP (Plastic) Note on Handling GaAs MMICs are ESD sensitive devices. Special handling precautions are required. Absolute Maximum Ratings (Ta = 25°C)

  • Bias voltage V DD 7V
  • Control voltage Vctl 5 V
  • Operating temperature Topr –35 to +85 °C
  • Storage temperature Tstg –65 to +150 °C

– 2 – CXG1092N GSM900 H L H L L DCS1800 L H L H L PCS1900 L L L L H Rx ON L L H H H STDBY H H H H H L On Pass Ant.-Tx1 GSM900 Ant.-Tx2 GSM1800 Ant.-Rx1 GSM900/1800/1900 Ant.-Rx2 GSM900/1800/1900 Ant.-Rx3 GSM900/1800/1900 OFF Truth Table Logic High Low Min. 2.4 0.0 Typ. 2.8 Max. 3.2 0.4 Unit V V (Ta = 25°C)CMOS logic values

– 3 – CXG1092N Electrical Characteristics (Ta = 25°C) ∗1 Pin 1 = 34.5dBm, 880 to 915MHz, VDD = 5.0V (GSM Tx) ∗2 Pin 2 = 32dBm, 1710 to 1910MHz, VDD = 5.0V (DCS & PCS Tx) ∗3 Pin 3 = 10dBm, 925 to 960MHz (GSM Rx) ∗4 Pin 4 = 10dBm, 1805 to 1880MHz (DCS Rx) ∗5 Pin 5 = 10dBm, 1930 to 1990MHz (PCS Rx) Note) Harmonics measured with Tx inputs harmonically matched. Sony recommends the use of harmonic matching to ensure optimum device performance Application Note (1). Item Insertion loss Isolation VSWR HarmonicsNote) P1dB compression input power Control current Supply current Tx mode Supply current Rx mode Leakage current Symbol IL ISO. VSWR 2fo 3fo P 1dB Ictl ITX IRX IIK Port Ant-Tx1, Tx2 Ant-Rx1, Rx2, Rx3 Ant-Tx1, Tx2 Ant-Rx1, Rx2, Rx3 Ant-Tx1, Tx2 Ant-Tx1 Ant-Tx2 Condition ∗4, ∗5 ∗1, ∗2 ∗1, ∗2 STBY = H TxON = L STBY = H RxON = H STBY = L Min. Typ. 0.6 0.7 0.6 0.85 0.9 1.2 35.5 Max. 0.9 1.0 0.9 1.1 1.15 –36 –30 170 100 Unit dB dB dB dB dB dB dB dB dB dBm dBm dBm µA mA mA µA

– 4 – CXG1092N Recommended Circuit Recommended PCB Layout ∗ As indicated in the diagram AC coupling capacitors are necessary to the Ant, Tx1, Tx2, Rx1, Rx2 and Rx3 pins, and decoupling capacitors are necessary to the VDD , STDBY and CTL lines. ∗ The ground plane should be included under the device and all ground pins connected to this. ∗ RRF (200kΩ ) is used to stabilize the electrical characteristics at the high power signal input. These resistors are required to ensure correct operation of the switch. ∗1 See Application Note (1). GND Tx2 GND Rx1 GND Rx2 GND Rx3 STDBY Tx1 GND GND V DD GND GSM900 CTL DCS1800 CTL PCS1900 CTL RX ON GND ANT (RRF) (RRF) (∗1) (RRF)

– 5– CXG1092N Application Note (1) Impedance matching for harmonic minimization To achieve the 2nd harmonic levels lower than –36dBm for GSM900 Design of 1.8GHz harmonic matching network and the 900MHz trap network is dependent on the board design and components. GND 1800MHz Matching Network 900MHz Trap LPF Tx2 GND Rx1 GND Rx2 GND Rx3 STDBY Tx1 GND GND VDD GND GSM900 CTL DCS1800 CTL PCS1900 CTL RX ON GND ANT Application Note (2) Operating the CXG1092 from a 3V supply Tx1 ANT Logic lines Tx2 Rx1 Rx2 Rx3 CXG1092N ≈ 4.0V D.C. Out VDD @2.7V 577µs VDD C D 200k R C Technique Allows use of the CXG1092N (SP5T) in handsets with 3V min. battery voltage (2.7V SW supply). The CXG1092N is for 5V nominal battery voltage but work well down to 4V. Fundamentally, the 577µs time slot waveform is used to increase the 2.7V supply to over 4V. ∗ This waveform may be taken from the PA ramping input (or drain supply in case of drain power control) or via the TX ON/OFF logic. Additional Components C: 0603 CAPS, few µF R: 200R D: Low Turn-on voltage diode 200k200k

– 6– CXG1092N Package Outline Unit: mm SONY CODE EIAJ CODE JEDEC CODE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM COPPER ALLOY PACKAGE STRUCTURE PLATING 0.1g SSOP-20P-L03 SSOP020-P-0044 20PIN SSOP(PLASTIC) NOTE: Dimension “∗” does not include mold protrusion. A 20 11 0.5

0.1 M SA

A 1.25MAX S B 0° to 10° (0.5) 0.6 ± 0.15 0.25 0.1 ± 0.1 DETAIL A 0.1 0.1 ∗5.0 ± 0.05 (0.15)0.17 ± 0.03 (0.2) b = 0.22 ± 0.05 DETAIL B : SOLDER 0.15 – 0.01 b = 0.2 ± 0.03 DETAIL B : PALLADIUM 0.1 S b + 0.03 Sony Corporation