CXD4016R SONY | Alldatasheet

Document overview

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Technical content

Features

‹ Performs all the transmitted digital signal processing on a single chip ‹ Supports the infrared spatial digital audio communication system formats for consumer uses ‹ Support the three audio sampling frequencies (32kHz, 44.1kHz, 48kHz) ‹ Direct output of RF signals enabled by on-chip DAC ‹ External RAM and PLL circuit not required < Audio I/F Block > Š Interfaces for various audio ADCs < Parity Generator Block > Š Automatic generation of Reed-Solomon parity for the infrared spatial digital audio communication system format < Modulator Block > Š Digital processing throughout enables the transmitted RF signals in the infrared spatial digital audio communication system formats to be processed directly Š External analog circuit can be simplified by on-chip digital filter and on-chip DAC for RF signal

applications

Š Generation of subcarrier processed digitally < Controller Block > Š Simple pin setting mode Š Serial interface provided by serial bus < PLL Block > Š On-chip analog PLL circuit for generating the clock signals (640fs) required by the infrared spatial digital audio communication system formats

  • 2 - Package 64 pin LQFP (Plastic) Structure Silicon gate CMOS IC Absolute Maximum Ratings Recommended Operating Conditions Input/Output Capacitance Note) Measurement conditions : Tj = 25°C, VDD = VI = 0V, f = 1MHz Š Supply voltage V DD – 0.5 to + 3.0 V Š Input voltage V I – 0.5 to VDD + 0.5 ( ≤ 3.0V) V Š Output voltage V O – 0.5 to VDD + 0.5 ( ≤ 3.0V) V Š Storage temperature Tstg – 55 to + 125 °C Š Supply voltage V DD 2.5 ± 0.2 V Š D/A supply voltage V DA 2.5 ± 0.2 V Š PLL supply voltage V PLL 2.5 ± 0.2 V Š Operating temperature Topr – 40 to + 85 °C Š Sampling frequency precision Within ± 0.1% ‹ Input capacitance C IN 16 (max.) pF ‹ Output capacitance C OUT 16 (max.) pF ‹ Input/Output capacitance C I/O 16 (max.) pF
  • 3 - Block Diagram * Test pins not shown. OSCI Clock Generator Audio I/F Reed- Solomon Parity Generator Buffer RAM Modulator Controller PLL Clock Selector D/A Converter APAVD44 APAVS45 APX38 DAAOUT21 DAAVD22 DAAVS23 DAVREF24 IFEXMD3 IIFSEL14 IIFSEL05 EXCKSEL6 CHNM_BL7 DIVCODE8 PCMID9 EMPIN10 XSCEN14 SCLK13 SWDT15 CSOD VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VDD DAVRO25 VCOT46 PLREF PLVAR APS APVGS APCPO OSCO 59 CK12 53 LRCK 49 BCK 50 DTIN 48 BCKOUT 51 LRCKOUT 52 XRST 64
  • 4 - Pin Configuration TESTMD IFEXMD SMCK IIFSEL1 IIFSEL0 CHNM_BL EXCKSEL DIVCODE PCMID VDD EMPIN VSS SCLK SWDT XSCEN CSOD DTIN VCOT DT2_INF APAVS APAVD APVGS APCPO APS VSS APX VDD PLVAR PLREF TEST6 TEST7 TEST5 TEST4 TEST2 TEST0 V DD TEST3 TEST1 V SS DAVREF DAVRO DAAVD VSS DACK DAAVS DAAOUT VDD DAPD LRCK BCKOUT CK12 VSS BCK LRCKOUT CSST OSCI VDD OSCO XSM XTST VSS XTCK4 MST XRST 1 2 3 4 5 6 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 7 8
  • 5 - Pin Description Pin No. Symbol I/O Description 1 TESTMD I Test mode selector, normally fixed “L”. 2 SMCK I SCAN test pin, normally fixed “H”. 3 IFEXMD I IIF extension mode. (L : Normal mode, H : Extension mode) 4 IIFSEL1 I Audio input mode selection. 5 IIFSEL0 I Audio input mode selection. 6 EXCKSEL I Clock selection for modulation. (L : APX internal connection, H : VCOT pin input) 7 CHNM_BL I Half-band : Channel number selection. (L : 0ch, H : 1ch) Full-band : Bit length control. (L : Full bit, H : 16-bit limited) 8 DIVCODE I Full/Half-band mode selection. (L : Full-band, H : Half-band) 9 PCMID I Source_info pcm_id input, normally fixed “L”. (L : PCM data)

10 EMPIN I Source_info emphasis input, (L : No emphasis, H : Emphasis)

DD — Digital power supply. 12 V SS — Digital GND. 13 SCLK I Serial interface data clock input. 14 XSCEN I Serial interface enable input (negative logic). 15 SWDT I Serial interface data write input. 16 CSOD O Chapter start delay output. 17 DAPD O Test pin. 18 DACK O Test pin. 19 V DD — Digital power supply. 20 V SS — Digital GND. 21 DAAOUT O RF DAC output. 22 DAAVD — Analog power supply for RF DAC. 23 DAAVS — Analog GND for RF DAC. 24 DAVREF I RF DAC reference voltage input, apply 1.1V (typ.) 25 DAVRO I/O RF DAC internal current setting. 26 V DD — Digital power supply. 27 V SS — Digital GND. 28 TEST0 O Test output pin. 29 TEST1 O Test output pin. 30 TEST2 O Test output pin. 31 TEST3 O Test output pin. 32 TEST4 O Test output pin. 33 TEST5 O Test output pin. 34 TEST6 O Test output pin. 35 TEST7 O Test output pin. 36 PLREF O PLL reference output.

  • 6 - 37 PLVAR O PLL frequency-divided output (APX out put or VCOT input divided by 640). 38 APX O PLL VCO output, 640fs. 39 V DD — Digital power supply. 40 V SS — Digital GND. 41 APS I PLL reset pin. 42 APVGS — PLL guard band GND. 43 APCPO O PLL charge pump output. 44 APAVD — PLL power supply. 45 APAVS — PLL GND. 46 VCOT I External clock input for modulation. 47 DT2_INF I Test pin, normally fixed “L”. 48 DTIN I Audio data input. 49 LRCK I LR clock input. 50 BCK I Bit clock input. 51 BCKOUT O Bit clock output (3.072MHz). 52 LRCKOUT O LR clock output (48kHz). 53 CK12 O Frequency-divided clock output for master clock (12.288MHz). 54 CSST I Test pin, normally fixed “L”. 55 V SS — Digital GND. 56 V DD — Digital power supply. 57 OSCI I Crystal oscillator circuit input for master clock (24.576MHz). 58 V SS Digital GND. 59 OSCO O Crystal oscillator circuit output for master clock (24.576MHz). 60 XTCK4 I Test pin, normally fixed “L”. 61 XSM I Test pin for SCAN, normally fixed “H”. 62 MST I Test pin for SCAN, normally fixed “L”. 63 XTST I Test pin for SCAN, normally fixed “H”. 64 XRST I Asynchronous reset input. While power supply is “ON”, be sure to reset by fixing “L” after power supply is stabilized. Pin No. Symbol I/O Description
  • 7 -

Electrical Characteristics

  1. DC characteristics (VDD = 2.5 ± 0.2V, VSS = 0V, Topr = – 40 to + 85°C) Applicable pins *1 TESTMD, SMCK, IFEXMD, IIFSEL1, IIFSEL0, EXCKSEL, CHNM_BL, DIVCODE, PCMID, EMPIN, SCLK, XSCEN, SWDT, APS, VCOT, DT2_INF, DTIN, LRCK, BCK, CSST, XTCK4, XSM, MST, XTST, XRST *2 CSOD, DAPD, DACK, TEST0, TEST1, TEST2, TEST3, TEST4, TEST5, TEST6, TEST7, PLREF, PLVAR, APX, BCKOUT, LRCKOUT, CK12 *3 APAVD *4 APCPO *5 DAAVD *6 DAVREF *7 DAVRO *8 DAAOUT *9 VDD (Pins 11, 19, 26, 39, 56) Item Symbol Conditions Min. Typ. Max. Unit Applicable pins High level input voltage V IH 1.7 — VDD + 0.3 V Low level input voltage V IL – 0.3 — 0.7 High level output voltage V OH IOH = – 100µA VDD – 0.2 —V DD Low level output voltage V OL IOL = 100µA0 — 0 . 2 High level output current I OH VOH = VDD – 0.4V – 4.0 — — mA Low level output current I OL VOL = 0.4V 4.0 — — *2 Input leakage current I L —— ± 5 µA *1 PLL supply voltage V PLL 2.3 2.5 2.7 V *3 PLL charge pump output current ICPO 500 µA *4 DAC supply voltage V DA 2.3 2.5 2.7 V *5 DAC reference voltage V REF 1.05 1.10 1.15 V *6 DAC full-scale adjusting resistor RREF Between DAVRO and DAAVS 2.4 2.7 k Ω *7 DAC output current I DAC VREF = 1.10V, RREF = 2.7kΩ Full-scale Zero-scale LSB-scale 4.67 5.194 20.3 5.71 mA µA µA DAC load resistance R L Between DAAOUT and DAAVS 150 160 Ω *8 Supply current of digital block IDD VDD = 2.5V fs = 44.1kHz Full-band mode 12 mA *9 Supply current of D/A block IDA V (DAAVD) = 2.5V fs = 44.1kHz Full-band mode 6.5 mA Supply current of PLL block IPLL V (APAVD) = 2.5V fs = 44.1kHz Full-band mode 3.5 mA
  • 8 - 2. AC characteristics (1) OSCI, OSCO pins (a) When using self-excited oscillation (VDD = 2.5 ± 0.2V, VSS = 0V, Topr = – 40 to + 85°C) (b) When inputting pulses to OSCI (VDD = 2.5 ± 0.2V, VSS = 0V, Topr = – 40 to + 85°C) (2) VCOT pin (VDD = 2.5 ± 0.2V, VSS = 0V, Topr = – 40 to + 85°C) Item Symbol Min. Typ. Max. Unit Oscillation frequency f SYS — 24.576 — MHz Item Symbol Min. Typ. Max. Unit Pulse frequency f SYS 24.330 24.576 24.600 MHz High level pulse width t WHX — 20.345 — ns Low level pulse width t WLX — 20.345 — ns Rise time/fall time t R, tF 2n s Item Symbol Min. Typ. Max. Unit Pulse frequency f CXR 20.275 — 31.027 MHz High level pulse width t WHXS 0.45 × tCXR — 0.55 × tCXR ns Low level pulse width t WLXR 0.45 × tCXR — 0.55 × tCXR ns VIH VIH × 0.9 VDD/2 VIH × 0.1 VIL tCX (1/fSYS) tWHX tWLX OSCI tFtR VIH VIH × 0.9 VDD/2 VIH × 0.1 VIL tWHXR tWLXR VCOT tFtR tCXR (1/fCXR)
  • 9 - (3) SCLK, XSCEN, SWDT, SRDT pins (VDD = 2.5 ± 0.2V, VSS = 0V, Topr = – 40 to + 85°C) (4) CSOD pin (VDD = 2.5 ± 0.2V, VSS = 0V, Topr = – 40 to + 85°C) (5) XRST pin (VDD = 2.5 ± 0.2V, VSS = 0V, Topr = – 40 to + 85°C) Item Symbol Min. Typ. Max. Unit Clock period t CW 200 — — ns Clock pulse width, high t CWH 100 — — ns Clock pulse width, low t CWL 100 — — ns Enable signal pulse width t CSWH 170 — — ns Enable signal setup time t CSS 0— — n s Enable signal hold time t CSH 100 — — ns SWDT Setup time t WSU 20 — — ns SWDT Hold time t WHD 100 — — ns Item Symbol Min. Typ. Max. Unit CSOD pulse width t CSOD 260 — — µs Item Symbol Min. Typ. Max. Unit XRST pulse width t XRST 100.0 — — ns SCLK XSCEN SWDT tCSS tCWL tCWH tCW tCSWHtCSH tWSU tWHD An example of data read phase CSOD tCSOD XRST tXRST
  • 10 - (6) BCK, DTIN, LRCK pins (VDD = 2.5 ± 0.2V, VSS = 0V, Topr = – 40 to + 85°C) Item Symbol Min. Typ. Max. Unit DTIN setup time t DTS 10 — — ns DTIN hold time t DTH 100 — — ns LRCK skew time t LRSK —— ± 20 ns tDTS BCK DTIN LRCK tDTH VDD/2 VDD/2 VDD/2 tLRSK
  • 11 - Description of Functions Description of clock generator 1. This LSI chip can generate the system clock pulse by connecting a 24.576MHz crystal oscillator to the OSCI pin and OSCO pin. Also, it incorporates 1MΩ (typ.) feedback resistor between the OSCI and OSCO pins. 2. It functions as the system clock by inputting a 24.576MHz external oscillation clock pulse to the OSCI pin while keeping the OSCO pin open. 3. Please keep the frequency precision for system clock within 24.576MHz ± 100ppm. Description of PLL circuit 1. In addition to supplying the system clock pulse using t he OSCI pin, this LSI requires the modulation clock pulse which is provided by the PLL circuit. The PLL circuit provided on the LSI chip can be used for this purpose. 2. If the sampling frequency of the digital audio input signals is fs, then the modulation clock pulse provided by the PLL circuit has a frequency of 640fs. 3. When the PLL circuit on the LSI is used, input a low level to the EXCKSEL pin and VCOT pin. Furthermore, an external lag-lead filter must be connected to the LSI for the charge pump current output APCPO pin of the PLL circuit. Ensure that the wiring involved is kept as short as possible. 4. When the PLL circuit on the LSI is not used, the LS I chip must be provided with an external PLL circuit. Input a high level to the EXCKSEL pin and the modulation clock pulse to the VCOT pin. The reference signal of the PLL circuit for generating the clock pulses is output to the PLREF pin, and its frequency is set to fs. At this time, the frequency of the clock pulse which has been input to the VCOT pin is divided by 640 inside the LSI, and the pulse with the resulting frequency is output to the PLVAR pin. Pin setting/serial data interface The setting modes of this LSI can be broadly classified into two : the pin setting mode and the serial data interface mode. By setting serial data interface mode, switching between pin setting mode and serial data interface mode is enabled. For example, setting SCEN01 bit to “0” validate pin setting mode and setting it to “1” validate serial data interface setting mode during Address 01 in serial data interface mode. (See “(3) Serial setting command table” on the next page.) Followings are pins which can be set even in the serial data interface mode. EXCKSEL pin, DIVCODE pin, CHNM_BL pin, IFEXMD pin, IIFSEL1 pin, IIFSEL0 pin, PCMID pin, EMPIN pin.
  • 12 - Description of serial data interface 1. Serial data interface timings This LSI enables the various LSI operations to be changed by the SCLK pin, SWDT pin and XSCEN pin. The interface timing chart for each code group is presented below. Also, the SCLK pin should not be used with other devices. Normal communication cannot be performed. 2. XRST pin All the internal registers are initialized to “Default value” presented in the “Serial data interface setting command table” when reset by setting the XRST pin to low. 3. Method for disabling the CXD4016R's FSLOCK signal The LRCK input to the CXD4016R must be a stable clock with no jitter. A PLL that uses LRCK as the reference is formed inside the CXD4016R, and this PLL generates a 640fs clock. However, the signal (FSLOCK) that indicates the PLL lock status is generated inside this LSI, and RF generation is temporarily stopped when the lock is lost. This lock detection logic has strict conditions, so if the LRCK jitter is large, the jitter of the clock generated by the PLL is also large, and the lock may be judged as lost. Using a LRCK with large jitter is not recommended, but when a LRCK with large jitter must be used, this LSI has a test mode that can reduce the RF generation stoppage frequency by disabling the FSLOCK signal as follows. FSLOCK can be enabled or disabled by sending the command indicated in the Serial Setting Command Table. At the default setting, FSLOCK operates according to the lock detection logic. To forcibly set the FSLOCK status, send address 71h and data 0Fh by the serial setting command. In addition, to return to the default setting, send address 71h and data 03h by the serial setting command. Performing this process is highly recommended. A7 A6 A5 A4 A3 A2 A1 A0 Dn – 1 Dn – 2 Dn – 3 D2 D3 D2 D1 D0 SCLK SWDT XSCEN Internal registers Valid
  • 13 - 4. Serial setting command table Address (HEX) Default value Length [bit] Signal name Signal length [bit] Value Effect 01h 00h 8 SCEN01 1 0 Invalidate serial setting of Address 01. Validate serial setting of Address 01. EXCKSEL 1 0 APX internal connection. VCOT pin input. DIVCODE 1 0 Full-band mode. Half-band mode. CHNM_BL 1 0 0ch/full-bit. 1ch/16-bit limited. IFEXMD 1 0 Normal mode. Extension mode. IIFSEL1 1 — Audio input interface mode select 1. IIFSEL0 1 — Audio input interface mode select 0. res. 1 0 Be sure to set the value to “0”. 02h 40h 8 SCEN02 1 0 Invalidate serial setting mode of Address 02. Validate serial setting mode of Address 02. CRC_FLG 1 0 CRC off. CRC on (default). VALID_FLG 1 0 Source_block is error free. Source_block contains some errors. PCM_ID 1 0 Data is Linear PCM. Data is used for other purposes. CPRGT_FLG 1 0 Copyright is asserted. No copyright is asserted. EMPHASIS 1 0 No emphasis. Emphasis. res. 2 00 Reserved. 03h 69h 8 CATEGORY 8 — Source_info Byte 3 category codes. 71h 03h 8 res. 4 0000 Be sure to set the value to “0000”. FSLOCK_EN 1 0 Invalidate serial setting mode of FSLOCK. Validate serial setting mode of FSLOCK. FSLOCK 1 0 Set to unlocked logic forcibly. Set to locked logic forcibly. res. 2 11 Be sure to set the value to “11”.
  • 14 - Description of audio I/F 1. As shown below, the audio ADC can be directly coupled in this LSI. The sampling frequencies (fs) which can correspond to this LSI are 32kHz, 44.1kHz, 48kHz. Also, the precision of fs is within ± 1000ppm. If it gets beyond this range even for a second, the normal operation might not be performed. So care should be taken. 2. This LSI has the LRCKOUT pin, BCKOUT pin and CK12 pin in order to use the audio ADC into which sample clock and bit clock are required to be input. Connect the LRCKOUT pin to the sample clock of ADC and the LRCK pin of this LSI. And connect the BCKOUT pin to the bit clock pin of ADC and the BCK pin of this LSI. 3. Sixty-four BCK cycles are contained in one LRCK cycle. 4. The DTIN input format can be changed by the setting of resistor with address 01h, or the IFEXMD pin, IIFSEL1 pin and IIFSEL0 pin. Note) 1. When CHNM_BL is set to “1” by the CHNM_BL pin or address 01h of serial data interface, only high-order 16 bits are validated during Full-band mode. 2. Only high-order 16 bits are validated during Half-band mode. DTIN : Connect the data output from ADC BCK : Connect the bit clock output from ADC (64fs) LRCK : Connect the sample clock output from ADC (fs) LRCKOUT pin : sample clock (48kHz) BCKOUT pin : bit clock (48kHz × 64) CK12 pin : master clock (12.288MHz (48kHz × 256) ) Name of iif_mode IFEXMD IIFSEL [1 : 0] Data input format mode-0 0 00 MSB first, Left Justified 24 bits mode-1 0 01 I 2S 24 bits mode-2 0 10 LSB first, Right Justified 24 bits mode-3 0 11 MSB first, Right Justified 24 bits mode-4 1 00 MSB first, Right Justified 20 bits mode-5 1 01 MSB first, Right Justified 16 bits
  • 15 - Timing charts covering what has been described above are presented below. Audio ADC interface timing charts mode-0 mode-1 mode-2 mode-3 mode-4 mode-5 MSB LSB LRCK BCK DAOUT Left channel MSB LSB LRCK BCK DAOUT Left channel LSB MSB LRCK BCK DAOUT Left channel MSB LSB LRCK BCK DAOUT Left channel MSB LSB LRCK BCK DAOUT Left channel MSB LSB LRCK BCK DAOUT Left channel
  • 16 - Application Circuit 1.1V reference voltage 2.5VA RF output 2.5VD LPF RL 1 2 3 4 5 6 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 7 8 TESTMD IFEXMD SMCK IIFSEL1 IIFSEL0 CHNM_BL EXCKSEL DIVCODE PCMID VDD EMPIN VSS SCLK SWDT XSCEN CSOD DTIN VCOT DT2_INF APAVS APAVD APVGS APCPO APS 2.5VA RxC2 APX VDD VSS PLVAR PLREF TEST6 TEST7 TEST5 TEST4 TEST2 TEST0 VDD TEST3 TEST1 V SS DAVREF DAVRO RREF DAAVD VSS DACK DAAVS DAAOUT VDD DAPD LRCK BCKOUT Audio Reset circuit A/D converter CK12 VSS BCK LRCKOUT CSST OSCI V DD OSCO XSM XTST V SS X'tal 24.576MHz XTCK4 MST XRST Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. C 1 = 0.1µF R1 = 2.2kΩ C2 = 4700pF Rx = 4.7MΩ
  • 17 - Notes on Operation ‹ The loop filter portion of the PLL block is important for the characteristics. Therefore, the loop filter should be located as close to the IC pin as possible and surrounded by AGND. In addition, temperature compensation parts should be used for the loop filter capacitor and resistor. ‹ The CXD4016R generates a delay during transmission. Labeling the sampling frequency as fs, the delay time is 192/fs [s] in full-band mode. For example, when fs = 48kHz, the delay time is 4ms. In addition, in half- band mode the delay time is 384/fs [s]. In this case for example, when fs = 48kHz, the delay time is 8ms. Note that a delay is also generated during reception by the receive side IC CXD4017R. See the CXD4017R data sheet for details. CXD4016R Evaluation Board

Description

The CXD4016R evaluation board is a dedicated board designed to allow easy evaluation of the CXD4016R which was developed for transmission of infrared spatial digital audio communication. Optical digital and analog (pin jack) circuits are mounted, and can be switched by a switch. The input audio signal is converted to an infrared spatial digital audio communication system format RF signal by the CXD4016R, and output from a SMB connector. ‹ Supply voltage : + 5V single power supply ‹ Analog and optical digital audio input can be selected Operating Conditions ‹ Supply voltage : + 5V (typ.) ‹ Current consumption : 150mA (typ.) ‹ Input signal : Analog or optical digital audio signal Operation Method The CXD4016R evaluation board allows easy evaluation simply by providing the power supply and inputting an analog or optical digital audio signal. The evaluation procedure is as follows. 1. Connect the power supply to the power supply connection pin J5. 2. SW1 is the manual reset switch. A reset is applied automatically during power-on, but this switch is used to perform reset manually. 3. The DIVCODE pin can be set by DIP switch S2-1. The DIVCODE pin is set low when this switch is OFF, and high when ON. 4. The CHNM_BL pin can be set by DIP switch S2-2. The CHNM_BL pin is set low when this switch is OFF, and high when ON. 5. The IFEXMD pin can be set by DIP switch S2-4. The IFEXMD pin is set low when this switch is OFF, and high when ON 6. The IIFSEL1 pin can be set by DIP switch S2-5. The IIFSEL1 pin is set low when this switch is OFF, and high when ON. 7. The IIFSEL0 pin can be set by DIP switch S2-6. The IIFSEL0 pin is set low when this switch is OFF, and high when ON. 8. The audio signal can be selected by DIP switch S2-7. The optical digital audio signal is selected when this switch is OFF, and the analog audio signal when ON. 9. Connect the optical digital audio signal to the U8 square optical connector. 10. Connect the analog audio signal to the J1 pin jack.

  • 18 - 11. When the analog audio signal is selected, the sampling frequency can be changed by DIP switch S2-8. 48kHz is set when this switch is OFF, and 44.1kHz when ON. 12. Always set DIP switches other than noted above to OFF. The above contents are listed in the tables below for reference. 13. Light emitting diode D1 is off when DIVCODE is low, and lighted when DIVCODE is high. 14. Light emitting diode D2 is off when CHNM_BL is low, and lighted when CHNM_BL is high. 15. Light emitting diodes D3 and D4 indicate the sampling frequency of the audio signal. This relationship is shown in the table below. 16. Light emitting diodes D5 to D8 are not used. 17. The infrared spatial digital audio communication system format RF signal is output from SMB connector J8. 18. J2 and J3 are not used. S1 Mode

1 Always OFF

2 Always OFF

3 Always OFF

4 Always OFF

5 Always OFF

6 Always OFF

7 Always OFF

8 Always OFF

1 OFF : DIVCODE = L, ON : DIVCODE = H

2 OFF : CHNM_BL = L, ON : CHNM_BL = H

4 OFF : IFEXMD = L, ON : IFEXMD = H

5 OFF : IIFSEL1 = L, ON : IIFSEL1 = H

6 OFF : IIFSEL0 = L, ON : IIFSEL0 = H

7 OFF : Optical digital, ON : Analog

8 OFF : 48kHz, ON : 44.1kHz (only when the analog audio signal is selected) D3, D4 Sampling frequency Off, off 44.1kHz Off, lighted 48kHz Lighted, lighted 32kHz Flashing, flashing Unlock

  • 19 - CXD4016R EVB Semiconductor Parts List FPGA Operation 1. Selects the optical digital audio signal or the analog audio signal selected by S2-7. 2. Converts the selected audio signal to the DTIN pin input format set by S2-4, S2-5 and S2-6. 3. Detects the sampling frequency. Parts No. Product name Manufacturer U1, 3 NJM2100M New Japan Radio U2 AK5353VT Asahi Kasei Microsystems U4, 21 TC74LCX541F Toshiba U5 CXD4016R SONY U6 TC74VHC04F Toshiba U7 CS8415A-CZ Cirrus Logic U8 TORX141P Toshiba U9 FXO-31FL 24.576MHz Kyocera Kinseki U10 EP1K100QI208-2 ALTERA U11 EPC2LI20 ALTERA U12 FXO-31FL 22.5792MHz Kyocera Kinseki U13, 14, 15, 16, 17, 18 LM317A National Semiconductor U19, 20 TL7705CP Texas Instruments U22 AD8057ART Analog Devices Q1 2SC2223L NEC D1, 2 TLG124 Toshiba D3, 4 TLY124 Toshiba D5, 6 TLO124 Toshiba D7, 8 TLR124 Toshiba D9 to 20 1S1588 Toshiba
  • 20 - Circuit Diagram (High-speed Signal) (High-speed Signal) (Middle-speed Signal) (High-speed Signal) (High-speed Signal) RFOUT DAAOUT PWXRST XRSTPW1 XRSTPW2 AIF SDTO_1 LRCK_AD MCLK SCLK_AD PDN POWER DIF PRO COPY EMPH RERR RCBL CHS NVERR OSCLK OLRCK SDOUT AUDIO U C RST ORIG RMCK PLD1 SCLK_AD DT2_INF LRCKOUT IIFSEL1 IFEXMD EMPIN CSST PCMID CSOD LRCK BCKOUT BCK XRSTPW1 XRSTPW2 SDTO_1 LRCK_AD MCLK COPY EMPH RST RERR RCBL PRO CHS NVERR OSCLK OLRCK SDOUT AUDIO U C ORIG RMCK PDN IIFSEL0 CHNM_BL DIVCODE EXCKSEL CK12 XRST XSCEN SCLK SWDT APS_XRST DTIN DAPD CXD4016R DT2_INF DTIN BCKOUT BCK LRCK CSOD PCMID SWDT CSST EMPIN IFEXMD IIFSEL1 IIFSEL0 CHNM_BL DIVCODE EXCKSEL CK12 XRST XSCEN SCLK LRCKOUT APS_XRST DAAOUT DAPD CXD4016R EVB circuit diagram (TOP)
  • 21 - AA A AA A A A D D D A A A A A AA AAA A A A A A A D Rch_1 (RED) Lch_1 (WHITE) VA5 VA5 VA5 VA5 VA5 VD5 VD5 VD33 U1A NJM2100M 22µ/16V 0.1µ U1B NJM2100M 2200p RV1A 50k 1 RCA JACK 2P RV1B 50k 4 0.1µ 22µ/16V 22µ/16V U3A NJM2100M C14 22µ/16V C21 22µ/16V C15 0.1µ U3B NJM2100M C22 0.1µ C16 22µ/16V 4.7µ/16V T C20 2200p C19 0.1µ C18 10µ/16V T C12 10µ/16V T C10 4.7µ/16V T 4.7µ/16V T C7 0.1µ C17 4.7µ/16V T C11 0.1µ C13 0.1µ AGND TP5 LC-2S-BK DGND TP3 LC-2S-BK AK5353VT 16AINR AINL VREF VCOM AGND VA VD DGND SDTO LRCK MCLK SCLK PDN DIF TTL TST AINR1 TP2 LC-2S-R AINL1 TP1 LC-2S-W MCLK TP4 LC-2S-Y SCLK TP6 LC-2S-G C23 0.1µ 330k R8 4.7k R10 4.7k R11 20k 10k 330 10k 20k 470 R17 330k R18 4.7k R13 20k R14 10k R12 10k R20 4.7k R16 470 R15 330 10k R19 100 R21 100 R22 100 R23 22 R24 100 20k TC74LCX541F 1011 20 G1 GNDY8 V CC SCLK_AD LRCK_AD SDTO_1 MCLK PDN CXD4016R EVB Circuit Diagram (AUDIO)
  • 22 - A D A A DD D A D A A A A A A A A R37 is missing number. VD25D VA25A VA25D VA25P VA5VA5 C29 0.1µ C33 27pF IFEXMD TP25 LC-2S-Y TP23 DAPD LC-2S-Y C30 18p C37 0.1µ C31 0.1µ C34 0.1µ VR1 200 C27 0.1µ C32 0.1µ PLVAR TP7 LC-2S-BL PLREF TP8 LC-2S-Y APS TP9 LC-2S-Y APX TP10 LC-2S-Y C26 0.1µ LRCK TP16 LC-2S-Y BCK TP15 LC-2S-Y DTIN TP12 LC-2S-Y DT2_INF TP11 LC-2S-BL SWDT TP33 LC-2S-Y XSCEN TP32 LC-2S-Y SCLK TP31 LC-2S-Y BCKOUT TP14 LC-2S-BL LRCKOUT TP13 LC-2S-G TP19 LC-2S-BLCK12 IIFSEL1 TP26 LC-2S-G IIFSEL0 TP27 LC-2S-G EXCKSEL TP28 LC-2S-BL TP34 EMPIN LC-2S-BL TP35 PCMID LC-2S-BL TP36 DIVCODE LC-2S-Y TP37 CHNM_BL LC-2S-Y CSOD TP30 LC-2S-G DAVREF TP21 LC-2S-G TP24 DACK LC-2S-Y Y1CX-49G_24.576MHz CXD4016R TESTMD SMCK IFEXMD IIFSEL1 IIFSEL0 EXCKSEL CHNM_BL DIVCODE PCMID EMPIN V DD VSS SCLK XSCEN SWDT CSOD DAPD DACK VDD VSS DAAOUT DAAVD DAAVS DAVREF DAVRO VDD VSS TEST0 TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 PLREF PLVAR APX V DD VSS APS APVGS APCPO APAVD APAVS VCOT DT2_INF DTIN LRCK BCK BCKOUT LRCKOUT CK12 CSST V SS VDD OSCI V SS OSCO XTCK4 XSM MST XTST XRST TP20 LC-2S-YCSST C28 0.1µ R36 2.7k R39 150 R38 910 R35 1.2k R29 R30 100 R31 100 R28 0R27 R32 100 R33 100 R34 22 R43 100 R41 R40 DAAOUT TP22 LC-2S-Y 2SC2223L C35 0.1µ C36 0.01µ R42 4.7k R44 10k R45 DAAOUT_Buf TP29 LC-2S-Y C38 0.01µ TP17 LC-2S-BK AGND TP18 LC-2S-BK DGND R25 2.2k R26 4.7M C25 0.1µ C24 4700p CK12 DTIN DT2_INF EXCKSEL BCK BCKOUT CSST PCMID IIFSEL1 EMPIN IIFSEL0 XRST DAAOUT LRCKOUT LRCK SCLK XSCEN SWDT IFEXMD CHNM_BL DIVCODE CSOD APS_XRST DAPD CXD4016R EVB Circuit Diagram (MAIN)
  • 23 - A D AA D D D D D D D D D A VD33 VD33 VD33 VD33 VA5 AGND TP39 LC-2S-BK C39 0.1µ C46 0.1µ DGND TP40 LC-2S-BK 47µH TORX141P OUT GND V CC NC NC C41 0.01µ CS8415A-CZ 14 15 28COPY VL2+ EMPH RXP0 RXN0 VA+ AGND FILT RSTx RMCK RERR PRO RCBL CHS NVERR OSCLK OLRCK SDOUT AUDIOx DGND3 DGND2 DGND VL+ H/S U C VL3+ ORIG R61 1.2k C47 0.1µ C45 4700p C42 0.01µ C44 1000p C43 0.1µ C40 0.01µSPDIF TP38 LC-2S-Y 74VHC04F 7 8 141A GND 4Y V CC R48 47k R47 100 R52 22 R54 100 R56 100 R58 0 R49

100 R50

C U CXD4016R EVB Circuit Diagram (DIGITAL INTERFACE)

  • 24 - DDDDD D D D D D DD D D D D D D D D ONON IFdata1 IFdata2 IFdata1 IFdata3 IFdata4 IFdata3 IFdata5 IFdata5 IFdata4 IFdata2 IFdata6 IFdata7 IFdata9 IFdata10 IFdata8 DSW2_6 DSW2_4 DSW2_1 DSW2_2 DSW2_3 DSW2_5 DSW2_7 DSW2_8 IFdata10 IFdata9 IFdata8 IFdata7 IFdata6 LED3 LED2 LED4 LED1 LED5 LED6 LED7 LED8 DSW2_1 DSW2_2 DSW2_3 DSW2_4 DSW2_5 DSW2_6 DSW2_7 DSW2_8 LED2 LED4 LED3 LED1 LED6 LED8 LED7 LED5 VD25B VD33 VD33 VD33 VD25B VD33 VD33 VD33 VD33 VD25B VD25B VD25B C74 0.1µ RA3 M5-1-102J1 COM XG4C-1031 5 6 7 8 9 10 TCK TDO GND Vcc TMS NC NC NC TDI GND U12 FXO-31FL_22.5792MHz VDDOUT INHXGND C49 0.1µ C76 0.1µ C72 0.1µ C75 0.1µ IL-10P-S3EN2 GND GND GND GND GND TP42 LC-2S-Y MCLK TP43 LC-2S-BL LRCK_AD TP44L C-2S-Y SDTO11 SDOUT LC-2S-BL TP47 LC-2S-Y TP50 RMCK RA2 M9-1-103J COM TP41 LC-2S-G SCLK_AD C71 0.1µ OSCLK LC-2S-Y TP49 C50 0.1µ OLRCK LC-2S-G TP48 C67 0.1µ C62 0.1µ A6E-8104 C63 0.1µ C55 0.1µ C70 0.1µ C61 0.1µ C57 0.1µ C69 0.1µ C54 0.1µ C52 0.1µ C56 0.1µ C58 0.1µ RA5 M9-1-103J COM C60 0.1µ C51 0.1µ C64 0.1µ C59 0.1µ C66 0.1µ C53 0.1µ C65 0.1µ FXO-31FL_24.576MHz VDD OUT INHX GND C48 0.1µ C68 0.1µ IL-10P-S3EN2 GND GND GND GND GND RA1 M9-1-103J COM RA4 M9-1-103J COM A6E-8104 TH11 TH TH10 TH TH8 TH TH7 TH TH1 TH TH2 TH TH4 TH TH3 TH TH6 TH TH5 TH C73 0.1µ TH12 TH TH14 TH TH15 TH TH13 TH TH9 TH D1 TLG124A FULL/HALF D2 TLG124A CHNM_BL D3 TLY124 Fs_1 D4 TLY124 Fs_0 D5 TLO124 STA_5 D6 TLO124 STA_6 D7 TLR124 STA_7 D8 TLR124 STA_8 R91 R64 R63 10k R82 10k R62 22 R67 100 R69 22 R70 100 R73 100 R75 100 R77 100 R81 R65 100 R66 100 R68 100 R72 100 R74 100 R76 100 R78 100 R79 100 R80 100 R83 100 R84 100 R85 100 R86 100 R87 100 R88 100 R89 100 R90 100 R71 0 TP45 LC-2S-BK DGND TP46 LC-2S-BK DGND U11 EPC2LI20

20 TDO

nInt_Conf VppSel NC NC NC VPP TMS VCC U10 EP1K100QI208-2_1 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 TCK CONF_DONE nCEO TDO V CCIO GND SDTO_1 I_O LRCK_AD CLKUSR_I_O MCLK I_O SCLK_AD PDN I_O RDYnBUSY I_O COPY INIT_DONE GND V CCINT VCCIO GND EMPHx RSTx RERR RCBL PRO I_O CHS NVERR GND V CCINT VCCIO GND OSCLK OLRCK I_O SDOUT I_O AUDIOx V CCIO GND U C I_O ORIG V CCINT GND TMS TRST nSTATUS I_O I_O LED1 LED2 LED3 LED4 GND DSW1_1 DSW1_2 LOCK DSW1_3 I_O DSW1_4 V CCIO DSW1_5 DSW1_6 DSW1_7 DSW1_8 RMCK V CCINT CRYST22M I_O GL_CLK1 GND V CC_CKLK Ded_Input GlobalCLK1 Ded_Input GND_CLK GND LED5 V CCIO LED6 I_O LED7 LED8 I_O DSW2_1 V CCINT DSW2_2 I_O DSW2_3 I_O DSW2_4 DSW2_5 V CCIO I_O DSW2_6 I_O DSW2_7 I_O DSW2_8 nCONFIG VCCINT MSEL1 MSEL0 GND V CCIO SWDT DAPD XSCEN I_O SCLK EMPIN GND VCCIO I_O PCMID I_O DIVCODE GND VCCINT CHNM_BL EXCKSEL IIFSEL0 IIFSEL1 GND V CCINT IFEXMD XRST I_O CSST I_O CK12 GND VCCIO CSOD LRCKOUT I_O BCKOUT BCK APS_XRST GND VCCIO USER_IO LRCK DTIN DT2_INF GND VCCINT TDI nCE DCLK DATA0 DATA1 DATA2 DATA3 I_O DATA4 DATA5 I_O DATA6 V CCIO DATA7 IFdata1 IFdata2 I_O IFdata3 GND IFdata4 I_O IFdata5 I_O I_O I_O V CCIO I_O DEV_CLRn GND Ded_Input CRYST24M Ded_Input VCCINT DEV_OE I_O GND I_O I_O I_O I_O I_O V CCIO I_O IFdata6 I_O IFdata7 I_O IFdata8 VCCINT I_O IFdata9 nRS IFdata10 nWS CS nCS MCLK PDN SDTO_1 COPY RST EMPH RERR RCBL PRO OSCLK CHS OLRCK SDOUT AUDIO ORIG U C SCLK_AD LRCK_AD NVERR IIFSEL1 IFEXMD DTIN RMCK XRSTPW2 CSOD XRSTPW1 IIFSEL0 CSST BCK DT2_INF BCKOUT LRCK LRCKOUT CK12 PCMID XRST EMPIN CHNM_BL EXCKSEL DIVCODE SCLK XSCEN SWDT APS_XRST DAPD CXD4016R EVB Circuit Diagram (PLD)

  • 25 - A A A A A A A A A A A A A A A A D D D D A A A A A A A A A A D D D D A AA D D D D AA AA A D D D VD25B VD5 VA5 VD33 VA25D VD25D VA25P VA25A C90 0.1µ 1S1588 C95 10µ/16V C83 0.1µ C84 47µ/16V C89 47µ/16V D12 1S1588 C79 0.1µ C82 47µ/16VTP53 LC-2S-BK AGND C77 22µ/16V C80 47µ/16V C81 0.1µTP52 LC-2S-BK AGND C78 0.1µ TP51 LC-2S-R +5V C92 0.1µ D10 1S1588 C96 10µ/16V C85 0.1µ C86 47µ/16V C91 47µ/16V D13 1S1588 C94 0.1µ 1S15881 C97 10µ/16V C87 0.1µ C88 47µ/16V C93 47µ/16V D14 1S1588 C105 0.1µ D15 1S1588 VR5

2 C110

10µ/16V C98 0.1µ C99 47µ/16V C104 47µ/16V D18 1S1588 C107 0.1µ D19 1S1588 D16 1S1588 C101 47µ/16V C100 0.1µ C106 47µ/16V C111 10µ/16V D20 1S1588 C108 47µ/16V C109 0.1µ D17 1S1588 C103 47µ/16V C112 10µ/16V C102 0.1µ U13 LM317A 2VIN ADJ VOUT U14 LM317A 2VIN ADJ VOUT U16 LM317A 2VIN ADJ VOUT U17 LM317A 2VIN ADJ VOUT U15 LM317A 2VIN ADJ VOUT U18 LM317A 2VIN ADJ VOUT TP54 LC-2S-G D2.5V_B SN3-200 SN3-200 SN3-200 SN3-200 SN3-200 SN3-200 SN3-200 SN3-200 RM1 RM2 RM3 RM6 RM5 RM4 TP57 LC-2S-R D3.3V TP55 LC-2S-G D2.5V_D TP58 LC-2S-O A2.5V_D TP59 LC-2S-O A2.5V_A TP56 LC-2S-O A2.5V_P R94 240 R93 240 R92 240 R104 240 R105 240 R106 240 VR4 500 R103 270 R100 750 R97 270 VR3 500 R102 270 R99 750 R96 270 VR6 500 R113 270 R109 750 R107 270 VR7 500 R114 270 R110 750 R108 270 VR2 500 R101 270 R98 750 R95 270 R111 270 R112 100 IL-2P-S3EN2 JP1 CXD4016R EVB Circuit Diagram (POWER)

  • 26 - D D D D D td = 60ms td = 60ms VD5VD5 VD5 VD5 VD5 VD25B C117 0.1µ U19 TL7705CP 4 5 8Vref RESIN Ct GND RESET RESET VsSENSE VCC SW1 AB-15AH1 C113 0.1µ C116 4.7µ/16V T C119 0.1µ U20 TL7705CP 4 5 8Vref RESIN Ct GND RESET RESET VsSENSE V CC C114 0.1µ C118 4.7µ/16V T C115 0.1µ TP60 LC-2S-Y XRSTPW1 TP61 LC-2S-Y XRSTPW2 R115 10k R116 10k R118 10k R117 10k R119 10k U21 TC74LCX541F 10 11 20G1 GND Y8 VCC XRSTPW1 XRSTPW2 CXD4016R EVB Circuit Diagram (RESET)
  • 27 - A A A A A A A A A A A A A A A Emitter Voltage Source RF OUT VA5 VA5 F-CONNECTOR NF-R-2 L10 68µH (Large Size) L11 6.8µH C127 27p C128 120p C129 120p IL-2P-S3EN2 L12 12µH C123 0.1µ C120 0.1µ TP64 LC-2S-BK AGND C130 10p VR9 10k C126 2200p U22 AD8057ART 5OUT V EE IN+ IN– VCC C124 0.1µ C125 2200p C122 TP62 LC-2S-BK AGND C121 SMB TP63 LC-2S-Y TX_LED R125 2.2k R121 2.2k R120 R124 R122 300 R123 VR8 10k DAAOUT CXD4016R EVB Circuit Diagram (RFOUT)
  • 28 - Pattern Diagram CXD4016R EVB A Side Pattern Diagram CXD4016R EVB B Side Pattern Diagram
  • 29 - CXD4016R EVB GND Layer Pattern Diagram CXD4016R EVB Power Supply Layer Pattern Diagram
  • 30 - CXD4016R EVB A Side Silk Diagram CXD4016R EVB B Side Silk Diagram
  • 31 - Sony Corporation Package Outline (Unit : mm) SONY CODE JEITA CODE JEDEC CODE LQFP-64P-L023 P-LQFP64-10X10-0.5 PACKAGE MATERIAL TERMINAL TREATMENT TERMINAL MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING

42 ALLOY

0.32g PACKAGE STRUCTURE 64PIN LQFP (PLASTIC) DETAIL A A 11 6 3348 1.5 – 0.1 + 0.2 0° to 8° 12.0 ± 0.2 10.0 ± 0.1 b 0.1 ± 0.1 0.5 ± 0.2 DETAIL B 0.145 ± 0.055 0.5 0.08 M 0.25 0.6 ± 0.15 0.20 ± 0.05 0.08 S S LEAD PLATING SPECIFICATIONS ITEM LEAD MATERIAL 42 ALLOY SOLDER COMPOSITION Sn-2%Bi PLATING THICKNESS 5-20µm SPEC.