Amplifier

CXD3057R

Sony Corporation

CD Digital Signal Processor with Built - in RF Amplifier and Digital Servo, Digital High - Bass Boost

Manufacturer: Sony Corporation

Document: 27 Pages / 342Kb

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Technical content

Features

All digital signal processing during playback is performed with a single chip Highly integrated mounting possible due to a built-in RF amplifier RF Block Supports 4× speed playback CD RF system equalizer Supports pickup built-in RF summing amplifier Gain level switch TE balance adjustment function Digital Signal Processor (DSP) Block Supports CAV (Constant Angular Velocity) playback Frame jitter free 0.5× to 4× speed continuous playback possible Allows relative rotational velocity readout Supports variable pitch playback The bit clock, which strobes the EFM signal, is generated by the digital PLL. EFM data demodulation Enhanced EFM frame sync signal protection Refined super strategy-based powerful error correction C1: double correction, C2: quadruple correction Supported during 4× speed playback Noise reduction during track jumps Auto zero-cross mute Subcode demodulation and subcode-Q data error detection Digital spindle servo 16-bit traverse counter Asymmetry correction circuit CPU interface on serial bus Error correction monitor signal, etc. output from CPU interface Servo auto sequencer Fine search performs track jumps with high accuracy Digital audio interface outputs Digital level meter, peak meter Bilingual compatible VCO control mode CD TEXT data demodulation Digital Servo (DSSP) Block Microcomputer software-based flexible servo control Offset cancel function for servo error signal Auto gain control function for servo loop E:F balance, focus bias adjustment functions Surf jump function supporting micro two-axis Tracking filter: 6 stages, Focus filter: 5 stages Digital Filter, DAC and Analog Low-pass Filter Blocks Digital dynamic bass boost and high boost Bass Boost: 4th-order IIR 24dB/Oct +10dB/+14dB/+18dB/+22dB High Boost: Second-order IIR 12dB/Oct +4dB/+6dB/+8dB/+10dB Independent turnover frequency selection possible Bass Boost: 125Hz/160Hz/200Hz High Boost: 5kHz/7kHz CD Digital Signal Processor with Built-in RF Amplifier and Digital Servo + Digital High & Bass Boost Digital dynamics (compressor) Volume increased by +5dB at low level 8× oversampling digital filter (attenuation: 61dB, ripple within band: ±0.0075dB) Digital signal output possible after boost Serial data format selectable from (output) 20 bits/18 bits/16 bits (rearward truncation, MSB first) Digital attenuation: –∞ , –60 to +6dB, 2048 steps (linear) Soft mute Digital de-emphasis

Applications

Absolute Maximum Ratings (Ta = 25°C) Supply voltage 1 V DD , XVDD VSS – 0.5 to +3.5 V Input voltage 1 V I1V SS – 0.3 to VDD + 0.3 V Output voltage 1 V O 1V SS – 0.3 to VDD + 0.3 V Supply voltage 2 IOVDD 0 to 2, AVDD 0 to 5 IOVSS – 0.5 to +4.5 V Input voltage 2 V I2I O V SS – 0.3 to IOVDD + 0.3 V Output voltage 2 V O 2I O V SS – 0.3 to IOVDD + 0.3 V Storage temperature Tstg –55 to +150 °C Supply voltage difference IOVSS , AVSS , XVSS – VSS –0.3 to +0.3 V XV DD – VDD –0.3 to +0.3 V IOVDD , AVDD , XVDD – VDD –0.3 to +0.3 V (IOVDD , AVDD , XVDD < 2.3V) Recommended Operating Conditions Supply voltage 1 V DD , XVDD 2.5 ± 0.2 V Supply voltage 2 IOVDD 0 to 2, AVDD 0 to 5 3.3 ± 0.3 V Operating temperature Topr –40 to +85 °C I/O Pin Capacitance Input capacitance CI 7 (Max.) pF Output capacitance CO 7 (Max.) pF I/O capacitance C I/O 7 (Max.) pF Note) Measurement conditions VDD = VI = 0V fM = 1MHz

– 2 – CXD3057R Block Diagram Bass Boost Block CD Signal Processor Block RFamp Block SERVO Block MIRR DFCT FOK SERVO Interface PWM Generator DAC SERVO DSP A/D Converter TE FE VC APC ATT EQ AMP CPU Interface Servo Auto Sequencer Digital CLV D/A Interface EFM Demodulator Sub Code Processor Asymmetry Corrector Digital PLL DC/DC Converter Error Corrector 32K RAM LPF LPF Clock Generator Digital OUT Selector SSTP COUT ATSK GFS XUGF WFCK EMPH WDCK C2PO SCOR SENS CLOK XLAT DATA EXCK SBSO AOUT2 VREFR LMUT RMUT VREL AOUT1 EMPHI LRCKI PCMDI BCKI XTACN XTSL XTAI BCK PCMD LRCK XRST TES1 TEST AV DD 0 to 5 AV SS 0 to 5 IOVDD 0 to 2 IOVSS 0 to 2 VDD VSS MIRR DFCT FOK TEO E F FEO A B C VC SFDR SRDR TFDR TRDR FFDR FRDR TEI FEI LOCK MDP XTAO VCTL VPCO DOUT SQCK SQSO SCLK SYSM D PD PDSENS LD RFACI BIAS ASYI DDVROUT DDVRSEN DDCR ASYO CLTV FIFO FILI PCO XPCK RFDCO AC_SUM EQ_IN RFC RFACO SUM

– 3 – CXD3057R Pin Configuration 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 301 70 69 68 67 63646566 61627172 737481828384 7576777888 87 86 85 79808990 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 RMUT IOVDD 0 NC AV DD 2 AOUT2 VREFR AV SS 2 AV SS 1 VREFL AOUT1 AV DD 1 XV DD XTAI XTAO XV SS NC IOVSS 2 TES1 TEST DOUT IOV DD 2 EMPHI EMPH VDD BCK PCMD VSS LRCK LRCKI PCMDI LMUT BCKI NC NC XTSL DDCR IOVSS 0 AV SS 5 XTACN DDVRSEN SQSO DDVROUT SQCK AV DD 5 SBSO PCO EXCK FILI XRST FILO SYSM CLTV DATA AV SS 3 VSS VCTL XLAT VPCO CLOK ASYO VDD ASYI SENS BIAS SCLK AV DD 3 ATSK RFACI WFCK RFACO XUGF AV SS 4 XPCK RFC GFS NC C2PO PD SCOR LD VDD EQ_IN C4M AC_SUM WDCK PDSENS COUT RFDCO NC AV DD 4 MIRR DFCT FOK VSS LOCK MDP SSTP IOVSS 1 SFDR SRDR TFDR TRDR FFDR FRDR IOVDD 1 AV DD 0 AV SS 0 NC E F TEI TEO FEI FEO VC A B C D NC

– 4 – CXD3057R Pin Description Pin No. Symbol I/O Description MIRR DFCT FOK V SS LOCK MDP SSTP IOV SS 1 SFDR SRDR TFDR TRDR FFDR FRDR IOV DD 1 AV DD 0 AV SS 0 NC E F TEI TEO FEI FEO VC A B C D NC AV DD 4 RFDCO PDSENS AC_SUM I/O I/O I/O I/O O I O O O O O O I I I O I O I/O I I I I I/O I O Mirror signal input/output. Defect signal input/output. Focus OK signal input/output. Internal digital GND. GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low. Or this pin inputs when LKIN = "1". Spindle motor servo control output. Disk innermost detection signal input. I/O digital GND. Sled drive output. Sled drive output. Tracking drive output. Tracking drive output. Focus drive output. Focus drive output. I/O digital power supply. Analog power supply. Analog GND. E signal input. F signal input. Tracking error signal input to DSSP block. Tracking error signal output from RF amplifier block. Focus error signal input to DSSP block. Focus error signal output from RF amplifier block. Center voltage output from RF amplifier block. Center voltage input to DSSP block by command switch. A signal input. B signal input. C signal input. D signal input. Analog power supply. RFDC signal output. RFDC signal input to DSSP block by command switch. Reference voltage pin for PD. RFAC summing amplifier output. Power supply 1, 0 1, 0 1, 0 1, 0 1, Z, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 Analog Digital I/O = 3.3V Internal = 2.5V A/D 3.3V RFamp 3.3V

– 5 – CXD3057R Pin No. Symbol I/O Description EQ_IN LD PD NC RFC AV SS 4 RFACO RFACI AV DD 3 BIAS ASYI ASYO VPCO VCTL AV SS 3 CLTV FILO FILI PCO AV DD 5 DDVROUT DDVRSEN AV SS 5 DDCR NC BCKI PCMDI LRCKl LRCK V SS PCMD BCK VDD EMPH EMPHI I O I I O I I I O O I I O I O O I I I I I O O O O I Equalizer circuit input. APC amplifier output. APC amplifier input. Equalizer cut-off frequency adjustment pin. Analog GND. RFAC signal output. RFAC signal input or EFM signal input. Analog power supply. Asymmetry circuit constant current input. Asymmetry comparator voltage input. EFM full-swing output. (Low = V SS , High = VDD ) Wide-band EFM PLL charge pump output. Wide-band EFM PLL VCO2 control voltage input. Analog GND. Multiplier VCO1 control voltage input. Master PLL (slave = digital PLL) filter output. Master PLL filter input. Master PLL charge pump output. Analog power supply. DC/DC converter output. Leave open when not using. DC/DC converter output voltage monitor pin. Connect to analog power supply when not using. Analog GND. Test pin. Normally GND. D/A interface bit clock input. D/A interface serial data input. (2's COMP , MSB first) D/A interface LR clock input. D/A interface LR clock output. f = Fs Internal digital GND. D/A interface serial data output. (2's COMP , MSB first) D/A interface bit clock output. Internal digital power supply. High when the playback disc has emphasis, low it has not. High when de-emphasis is ON, low when input OFF . Power supply 1, 0 1, Z, 0 Analog 1, Z, 0 1, 0 1, 0 1, 0 1, 0 RFamp 3.3V ASYM 3.3V DC/DC 3.3V Digital I/O = 3.3V Internal = 2.5V

– 6 – CXD3057R Pin No. Symbol I/O Description 100 101 102 103 104 IOV DD 2 DOUT TEST TES1 IOVss2 NC XV SS XTAO XTAI XV DD AV DD 1 AOUT1 VREFL AV SS 1 AV SS 2 VREFR AOUT2 AV DD 2 NC IOV DD 0 RMUT LMUT NC XTSL IOV SS 0 XTACN SQSO SQCK SBSO EXCK XRST SYSM DATA V SS XLAT O I I O I O O O O O O I I O I O I I I I I I/O digital power supply. Digital Out output. Test pin. Normally GND. Test pin. Normally GND. I/O digital GND. Master clock GND. Crystal oscillation circuit output. Crystal oscillation circuit input. Master clock power supply. Analog power supply. Lch analog output. Lch reference voltage. Analog GND. Analog GND. Rch reference voltage. Rch analog output. Analog power supply. I/O digital power supply. Rch "0" detection flag. Lch "0" detection flag. Crystal selection input. Low when the crystal is 16.9344MHz; high when the crystal is 33.8688MHz. I/O digital GND. Oscillation circuit control. Self-oscillation when high, oscillation stop when low. Subcode Q 80-bit and PCM peak and level data output. CD TEXT data output. SQSO readout clock input. Subcode P to W serial output. SBSO readout clock input. System reset. Reset when low. Mute input. Muted when high. Serial data input from CPU. Internal digital GND. Latch input from CPU. The serial data is latched at the falling edge. Power supply 1, 0 1, 0 1, 0 1, 0 1, 0 X'tal 2.5V Digital I/O = 3.3V Internal = 2.5V Lch 3.3V Rch 3.3V Digital I/O = 3.3V Internal = 2.5V

– 7 – CXD3057R Pin No. Symbol I/O Description 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 CLOK V DD SENS SCLK ATSK WFCK XUGF XPCK GFS C2PO SCOR V DD C4M WDCK COUT NC I O I I/O O O O O O O O O I/O Serial data transfer clock input from CPU. Internal digital power supply. SENS output to CPU. SENS serial data readout clock input. Anti-shock input/output. WFCK output. XUGF output. Output MNT0, RFCK, SOUT by command switch. XPCK output. Output MNT1, SOCK by command switch. GFS output. Output MNT2, XROF , XOLT by command switch. C2PO output. Output MNT3, GTOP by command switch. High output when the subcode sync, S0 or S1, is detected. Internal digital power supply. 4.2336MHz output. 1/4 frequency-division output of the V16M in CAV-W mode and variable pitch mode. Word clock output. f = 2Fs. GRSCOR output by command switch. Track number count signal input/output. Power supply 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 Digital I/O = 3.3V Internal = 2.5V Notes) PCMD is a MSB first, two's complement output. GTOP is used to monitor the frame sync protection status. (High: sync protection window released.) XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before sync protection. XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point coincide. The GFS signal goes high when the frame sync and the insertion protection timing match. RFCK is derived from the crystal accuracy, and has a cycle of 136µs. C2PO represents the data error status. XROF is generated when the 32K RAM exceeds the ±28 frame jitter margin. C4M is a 4.2336MHz output that changes in CAV-W mode and variable pitch mode. FSTO is the 2/3 frequency-division output of the XTAI pin. SOUT is the serial data output inside the servo block. SOCK is the serial data readout clock output inside the servo block. XOLT is the serial data latch output inside the servo block.

– 8 – CXD3057R Monitor Pin Output Combinations Command bit Output data XUGF MNT0 RFCK C4M SOUT XPCK MNT1 XPCK GSTO SOCK GFS MNT2 XROF GFS XOLT C2PO MNT3 GTOP C2PO C2PO SRO1 MTSL1 MTSL0 Reset Timing when Power on Power on with XRST pin low. Set XRST pin high after holding it low 100ns or more to cancel reset.

– 9 – CXD3057R RF Block Pin Equivalent Circuit Pin No. Symbol I/O Equivalent circuit Description VC VC 1pF 1pF

19 E I

Tracking error amplifier input.

20 F I

21 TEI I Tracking error signal input to DSSP

block. 22 TEO O Tracking error amplifier output.

23 FEI I Focus error signal input to DSSP

block. 24 FEO O Focus error amplifier output. 25 VC I/O (AV DD 4 – AVSS 4)/2 voltage output.

– 10 – CXD3057R Pin No. Symbol I/O Equivalent circuit Description RF summing amplifier and focus error amplifier input. NC AV DD 4 Analog power supply. 32 RFDCO I/O RFDC amplifier output.

33 PDSENS I APC amplifier reference voltage

(GND signal) input. 15kΩ 30kΩ 30kΩ

26 A I

27 B I

28 C I

29 D I

0.5pF 100Ω 10kΩ 10kΩ 59kΩ 34 AC_SUM O RFAC summing amplifier output.

– 11 – CXD3057R Pin No. Symbol I/O Equivalent circuit Description Equalizer circuit input. 36 LD O APC amplifier output. 37 PD I APC amplifier input. VC 4kΩ 4kΩ 4kΩ 4kΩ

35 EQ_IN I

39 RFC I Equalizer cut-off frequency

adjustment. 500Ω 57kΩ 10kΩ 1kΩ

38 NC — — —

40 AV SS 4 — Analog GND. — 41VC 25Ω 41 RFACO O RFAC amplifier output.

– 12 – CXD3057R

Electrical Characteristics

DC Characteristics DD = XVDD = 2.5 ± 0.2V , IOVDD 0 to 2 = AVDD 0 to 5 = 3.3 ± 0.3V, VSS = XVSS = IOVSS = AVSS = 0V, Topr = –40 to +85°C) V V V V V V V µA µA µA 0.7V DD 0.7VDD VSS VDD – 0.4 VDD – 0.4 VDD – 0.4 VDD – 0.4 –10 –10 Schmitt input Analog input IOH = –2.4mA IOL = 4mA IOH = –1.2mA IOL = 2mA IOH = –2.4, –4.8, –7.2, –9.6mA IOL = 4, 8, 12, 16mA IOH = –0.28mA IOL = 0.36mA VIN = VSS or VDD VIN = VDD VIN = VSS or VDD 0.5 100 0.2VDD 0.2VDD VDD 0.4 0.4 0.4 0.4 240 Input voltage (1) Input voltage (2) Input voltage (3) Output voltage (1) Output voltage (2) Output voltage (3) Output voltage (4) Input leak current Input leak current (with pull-down resistor) Tri-state output leak current (when high impedance) UnitMax.Typ.Min.ConditionsItem High level input voltage Low level input voltage High level input voltage Low level input voltage Hysteresis Input voltage High level output voltage Low level output voltage High level output voltage Low level output voltage High level output voltage Low level output voltage High level output voltage Low level output voltage ∗1, ∗3, ∗9 ∗4, ∗12 ∗5, ∗8, ∗9 ∗11 ∗1, ∗2, ∗9 Applicable pins VIH (1) VIL (1) VIH (2) VIL (2) Vt+ – Vt– VIN (3) VOH (1) VOL (1) VOH (2) VOL (2) VOH (3) VOL (3) VOH (4) VOL (4) II IIH IOZ

– 13 – CXD3057R Applicable pins ∗1 PCMDI, EMPHI, TEST, TES1, XTSL, XTACN, SYSM, DATA ∗2 BCKI, LRCKI, SQCK, EXCK, XRST, XLAT, CLOK, SCLK ∗3 SSTP ∗4 E, F , TEI, FEI, A, B, C, D, PDSENS, EQ_IN, PD, RFC, RFACI, BIAS, ASYI, VCTL, CLTV, FILI, DDVRSEN, DDCR ∗5 SFDR, SRDR, TFDR, TRDR, FFDR, FRDR, LRCK, PCMD, BCK, EMPH, RMUT, LMUT, SQSO, SBSO, WFCK, XUGF , XPCK, GFS, C2PO, SCOR, C4M, WDCK ∗6 ASYO ∗7 DOUT ∗8 MDP , VPCO, PCO, SENS ∗9 MIRR, DFCT, FOK, LOCK, ATSK, COUT ∗10 TEO, FEO, AC_SUM, LD, RFACO, DDVROUT, AOUT1, VREFL, VREFR, AOUT2 ∗11 FILO ∗12 VC, RFDCO

– 14 – CXD3057R 2. AC Characteristics (1) XTAI pin (a) When using self-oscillation DD = XVDD = 2.5 ± 0.2V , IOVDD 0 to 2 = AVDD 0 to 5 = 3.3 ± 0.3V, VSS = XVSS = IOVSS = AVSS = 0V, Topr = –40 to +85°C) Oscillation frequency Item fMAX Symbol MHz Unit (b) When inputting pulses to XTAI pin (VDD = XVDD = 2.5 ± 0.2V , IOVDD 0 to 2 = AVDD 0 to 5 = 3.3 ± 0.3V, VSS = XVSS = IOVSS = AVSS = 0V, Topr = –40 to +85°C) High level pulse width Low level pulse width Pulse cycle Input high level Input low level Rise time, fall time Item t WHX tWLX tCX VIHX VILX tR , tF Symbol 6.6 6.6 14.6 1.7 Min. Typ. 32.7 32.7 59.5 0.7 Max. ns ns ns V V ns Unit tR tF tWHX tWLX tCX VILX VIHX × 0.1 VIHX × 0.9 VIHX XTAI VDD /2 Note) When the pulse is input to the XTAI pin, be sure to input it via the capacitor. XTSL = L, $AEXX1 CKSL (1, 0) = 00 XTSL = H, $AEXX1 CKSL (1, 0) = 00 XTSL = H, $AEXX1 CKSL (1, 0) = 01 or 10 or 11 Conditions 16.8 33.5 67.1 Min. Typ. 17.1 34.2 68.4 Max. 16.9344 33.8688 67.7376

– 15 – CXD3057R (2) CLOK, DATA, XLAT, SQCK and EXCK pins (VDD = XVDD = 2.5 ± 0.2V , IOVDD 0 to 2 = AVDD 0 to 5 = 3.3 ± 0.3V, VSS = XVSS = IOVSS = AVSS = 0V, Topr = –40 to +85°C) Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width Command transfer interval EXCK frequency EXCK pulse width SQCK frequency SQCK pulse width COUT frequency (during input)∗ COUT pulse width (during input)∗ Item f CK tWCK tSU tH tD tWL tWCT fT tWT fT tWT fT fWT Symbol 31.3 300 750 750 750 750 7.5 Min. Typ. 30000 30000 0.65 0.65 120000 Max. MHz ns ns ns ns ns ns MHz ns MHz ns kHz µs Unit ∗ Only when $44 and $45 are executed. tWCK tWCK 1/fCK tHtSU tWLtD 1/fT tWT tWT CLOK DATA XLAT EXCK SQCK COUT tWCT

– 16 – CXD3057R (3) SCLK pin tSPWtDLS 1/fSCLK MSB ... ... LSB XLAT SCLK Serial Read Out Data (SENS) (VDD = XVDD = 2.5 ± 0.2V, IOVDD 0 to 2 = AVDD 0 to 5 = 3.3 ± 0.3V, VSS = XVSS = IOVSS = AVSS = 0V, Topr = –40 to +85°C) SCLK frequency SCLK pulse width Delay time Item f SCLK tSPW tDLS Symbol Min. Typ. Max. MHz ns µs Unit 31.3 (4) COUT, MIRR and DFCT pins Operating frequency (VDD = XVDD = 2.5 ± 0.2V, IOVDD 0 to 2 = AVDD 0 to 5 = 3.3 ± 0.3V, VSS = XVSS = IOVSS = AVSS = 0V, Topr = –40 to +85°C) COUT maximum operation frequency MIRR maximum operation frequency DFCT maximum operation frequency Item f COUT fMIRR fDFCTH Symbol Min. Typ. Max. kHz kHz kHz Unit Conditions ∗1 When using a high-speed traverse TZC When the RF signal continuously satisfies the following conditions during the traverse. A = 0.11VDD to 0.23VDD ≤ 25% ∗3 During complete RF signal omission. When settings related to DFCT signal generation are Typ. A B B A + B

– 17 – CXD3057R 1-bit DAC and LPF Block Analog Characteristics (VDD = XVDD = 2.5V, IOVDD 0 to 2 = AVDD 0 to 5 = 3.3V, VSS = XVSS = IOVSS = AVSS = 0V, Topr = +25°C) Total harmonic distortion Signal-to-noise ratio Item dB Unit THD S/N Symbol 1kHz sine wave, 0dB data, 20kHz LPF 1kHz sine wave, 0dB data, AMUT OFF (Using A-weighting filter 20kHz LPF) Conditions Fs = 44.1kHz in all cases. The total harmonic distortion and signal-to-noise ratio measurement circuits are shown below. 22µF AOUT1 (2) VREFL (R) 1µF 100Ω 2200pF 100kΩ Audio Analyzer LPF external circuit diagram Audio AnalyzerCXD3059AR Rch A Lch B DATA RF TEST DISC Block diagram of analog characteristics measurement (VDD = XVDD = 2.5V, IOVDD 0 to 2 = AVDD 0 to 5 = 3.3V, VSS = XVSS = IOVSS = AVSS = 0V, Topr = +25°C) Output voltage Load resistance VREF pin capacitance Item V OUT R L C VREF Symbol 920 Min. Typ. Max. mVrms kΩ µF Unit Applicable pins 928 ∗ Measurement is conducted for the above circuit diagrams with the sine wave output of 1kHz and 0dB. Applicable pins ∗1 AOUT1, AOUT2 ∗2 VREFL, VREFR 0.014 Min. Typ. Max. 0.006

– 18 – CXD3057R RF Block Electrical Characteristics (VDD = XVDD = 2.5V, IOVDD 0 to 2 = AVDD 0 to 5 = 3.3V, VSS = XVSS = IOVSS = AVSS = 0V, Topr = +25°C) Measurement item Input impedance (A, B, C and D) Input impedance (E and F) Input impedance (PD) RF block current consumption (on operation) RF block current consumption (on standby) Output voltage Input voltage Output voltage (on standby) Input voltage range Maximum output current Output impedance Symbol R A,B,C,D R E,F R PD IAVD ISTB VVC VPD VLD stb VPDT VPDB ILD R LD SW conditions Connect to VC except measure- ment pins. Sending command $3AF100 $ADF7CC00 $AD000800 AC input amplitude AC input frequency DC input voltage VPD + 12mV VPD – 12mV VPD DC input current ±3mA 1mA 1mA Bias conditions V DD 2.5V 2.5V 2.5V 2.5V AV DD 3.3V 3.3V 3.3V 3.3V Measurement conditions Pin current Pin current Pin current Pin current Pin current Pin voltage PD input voltage which LD pin voltage is 1.41V Pin voltage Pin voltage Pin voltage Pin voltage Pin voltage Measure- ment pins A, B, C, D E, F PD AV DD 4 AV DD 4 VC LD, PD LD LD LD LD LD APCVC Min. 0.5AVDD – 0.1 100 AV DD – 0.2 1.89 0.43 0.34 1.66 Typ. 0.5AVDD 150 2.14 0.68 0.64 1.91 Max. 0.5AVDD + 0.1 200 2.39 0.93 0.94 2.16 Unit kΩ kΩ M Ω mA mA V mV V V V V V

– 19 – CXD3057R Measurement item Input voltage range Output voltage range Input conversion DC offset voltage Input conversion DC offset temperature drift Offset voltage Frequency characteristics 1 Frequency characteristics 2 Distortion rate Input voltage range Output voltage range Input conversion DC offset voltage Input conversion DC offset temperature drift Frequency characteristics 1 Frequency characteristics 2 Distortion rate Symbol VIR-ACSUM VOR-ACSUM VOF-ACSUM VDF-ACSUM VOFFSUM FSUM1 FSUM2 D SUM VIR-RFDC VOR-RFDC VOF-RFDC VDF-RFDC FRFDC1 FRFDC2 D RFDC SW conditions Sending command $3AA000 $3AA01C $3AA004 $3AA018 $3AA000 $3AA01C $3AA004 $3AA018 AC input amplitude AC input frequency DC input voltage DC input current VC + VAC1/2 VC + VAC1/2 VC + VAC1/2 Bias conditions VDD 2.5V 2.5V AV DD Measurement conditions Pin voltage, A + B + C + D Pin voltage Pin voltage Pin voltage 20 log (V6M/V0.2M) (V6M/V3M) × 100 Pin voltage, A + B + C + D Pin voltage Pin voltage 20 log (V6M/V0.2M) Measure- ment pins RFDC RFDC RFDC RFDC RFDC RFDC RFDC RFDC RFDC RFDC RFDC 61mVp-p 104mVp-p 600mVp-p 61mVp-p 104mVp-p 1.5Vp-p 0.2/6MHz 3MHz 0.2/6MHz 100kHz ACSUM RFDC Min. 0.5AVDD – 0.1 0.47AVDD 0.5AVDD – 0.23 0.7 0.3AVDD – 0.1 0.25AVDD 0.3AVDD – 0.23 Typ. 0.9 0.1 Max. 0.9AVDD + 0.1 0.65AVDD 0.5AVDD + 0.23 1.1 0.7AVDD + 0.1 0.75AVDD 0.3AVDD + 0.23 Unit V V V µV/ V dB dB V V V µV/ dB dB

– 20 – CXD3057R Measurement item Input voltage range Output voltage range Input conversion DC offset voltage Input conversion DC offset temperature drift Offset voltage Frequency characteristics 1 Frequency characteristics 2 Distortion rate Input voltage range Output voltage range Input conversion DC offset voltage Input conversion DC offset temperature drift Offset voltage Frequency characteristics 1 Frequency characteristics 2 Distortion rate Symbol VIR-FE VOR-FE VOF-FE VDF-FE VOFFFE FFE1 FFE2 D FE VIR-TE VOR-TE VOF-TE VDF-TE VOFFTE FTE1 FTE2 D TE SW conditions Sending command $3AA104 $3AA118 $3AA204 $3AA218 $3AA200 AC input amplitude AC input frequency DC input voltage DC input current Bias conditions VDD 2.5V 2.5V AV DD Measurement conditions VC reference about (B + D) and (A + C) Pin voltage Pin voltage Pin voltage 20 log (V100k/V10k) (V50k/V100k) × 100 VC reference about (B + D) and (A + C) Pin voltage Pin voltage Pin voltage 20 log (V100k/V10k) (V50k/V100k) × 100 Measure- ment pins FE FE FE FE FE FE TE TE TE TE TE TE 30mVp-p 52mVp-p 600mVp-p 28mVp-p 45mVp-p 480mVp-p 10/ 100kHz 50kHz 10/ 100kHz 50kHz FE TE Min. 0.375 AV DD 0.5 0.5AVDD – 0.03 –0.06 0.4AVDD 0.5 0.5AVDD – 0.03 –0.075 Typ. ±2.8 ±2.5 Max. 0.625 AV DD AV DD – 0.5 0.5AVDD + 0.03 0.06 0.6AVDD AV DD – 0.5 0.5AVDD + 0.03 0.075 Unit V V V µV/ V dB dB V V V µV/ V dB dB

– 21 – CXD3057R Measurement item Input voltage range Output voltage range Input conversion DC offset voltage Input conversion DC offset temperature drift Offset voltage Frequency characteristics 1 Frequency characteristics 2 Distortion rate Symbol V IR-EQ VOR-EQ VOF-EQ VDF-EQ VOFFEQ FEQ1 FEQ2 D EQ SW conditions Sending command $3AA204 $3AA218 $3AA200 AC input amplitude AC input frequency DC input voltage DC input current Bias conditions V DD 2.5V AV DD Measurement conditions Distortion rate 3% or less, no DC bias Pin voltage Pin voltage Ta = –40 to +85°C Pin voltage 20 log (V100k/V10k) (V720k/V360k) × 100 Measure- ment pins RFACO RFACO RFACO RFACO RFACO RFACO 28mVp-p 45mVp-p 1.2Vp-p 10/ 100kHz 360kHz EQ Min. 0.5 –0.25 –0.5 Typ. ±0.1 Max. 250 AV DD – 0.5 0.25 0.5 Unit mVp-p V V V V dB dB

– 22 – CXD3057R Notes on Operation for RFC Pin Set each impedance of the heavy line shown bellow 0.1Ω or less. Make each wiring length of L1 to L4, L1 ≤ 20mm, L2 ≤ 20mm and L3 + L4 ≤ 40mm. Use the bypass condenser C with capacitance led by resistance (regulator output impedance and wiring resistance to C) or more seeing the figure bellow. Regulator GND OUT 15kΩ 0.1µF AV SS 4 RFC AV DD 4 R AVS C 0.1µF 02 0 4 0 6 0 C [µF] R [Ω ] 80 100 Impedance R tolerance for bypass condenser C

– 23 – CXD3057R DC-DC Converter Characteristics (VDD = XVDD = 2.5 ± 0.2V , IOVDD 0 to 2 = AVDD 0 to 5 = 3.3 ± 0.3V, VSS = XVSS = IOVSS = AVSS = 0V, Topr = –40 to +85°C) Output voltage Output current Item 2.7 100 Min. Typ. Max. V mA Unit 2.3 VO Iope Symbol 2.5 Conditions DC-DC converter application circuit sample Refer to Application Notes on operation. C 2 AV DD 5 DDVROUT C 1 Power supply for DC-DCEQPXGTVGT DDVRSEN AV SS 5 DDCR VOUT GND for DC-DCEQPXGTVGT

– 24 – CXD3057R CPU Interface Timing Spindle Output Servo Output 31.3nsVQ30µs D18 D19 D20 D21 D22 D23 750ns or more Valid CLOK DATA XLAT Registers D0 D1 64tMCK 64tMCK 64tMCK AtMCK AtMCKSFDR SRDR SLD 32tMCK 32tMCK 32tMCK 32tMCK32tMCK32tMCK FCS/TRK FFDR/ TFDR FRDR/ TRDR Output value + A Output value – A Output value 0 BtMCK BtMCK BtMCK BtMCK MCK VQKPVGIGTPWODGT VQKPVGIGTPWODGT MDP Acceleration Z Deceleration 132kHz 7.6µs n . 236 (ns) n = 0 to 31 MDP Acceleration Z Deceleration 264kHz 3.8µs

– 25 – CXD3057R DA Interface CDDSP output selected (1××××× speed playback LRCK = 44.1kHz, BCK = 2.1168MHz) DAC output selected (1××××× speed playback LRCK = 44.1kHz, BCK = 2.8224MHz) $A5EA OBIT1 = 1, OBIT0 = 1 DAC block input timing (LRCK = 44.1kHz, BCK = 2.1168MHz) $A5EA OBIT1 = 1, OBIT0 = 0 $A5EA OBIT1 = 0, OBIT0 = 0 LRCK WDCK BCK 1 24 PCMD R0 Lch MSB (15) L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Rch MSB 23456789 1 0 1 1 1 2 LRCK WDCK BCK 1 32 PCMD R0 Lch MSB (15) L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Rch MSB PCMD R0 Lch MSB (17) L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Rch MSB PCMD R0 Lch MSB (19) L14 L13 L12 L11 L16 L15 L18 L17 L16 L15 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Rch MSB 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 LRCKI BCKI 1 24 PCMDI R0 Lch MSB (15) L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Rch MSB 23456789 1 0 1 1 1 2

– 26 – CXD3057R Application Circuit DDVROUT LRCK PCMD BCK RFDCO MIRR DFCT LOCK COUT WDCK C4M C2PO GFS XPCK XUGF WFCK SBSO LMUT EMPH DOUT Lch Rch RMUT Driver circuit Limit switch PD LD A.GND D C B A VC F E FD TD Driver circuit SLED SPDL SQSO SQCK XRST SYSM DATA XLAT CLOK SENS SCLK SCOR FOK CXD3059AR 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 301 70 69 68 67 63646566 61627172 737481828384 7576777888 87 86 85 79808990 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 RMUT IOVDD 0 NC AV DD 2 AOUT2 VREFR AV SS 2 AV SS 1 VREFL AOUT1 AV DD 1 XV DD XTAI XTAO XV SS NC IOVSS 2 TES1 TEST DOUT IOVDD 2 EMPHI EMPH VDD BCK PCMD VSS LRCK LRCKI PCMDILMUT BCKI NC NC XTSL DDCR IOVSS 0 AV SS 5 XTACN DDVRSEN SQSO DDVROUT SQCK AV DD 5 SBSO PCO EXCK FILI XRST FILO SYSM CLTV DATA AV SS 3 VSS VCTL XLAT VPCO CLOK ASYO VDD ASYI SENS BIAS SCLK AV DD 3 ATSK RFACI WFCK RFACO XUGF AV SS 4 XPCK RFC GFS NC C2PO PD SCOR LD VDD EQ_IN C4M AC_SUM WDCK PDSENS COUT RFDCO NC AV DD 4 MIRR DFCT FOK VSS LOCK MDP SSTP IOV SS 1 SFDR SRDR TFDR TRDR FFDR FRDR IOVDD 1 AV DD 0 AV SS 0 NC E F TEI TEO FEI FEO VC A B C D NC Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 27 – CXD3057R Package Outline Unit: mm Sony Corporation SONY CODE EIAJ CODE JEDEC CODE PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 0.5 b M0.1 DETAIL A DETAIL B b = 0.20 ± 0.03 0.125 ± 0.03

1.7 MAX

1.4 ± 0.1 B A 120PIN LQFP (PLASTIC) LQFP-120P-L01 LQFP120-P-1616 0.8g 13 0 6190 120 0.1 S S S 18.0 ± 0.2 16.0 ± 0.1 (17.0) (0.5)0˚ to 10˚ 0.1 ± 0.05 0.6 ± 0.15 0.25

Product Information

CXD3057R specifications and overview.

Summary

CD Digital Signal Processor with Built - in RF Amplifier and Digital Servo, Digital High - Bass Boost

Description

CD Digital Signal Processor with Built - in RF Amplifier and Digital Servo, Digital High - Bass Boost

Source title CXD3057R Datasheet(PDF) - Sony Corporation

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