Power Management

CXD3027R

Sony Corporation

The CXD3027R is a digital signal processor LSI for CD players. This LSI incorporates a digital servo, high & bass boost, shock-proof memory controller, 1-bit DAC and analog low-pass filter.

Manufacturer: Sony Corporation

Document: 191 Pages / 1Mb

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CXD3027R SONY | Alldatasheet

Document overview

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PDF pages: 191

Technical content

Datasheet sections

Features

All digital signal processing during playback is performed with a single chip
Highly integrated mounting possible due to a built-in RAM Digital Signal Processor (DSP) Block
Supports CAV (Constant Angular Velocity) playback
Frame jitter free
0.5
to 4· speed continuous playback possible
Allows relative rotational velocity readout
Wide capture range playback mode
Spindle rotational velocity following method
Supports 1· to 4· speed playback
Supports variable pitch playback
The bit clock, which strobes the EFM signal, is generated by the digital PLL.
EFM data demodulation
Enhanced EFM frame sync signal protection
Refined super strategy-based powerful error correction C1: double correction, C2: quadruple correction Supported during 4· speed playback
Noise reduction during track jumps
Auto zero-cross mute
Subcode demodulation and subcode-Q data error detection
Digital spindle servo
16-bit traverse counter
Asymmetry correction circuit
CPU interface on serial bus
Error correction monitor signal, etc. output from a new CPU interface
Servo auto sequencer
Fine search performs track jumps with high accuracy
Digital audio interface outputs
Digital level meter, peak meter
Bilingual compatible
VCO control mode
CD TEXT data demodulation
Digital Out can be generated from the audio serial input. (also supported after shock-proof and digital bass boost processing, subcode-Q addition function) Digital Servo (DSSP) Block
Microcomputer software-based flexible servo control
Offset cancel function for servo error signal
Auto gain control function for servo loop
E:F balance, focus bias adjustment functions
Surf jump function supporting micro two-axis
Tracking filter: 6 stages Focus filter: 5 stages Shock-Proof Memory Controller Block
Supports an external 4M-bit/16M-bit DRAM
Time axis-based data linking
ADPCM compression method (uncompressed/4 bits/ 6 bits/8 bits) Digital Filter, DAC and Analog Low-pass Filter Blocks
Digital dynamic bass boost and high boost Bass Boost: 4th-order IIR 24dB/Oct +10dB/+14dB/+18dB/+22dB High Boost: Second-order IIR 12dB/Oct +4dB/+6dB/+8dB/+10dB
Independent turnover frequency selection possible Bass Boost: 125Hz/160Hz/200Hz High Boost: 5kHz/7kHz
Digital dynamics (compressor) Volume increased by +5dB at low level
8· oversampling digital filter (attenuation: 61dB, ripple within band: ±0.0075dB)
Digital signal output possible after boost
Serial data format selectable from (output) 20 bits/ 18 bits/16 bits (rearward truncation, MSB first)
Digital attenuation: –∞ , –60 to +6dB, 2048 steps (linear)
Soft mute
Digital de-emphasis
High-cut filter

Applications

Supply voltage V DD , AVDD –0.3 to +4.6 V
Input voltage V I –0.3 to +4.6 V (VSS – 0.3V to VDD + 0.3V)
Output voltage V O –0.3 to +4.6 V
Storage temperatureTstg –40 to +125 °C
Supply voltage difference AV SS – VSS –0.3 to +0.3 V AV DD – VDD –0.3 to +0.3V (AVDD < 2.2V) AV DD – VDD –0.3 to +1.4V (AVDD = 2.2 to 3.6V) Recommended Operating Conditions
Supply voltage VDD , AVDD 0, 3 2.2 to 3.6 V AV DD 1, 2, DVDD VDD to 3.6 V
Operating temperatureTopr –20 to +75 °C I/O Pin Capacitance
Input capacitance CI 12 (max.) pF
Output capacitance CO 12 (max.) pF Note) Measurement conditions VDD = VI= 0V fM = 1MHz – 1 – E99431B04-PS Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. 120 pin LQFP (Plastic) CD Digital Signal Processor with Built-in Digital Servo + Shock-Proof Memory Controller + Digital High & Bass Boost

– 2 – CXD3027R A0 to A11 D 0 to D 4 XEM P XW IH XQ O K BC K LR C K D O U T PC M D XR ST TEST TES1 D /A Interface EFM dem odulator Error C orrector 32K R AM Sub C ode Processor C lock G enerator Asym m etry C orrector D igital PLL C PU Interface Signal Processor Block C2PO W FCK EM PH GFS XUGF XTAI R FAC ASYI ASYO BIAS FILO FILI PC O C LTV M D P PW M I SEN S D ATA XLAT C LO K SC O R SBSO EXC K W DCK XTAO VPCO VCTL XPC K SQ SO SQ C K D igital C LV SC SY Servo Block SER VO Interface ATSK SC LK SSTP M IR R D FC T FO K M IR R D FC T FO K SER VO D SP FO C U S SER VO TR AC KIN G SER VO SLED SER VO PW M G EN ER ATO R FO C U S PW M G EN ER ATO R TR AC KIN G PW M G EN ER ATO R SLED PW M G EN ER ATO R FFD R FR D R TFD R TR D R SFD R SR D R R FD C C E TE SE FE VC IG EN O PAm p Analog SW A/D C onverter C O U T XR AS LO C K XW E XC AS XO E XW R E XR D E Selecter D igital O U T M em ory C ontroller, Bass Boost Block XTSL Servo Auto Sequencer XSO E SYSM LR M U LR C KI BC KI PC M D I LPF AO U T1 AIN 1 LO U T1 LPF AO U T2 AIN 2 LO U T2 D AC Shock-Proof M em ory C ontroller + C om pression/ Expansion Block Diagram

– 3 – CXD3027R Pin Configuration 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 301 70 69 68 67 63646566 61627172 100 101 102 103 104 105 106 107 108 737481828384 7576777888 87 86 85 79808990 111 109 110 112 113 114 115 116 117 118 119 120 BCK PCM DI V DD2 W FCK C2PO GFS XUGF W DCK V SS2 XTSL AV DD3 ASYO ASYI BIAS CLTV PCO FILI FILO VCTL VPCO VC FEDOUT XPCK AV SS3 SE A9 A8 A7 A4 XW RE XRDE XEM P XW IH XQOK LRM U SQSO SQCK SCSY SCOR V SS0 SBSO EXCK XRST SYSM DATA XLAT CLOK SENS SCLK XSOE R4MA6 A5 DV SS ATSK M D P C 176 VD D 1 TEST3 TEST2 TEST1 LO C K FO K D FC T M IR R C O U T VD D 0 AVD D 0 TES1 TEST VSS1 FR D R FFD R TR D R TFD R SR D R SFD R SSTP M D S R FD C AVSS0 IG EN PW M I C E TE RFAC LRCKI LRCK PCM D D VD D A10 A11 XR AS XW E D 0 D 3 D 2 XC AS XO E AVD D 1 LO U T1 AIN 1 AO U T1 AVSS1 AVSS2 AO U T2 AIN 2 LO U T2 AVD D 2 XTAI XTAO XVSS D 1 XVD D BC KI

– 4 – CXD3027R Pin Description Pin No. O O O O O O I I O O I O O I I O O I I I I I I O I I I/O O 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 4M-bit/16M-bit DRAM address bus 9. 4M-bit/16M-bit DRAM address bus 8. 4M-bit/16M-bit DRAM address bus 7. DRAM interface GND 4M-bit/16M-bit DRAM address bus 6. 4M-bit/16M-bit DRAM address bus 5. 4M-bit/16M-bit DRAM address bus 4. DRAM write enable signal. DRAM readout enable signal. DRAM readout prohibited signal. DRAM write prohibited signal. Subcode-Q OK input. Lch, Rch "0" detection flag (AND output) Subcode-Q 80-bit, PCM peak and level data output. CD TEXT data output, DRAM data output. SQSO readout clock input. GRSCOR resynchronization input. High during track jump. Outputs a high signal when either subcode sync S0 or S1 is detected. Digital GND. Subcode P to W serial output. SBSO readout clock input. System reset. Reset when low. Mute input. Muted when high. Serial data input from CPU. Latch input from CPU. Serial data is latched at the falling edge. Serial data transfer clock input from CPU. SQSO or SENS readout clock is input by switching with the command. SENS output to CPU. SQSO data is output by switching with the command. SENS serial data readout clock input. CPU serial data output enable signal. Anti-shock I/O. Microcomputer clock output. C4M is output by switching with the command. Digital power supply. DV SS XWRE XRDE XEMP XWIH XQOK LRMU SQSO SQCK SCSY SCOR V SS 0 SBSO EXCK XRST SYSM DATA XLAT CLOK SENS SCLK XSOE ATSK R4M V DD 0 Symbol I/O Description

– 5 – CXD3027R Pin No. I/O I/O I/O I/O I I/O O O O O O O I O O O O O O I I I I I I I I I O I 1, 0 1, 0 1, 0 1, 0 1, 0 1, Z, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, Z, 0 Track count signal I/O. Mirror signal I/O. Defect signal I/O. Focus OK signal I/O. Spindle motor external control input. GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low. Or input when LKIN = 1. Test pin. Test pin. Test pin. Digital power supply. 176.4kHz output. Spindle motor servo control output. Spindle motor servo control output. Disc innermost track detection signal input. Sled drive output. Sled drive output. Tracking drive output. Tracking drive output. Focus drive output. Focus drive output. Digital GND. Test pin. Normally, GND. Test pin. Normally, GND. Analog power supply. Operational amplifier constant current input. Analog GND. RF signal input. Center servo analog input or E input. Tracking error signal input or F input. Sled error signal input or B input. Focus error signal input or A output. Center voltage input. Wide-band EFM PLL charge pump output. Wide-band EFM PLL VCO2 control voltage input. COUT MIRR DFCT FOK PWMI LOCK TEST1 TEST2 TEST3 V DD 1 C176 MDP MDS SSTP SFDR SRDR TFDR TRDR FFDR FRDR V SS 1 TEST TES1 AV DD 0 IGEN AV SS 0 RFDC CE TE SE FE VC VPCO VCTL Symbol I/O Description

– 6 – CXD3027R Pin No. O I O I I I I O I O O O O O O O O I O I O I I O Analog 1, Z, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 Master PLL filter output (slave = digital PLL). Master PLL filter input. Master PLL charge pump output. Multiplier VCO1 control voltage input. Analog GND. EFM signal input. Asymmetry circuit constant current input. Asymmetry comparator voltage input. EFM full-swing output (low = V SS , high = VDD ). Analog power supply. Crystal selection input. Low when the crystal is 16.9344MHz; high when the crystal is 33.8688MHz. Digital GND. Word clock output f = 2Fs. GRSCOR is output by switching with the command. XUGF output. MNT0, RFCK or SOUT is output by switching with the command. XPCK output. MNT1 or SOCK is output by switching with the command. GFS output. MNT2, XROF or XOLT is output by switching with the command. C2PO output. MNT3 or GTOP is output by switching with the command. WFCK output. Digital power supply. Digital Out output. D/A interface. LR clock output f = Fs. D/A interface. LR clock input. D/A interface. Serial data output. (two's complement, MSB first) D/A interface. Serial data input. (two's complement, MSB first) D/A interface. Bit clock output. D/A interface. Bit clock input. Master clock power supply. Crystal oscillation circuit input. The master clock is externally input from this pin. Crystal oscillation circuit output. FILO FILI PCO CLTV AV SS 3 RFAC BIAS ASYI ASYO AV DD 3 XTSL V SS 2 WDCK XUGF XPCK GFS C2PO WFCK V DD 2 DOUT LRCK LRCKI PCMD PDMDI BCK BCKI XV DD XTAI XTAO Symbol I/O Description

– 7 – CXD3027R Pin No. 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 O I O O I O O O O O O O O O I/O I/O I/O I/O O O 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 Master clock GND. Analog power supply. Lch LINE output. Lch operational amplifier input. Lch analog output. Analog GND. Analog GND. Rch analog output. Rch operational amplifier input. Rch LINE output. Analog power supply. 4M-bit/16M-bit DRAM address bus 3. 4M-bit/16M-bit DRAM address bus 2. 4M-bit/16M-bit DRAM address bus 1. 4M-bit/16M-bit DRAM address bus 0. DRAM interface power supply. 16M DRAM address bus 10. 16M DRAM address bus 11. DRAM row address strobe signal. DRAM data input enable signal. DRAM data bus 1. DRAM data bus 0. DRAM data bus 3. DRAM data bus 2. DRAM column address strobe signal. DRAM data output enable signal. XV SS AV DD 1 LOUT1 AIN1 AOUT1 AV SS 1 AV SS 2 AOUT2 AIN2 LOUT2 AV DD 2 DV DD A10 A11 XRAS XWE XCAS XOE Symbol I/O Description Notes) •PCMD is a MSB first, two's complement output.

GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)
XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before sync protection.
XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point coincide.
The GFS signal goes high when the frame sync and the insertion protection timing match.
RFCK is derived from the crystal accuracy, and has a cycle of 136µs.
C2PO represents the data error status.
XROF is generated when the 32K RAM exceeds the ±28F jitter margin.
C4M is a 4.2336MHz output that changes in CAV-W mode and variable pitch mode.
FSTO is the 2/3 frequency-division output of the XTAI pin.
SOUT is the serial data output inside the servo block.
SOCK is the serial data readout clock output inside the servo block.
XOLT is the serial data latch output inside the servo block.

– 8 – CXD3027R Monitor Pin Output Combinations Command bit Output data SRO1 MTSL1 MTSL0 XUGF XPCK GFS C2PO MNT0 MNT1 MNT2 MNT3 RFCK XPCK XROF GTOP C4M FSTO GFS C2PO SOUT SOCK XOLT C2PO

– 9 – CXD3027R

Electrical Characteristics

DC Characteristics (VDD = AVDD = 3.3 ± 0.3V, VSS = AVSS = 0V, Topr = –20 to +75°C) Item Input voltage (1) Input voltage (2) Input voltage (3) Output voltage (1) Output voltage (2) *1, *2, *3, *4, *12 *6, *7 *2, *4, *8, *9, *11, *12 Input leak current (1) Input leak current (2) Tri-state output leak current *3, *4, *5, *10 Schmitt input Analog input IOH = –4mA IOL = 4mA IOH = –0.28mA IOL = 0.36mA VIN = 0 to VDD VIN = 0.25VDD to 0.75VDD VO = 0 to 3.6V High level input voltage Low level input voltage High level input voltage Low level input voltage Input voltage High level output voltage Low level output voltage High level output voltage Low level output voltage VIH (1) VIL(1) VIH (2) VIL (2) VIN (3) VO H (1) VO L (1) VO H (2) VO L(2) ILI(1) ILI(2) ILO 0.7VDD 0.8VDD Vss VDD – 0.4 VDD – 0.5 –10 –40 0.2VDD 0.2VDD VDD VDD 0.4 VDD 0.4 V V V V V V V V V µA µA µA Conditions Min. Typ. Max. Unit Applicable pins Applicable pins

1 TEST, TES1

*2 COUT, MIRR, DFCT, FOK, LOCK *3 XQOK, SCSY, SYSM, DATA, PCMDI, XWRE, XSOE, XRDE, XTSL, SSTP *4 ATSK, PWMI, SSTP *5 SQCK, EXCK, XRST, CLOK, SCLK, BCKI, LRCKI, XLAT *6 VCTL, FILI, CLTV, ASYI, IGEN, BIAS *7 CE, TE, SE, FE, VC *8 XEMP, XWIH, SQSO, SBSO, WFCK, XUGF, XPCK, GFS, C2PO, SCOR, WDCK, SFDR, SRDR, TFDR, TRDR, FFDR, FRDR, ASYO, DOUT, LRCK, PCMD, BCK, R4M, C176 *9 SENS, MDP, VPCO, PCO, MDS *10 FILO *11 A0, A11, XRAS, XWE, XCAS, XOE *12 D0 to D3

– 10 – CXD3027R 2. AC Characteristics (1) XTAI pin (a) When using self-excited oscillation (Topr = –20 to +75°C, VDD = AVDD = 3.3 ± 0.3V) (b) When inputting pulses to XTAI pin (Topr = –20 to +75°C, VDD = AVDD = 3.3 ± 0.3V) (c) When inputting sine waves to XTAI pin via a capacitor (Topr = –20 to +75°C, VDD = AVDD = 3.3 ± 0.3V) Oscillation frequency fMAX 7 34 MHz Item Symbol Min. Typ. Max. Unit High level pulse width tWHX 13 500 ns Low level pulse width tWLX 13 500 ns Pulse cycle tCX 26 1000 ns Input high levelVIHX 0.7VDD V Input low level VILX 0.2VDD V Rise time, fall time tR , tF 10 ns Item Symbol Min. Typ. Max. Unit Input amplitudeVI 0.5VDD VDD + 0.3 Vp-p Item Symbol Min. Typ. Max. Unit tR tF tW H X tW LX tC X VILX VIH X × 0.1 VIH X × 0.9 VIH X XTAI VD D /2

– 11 – CXD3027R (2) CLOK, DATA, XLAT, SQCK and EXCK pins (VDD = AVDD = 3.3 ± 0.3V, VSS = AVSS = 0V, Topr = –20 to +75°C) Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width EXCK SQCK frequency EXCK SQCK pulse width COUT frequency (during input)* COUT pulse width (during input)* f CK tWCK tSU tH tD tWL fT tWT fT tWT 750 300 300 300 750 750 7.5 0.65 0.65 MHz ns ns ns ns ns MHz ns kHz µs Item Symbol Min. Typ. Max. Unit tW C K tW C K 1/fC K tHtSU tW LtD 1/fT tW T tW T tHtSU C LO K D ATA XLAT EXC K SQ C K C O U T SBSO SQ SO * Only when $44 and $45 are executed.

– 12 – CXD3027R (3) SCLK pin SCLK frequency SCLK pulse width Delay time f SCLK tSPW tDLS 31.3

16 MHz

µs Item Symbol Min. Typ. Max. Unit tSPWtD LS 1/fSC LK M SB LSB... ... XLAT SC LK Serial R ead O ut D ata (SEN S) (4) COUT, MIRR and DFCT pins Operating frequency(VDD = AVDD = 3.3 ± 0.3V, VSS = AVSS = 0V, Topr = –20 to +75°C) COUT maximum operating frequency MIRR maximum operating frequency DFCT maximum operating frequency fCOUT fMIRR fDFCTH kHz kHz kHz Signal Symbol Min. Typ. Max. Unit Conditions *1 When using a high-speed traverse TZC. When the RF signal continuously satisfies the following conditions during the above traverse.

A = 0.11VDD to 0.23VDD
≤ 25% *3 During complete RF signal omission. When settings related to DFCT signal generation are Typ. A B B A + B

Fs = 44.1kHz in all cases. The total harmonic distortion and signal-to-noise ratio measurement circuits are shown below. – 13 – CXD3027R 1-bit DAC and LPF Block Analog Characteristics (VDD = AVDD = 3.3V, VSS = AVSS = 0V, Ta = 25°C) Item Total harmonic distortion Signal-to-noise ratio Symbol THD S/N Conditions 1kHz, 0dB data Crystal 1kHz, 0dB data, AMUT ON (Using A-weighting filter) 384Fs 768Fs 384Fs 768Fs 0.0120 0.0120 100 100 0.0140 0.0140 Min. Typ. Max. Unit dB Audio Analyzer SH IBASO KU (AM 51A) 100k 22µF 330pF 27k 27k 27k 68pF AO U T1 (2) AIN 1 (2) LO U T1 (2) Audio AnalyzerC XD 3027R R ch A Lch B D ATA R F TEST D ISC 768Fs/384Fs (VDD = AVDD = 3.3V, VSS = AVSS = 0V, Topr = –20 to +75°C) VOUT R L Vrms kΩ Symbol Min. Max. 0.64 Typ. Applicable pinsUnit Output voltage Load resistance Item * Measurement is conducted for the above circuit diagrams with the sine wave output of 1kHz and 0dB. Applicable pins *1 LOUT1, LOUT2 Block diagram of analog characteristics measurement LPF external circuit diagram

– 15 – CXD3027R [1] CPU Interface §1-1. CPU Interface Timing

CPU interface This interface uses DATA, CLOK and XLAT to set the modes. The interface timing chart is shown below.
The internal registers are initialized by a reset when XRST = 0. §1-2. CPU Interface Command Table Total bit length for each register Register 0 to 2 4 to 6 A B C D E 8 bits 8 to 24 bits 16 bits 20 bits 32 bits 32 bits 28 bits 28 bits 28 bits 28 bits 20 bits Total bit length 750ns or m ore D 18 D 19 D 20 D 21 D 22 D 23 750ns or m ore Valid C LO K D ATA XLAT R egisters D 0 D 1

– 16 – CXD3027R FOCUS SERVO ON (FOCUS GAIN NORMAL) FOCUS SERVO ON (FOCUS GAIN DOWN) FOCUS SERVO OFF, 0V OUT FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT FOCUS SEARCH VOLTAGE DOWN FOCUS SEACH VOLTAGE UP ANTI SHOCK ON ANTI SHOCK OFF BRAKE ON BRAKE OFF TRACKING GAIN NORMAL TRACKING GAIN UP TRACKING GAIN UP FILTER SELECT 1 TRACKING GAIN UP FILTER SELECT 2 0 0 0 0 0 0 0 1 FOCUS CONTROL TRACKING CONTROL Regis- ter Command Address D23 to D20 Data 1 D19 D18 D17 D16 Data 2 D15 D14 D13 D12 Data 3 D11 D10 D9 D8 Data 4 D7 D6 D5 D4 Data 5 D3 D2 D1 D0 Command Table ($0X to 1X) —: don’t care

– 17 – CXD3027R TRACKING SERVO OFF TRACKING SERVO ON FORWARD TRACK JUMP REVERSE TRACK JUMP SLED SERVO OFF SLED SERVO ON FORWARD SLED MOVE REVERSE SLED MOVE SLED KICK LEVEL (±1 · basic value) (default) SLED KICK LEVEL (±2 · basic value) SLED KICK LEVEL (±3 · basic value) SLED KICK LEVEL (±4 · basic value) 0 0 1 0 0 0 1 1 TRACKING MODE SELECT Regis- ter Command Address D23 to D20 Regis- ter Command Address D23 to D20 Data 1 D19 D18 D17 D16 Data 1 D19 D18 D17 D16 Data 2 D15 D14 D13 D12 Data 2 D15 D14 D13 D12 Data 3 D11 D10 D9 D8 Data 4 D7 D6 D5 D4 Data 5 D3 D2 D1 D0 Data 3 D11 D10 D9 D8 Data 4 D7 D6 D5 D4 Data 5 D3 D2 D1 D0 —: don’t care Command Table ($2X to 3X)

– 18 – CXD3027R KRAM DATA (K00) SLED INPUT GAIN KRAM DATA (K01) SLED LOW BOOST FILTER A-H KRAM DATA (K02) SLED LOW BOOST FILTER A-L KRAM DATA (K03) SLED LOW BOOST FILTER B-H KRAM DATA (K04) SLED LOW BOOST FILTER B-L KRAM DATA (K05) SLED OUTPUT GAIN KRAM DATA (K06) FOCUS INPUT GAIN KRAM DATA (K07) SLED AUTO GAIN KRAM DATA (K08) FOCUS HIGH CUT FILTER A KRAM DATA (K09) FOCUS HIGH CUT FILTER B KRAM DATA (K0A) FOCUS LOW BOOST FILTER A-H KRAM DATA (K0B) FOCUS LOW BOOST FILTER A-L KRAM DATA (K0C) FOCUS LOW BOOST FILTER B-H KRAM DATA (K0D) FOCUS LOW BOOST FILTER B-L KRAM DATA (K0E) FOCUS PHASE COMPENSATE FILTER A KRAM DATA (K0F) FOCUS DEFECT HOLD GAIN KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 3 0 0 1 1 0 1 0 0 0 0 0 0SELECT Regis- ter Command Address 1 D23 to D20 Address 2 D19 to D16 Address 3 D15 to D12 Address 4 D11 D10 D9 D8 Data 1 D7 D6 D5 D4 Data 2 D3 D2 D1 D0 Command Table ($340X)

– 19 – CXD3027R KRAM DATA (K10) FOCUS PHASE COMPENSATE FILTER B KRAM DATA (K11) FOCUS OUTPUT GAIN KRAM DATA (K12) ANTI SHOCK INPUT GAIN KRAM DATA (K13) FOCUS AUTO GAIN KRAM DATA (K14) HPTZC / AUTO GAIN HIGH PASS FILTER A KRAM DATA (K15) HPTZC / AUTO GAIN HIGH PASS FILTER B KRAM DATA (K16) ANTI SHOCK HIGH PASS FILTER A KRAM DATA (K17) HPTZC / AUTO GAIN LOW PASS FILTER B KRAM DATA (K18) FIX KRAM DATA (K19) TRACKING INPUT GAIN KRAM DATA (K1A) TRACKING HIGH CUT FILTER A KRAM DATA (K1B) TRACKING HIGH CUT FILTER B KRAM DATA (K1C) TRACKING LOW BOOST FILTER A-H KRAM DATA (K1D) TRACKING LOW BOOST FILTER A-L KRAM DATA (K1E) TRACKING LOW BOOST FILTER B-H KRAM DATA (K1F) TRACKING LOW BOOST FILTER B-L KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 3 0 0 1 1 0 1 0 0 0 0 0 1SELECT Regis- ter Command Address 1 D23 to D20 Address 2 D19 to D16 Address 3 D15 to D12 Address 4 D11 D10 D9 D8 Data 1 D7 D6 D5 D4 Data 2 D3 D2 D1 D0 Command Table ($341X)

– 20 – CXD3027R KRAM DATA (K20) TRACKING PHASE COMPENSATE FILTER A KRAM DATA (K21) TRACKING PHASE COMPENSATE FILTER B KRAM DATA (K22) TRACKING OUTPUT GAIN KRAM DATA (K23) TRACKING AUTO GAIN KRAM DATA (K24) FOCUS GAIN DOWN HIGH CUT FILTER A KRAM DATA (K25) FOCUS GAIN DOWN HIGH CUT FILTER B KRAM DATA (K26) FOCUS GAIN DOWN LOW BOOST FILTER A-H KRAM DATA (K27) FOCUS GAIN DOWN LOW BOOST FILTER A-L KRAM DATA (K28) FOCUS GAIN DOWN LOW BOOST FILTER B-H KRAM DATA (K29) FOCUS GAIN DOWN LOW BOOST FILTER B-L KRAM DATA (K2A) FOCUS GAIN DOWN PHASE COMPENSATE FILTER A KRAM DATA (K2B) FOCUS GAIN DOWN DEFECT HOLD GAIN KRAM DATA (K2C) FOCUS GAIN DOWN PHASE COMPENSATE FILTER B KRAM DATA (K2D) FOCUS GAIN DOWN OUTPUT GAIN KRAM DATA (K2E) NOT USED KRAM DATA (K2F) NOT USED KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 3 0 0 1 1 0 1 0 0 0 0 1 0SELECT Regis- ter Command Address 1 D23 to D20 Address 2 D19 to D16 Address 3 D15 to D12 Address 4 D11 D10 D9 D8 Data 1 D7 D6 D5 D4 Data 2 D3 D2 D1 D0 Command Table ($342X)

– 21 – CXD3027R KRAM DATA (K30) SLED INPUT GAIN (when TGup2 is accessed with SFSK = 1) KRAM DATA (K31) ANTI SHOCK LOW PASS FILTER B KRAM DATA (K32) NOT USED KRAM DATA (K33) ANTI SHOCK HIGH PASS FILTER B-H KRAM DATA (K34) ANTI SHOCK HIGH PASS FILTER B-L KRAM DATA (K35) ANTI SHOCK FILTER COMPARATE GAIN KRAM DATA (K36) TRACKING GAIN UP2 HIGH CUT FILTER A KRAM DATA (K37) TRACKING GAIN UP2 HIGH CUT FILTER B KRAM DATA (K38) TRACKING GAIN UP2 LOW BOOST FILTER A-H KRAM DATA (K39) TRACKING GAIN UP2 LOW BOOST FILTER A-L KRAM DATA (K3A) TRACKING GAIN UP2 LOW BOOST FILTER B-H KRAM DATA (K3B) TRACKING GAIN UP2 LOW BOOST FILTER B-L KRAM DATA (K3C) TRACKING GAIN UP PHASE COMPENSATE FILTER A KRAM DATA (K3D) TRACKING GAIN UP PHASE COMPENSATE FILTER B KRAM DATA (K3E) TRACKING GAIN UP OUTPUT GAIN KRAM DATA (K3F) NOT USED KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 3 0 0 1 1 0 1 0 0 0 0 1 1SELECT Regis- ter Command Address 1 D23 to D20 Address 2 D19 to D16 Address 3 D15 to D12 Address 4 D11 D10 D9 D8 Data 1 D7 D6 D5 D4 Data 2 D3 D2 D1 D0 Command Table ($343X)

– 22 – CXD3027R KRAM DATA (K40) TRACKING HOLD FILTER INPUT GAIN KRAM DATA (K41) TRACKING HOLD FILTER A-H KRAM DATA (K42) TRACKING HOLD FILTER A-L KRAM DATA (K43) TRACKING HOLD FILTER B-H KRAM DATA (K44) TRACKING HOLD FILTER B-L KRAM DATA (K45) TRACKING HOLD FILTER OUTPUT GAIN KRAM DATA (K46) TRACKING HOLD INPUT GAIN (when TGup2 is accessed with THSK = 1) KRAM DATA (K47) NOT USED KRAM DATA (K48) FOCUS HOLD FILTER INPUT GAIN KRAM DATA (K49) FOCUS HOLD FILTER A-H KRAM DATA (K4A) FOCUS HOLD FILTER A-L KRAM DATA (K4B) FOCUS HOLD FILTER B-H KRAM DATA (K4C) FOCUS HOLD FILTER B-L KRAM DATA (K4D) FOCUS HOLD FILTER OUTPUT GAIN KRAM DATA (K4E) NOT USED KRAM DATA (K4F) NOT USED KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 3 0 0 1 1 0 1 0 0 0 1 0 0SELECT Regis- ter Command Address 1 D23 to D20 Address 2 D19 to D16 Address 3 D15 to D12 Address 4 D11 D10 D9 D8 Data 1 D7 D6 D5 D4 Data 2 D3 D2 D1 D0 Command Table ($344X)

– 23 – CXD3027R PGFS, PFOK, RFAC DOUT Booster Surf Brake Booster DFCT FCS Bias Limit FCS Bias Data Traverse Center Data PGFS1 A/D SEL SFBK1 THBON IDFS3 PGFS0 COPY EN SFBK2 FHBON IDFS2 PFOK1 EMPH D TLB10N IDFS1 FBL9 FB9 TV9 PFOK0 CAT FLB1ON IDFS0 FBL8 FB8 TV8 DOUT EN1 TLB2ON FBL7 FB7 TV7 DOUT DMUT FBL6 FB6 TV6 DOUT WOD HBST1 IDFT1 FBL5 FB5 TV5 MRS WIN EN HBST0 IDFT0 FBL4 FB4 TV4 MRT1 DOUT EN2 LB1S1 FBL3 FB3 TV3 MRT0 LB1S0 FBL2 FB2 TV2 LB2S1 FBL1 FB1 TV1 LB2S0 INVRFDC TV0 SELECT Regis- ter Command Address 1 Address 2 D23 to D20 Address 3 D15 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D1 D0D3 D2 Data 3Data 2Data 1Address 3 D14 D13 D12 Data 1 D11 D10 D9 D8 Data 2 D7 D6 D5 D4 Data 3 D3 D2 D1 D0 Command Table ($348X to 3FX) 0 0 1 1 D19 to D16 0 1 0 0

– 24 – CXD3027R FCS search, AGF TRK jump, AGT FZC, AGC, SLD move DC measure, cancel Serial data read out FCS Bias, Gain, Surf jump/brake Mirr, DFCT, FOK TZC, COUT, Bottom, MIRR SLD filter Filter Clock, others FT1 FZSH VCLM DAC SFO2 COSS SFID F1NM FT0 DTZC FZSL VCLC SD6 FBON SFO1 COTS SFSK F1DM AGG4 FS5 TJ5 SM5 FLM SD5 FBSS SDF2 CETZ THID F3NM XT4D FS4 TJ4 SM4 FLC0 SD4 FBUP SDF1 CETF THSK F3UM XT2D FS3 TJ3 SM3 RFLM SD3 FBV1 MAX2 COT2 ABEF TINM FS2 TJ2 SM2 RFLC SD2 FBV0 MAX1 COT1 TLD2 TIUM DRR2 FS1 TJ1 SM1 AGF SD1 FI FZC SFOX MOT2 TLD1 T3NM DRR1 FS0 TJ0 SM0 AGT SD0 TJD0 BTF TLD0 T3DM DRR0 FTZ SFJP AGS DFSW FPS1 D2V2 BTS1 DFIS FG6 TG6 AGJ LKSW FPS0 D2V1 BTS0 TLCD ASFG FG5 TG5 AGGF TBLM TPS1 D1V2 MRC1 FTQ FG4 TG4 AGGT TCLM TPS0 D1V1 MRC0 LKIN LPAS FG3 TG3 AGV1 FLC1 SVDA RINT COIN SRO1 FG2 TG2 AGV2 TLC2 SJHD MDFI FG1 TG1 AGHS TLC1 INBK MIRI AGHF FG0 TG0 AGHT TLC0 MTI0 XT1D ASOT SELECT Regis- ter Command Address 1 Address 2 D23 to D20 D19 D18 D17 D16 Data 1 D15 D14 D13 D12 Data 2 D11 D10 D9 D8 Data 3 D7 D6 D5 D4 Data 4 D3 D2 D1 D0 0 0 1 1 Command Table ($34FX to 3FX) cont. Address 2 D19 1 1 1 1 SYG3 SYG2 SYG1 SYG1 FI FZB3 FI FZB2 FI FZB1 FI FZB0 FI FZA3 FI FZA2 FI FZA1 FI FZA0 System GAIN D18 D17 D16 Address 3 D15 D14 D13 D12 Data 1 D11 D10 D9 D8 Data 2 D7 D6 D5 D4 Data 3 D3 D2 D1 D0

– 25 – CXD3027R Auto sequence Blind (A, E), Brake (B), Overflow (C, G) Sled KICK, BRAKE (D), KICK (F) Auto sequence (N) track jump count setting MODE specification Function specification AS3 TR3 SD3 32768 CD- ROM AS2 TR2 SD2 16384 DOUT Mute DSPB AS1 TR1 SD1 8192 DOUT Mute-F ASEQ AS0 TR0 SD0 4096 WSEL MT3 KF3 2048 VCO SEL1 BiliGL MAIN MT2 KF2 1024 ASHS BiliGL SUB MT1 KF1 512 SOCT0 FLFC MT0 KF0 256 VCO SEL2 LSSL 128 KSL3 KSL2 KSL1 SYCOF KSL0 VCO1 CS1 VCO1 CS0 VCO2 CS Regis- ter Command Address D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 Data 1 Data 2 Data 3 Data 4 Command Table ($4X to EX) —: don’t care

– 26 – CXD3027R Audio CTRL Signal select Bass boost Shock-proof memory setting Shock-proof memory control DOUT subcode-Q setting DRAM I/F Compression setting EFM playability enhancement settin g Sync expansion specification Sleep setting Variable pitch setting Spindle servo setting 1 0 1 0 Mute ATT PCT1 RSL1 SL XQOK XQOK SubQA3 ADPON ARDTEN AVW ADCPS VARI ON SYG3 EA PCT2 RSL0 SL XWRE XWRE SubQA2 BITSL1 DSP SLEEP VARI USE SYG2 EA PWDN BBON1 COMP ON GTOP CHECK XRDE SubQA1 BITSL0 SFP5 DSSP SLEEP SYG1 EA SOC2 ZMUTA ZDPL BBON0 NOLIM WDCK XSOEO SubQA0 SFP4 ASYM SLEEP SYG0 EA DTSL1 SMUT XWOC HBON1 SPSL COM XSOEO2 DADR19 SFP3 ESP SLEEP MDP OUTSL1 DTSL0 AD10 DAC EMPH HBON0 READ2 DRWR DADR18 SFP2 LPF SLEEP MDP OUTSL0 MCSL1 AD9 HiCut FILTER BBSL1 REFSEL DRADR DADR17 SFP1 DSUB SLEEP LPWR2 MCSL0 AD8 BST CL BBSL0 REFON SDTO OUT DADR16 SFP0 AD7 HBSL1 SubQD7 DRD15 DADR15 MDS CTL SDSL2 AD6 HBSL0 MSL2 SubQD6 DRD14 DADR14 GRSEL MDP UP SDSL1 AD5 OBIT1 BBST Vdwn1 MSL1 SubQD5 DRD13 DADR13 SDSL0 AD4 OBIT0 BBST Vdwn0 MSL0 SubQD4 DRD12 DADR12 MDP CTL4 A Regis- ter Command Address D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 Data 1 Data 2 Data 3 Data 4 Command Table ($4X to EX) cont.

– 27 – CXD3027R 32768 Gain MDP1 CM3 Traverse monitor counter setting Spindle servo coefficient setting CLV CTRL SPD mode 16384 Gain MDP0 TB CM2 8192 Gain MDS1 TP CM1 4096 Gain MDS0 CLVS Gain CM0 2048 Gain DCLV1 VP7 EPWM 1024 Gain DCLV0 VP6 SPD 512 PCC1 VP5 ICAP 256 PCC0 VP4 SFSL 128 SFP3 VP3 VC2C SFP2 VP2 HIFC SFP1 VP1 LPWR SFP0 VP0 VPON SRP3 VP CTL1 Gain CAV1 SRP2 VP CTL0 Gain CAV0 SPR1 SRP0 INV VPCO B C D E Regis- ter Command Address D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 Data 1 Data 2 Data 3 Data 4 Command Table ($4X to EX) cont.

– 28 – CXD3027R —: don’t care MODE specification Function specification AUDIO CTRL Signal select Bass boost DOUT subcode-Q setting DRAM I/F EFM playability enhancement setting Spindle servo setting Traverse monitor counter setting Spindle servo coefficient setting CLV CTRL A B C D 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 0 0 0 * * 0 1 0 0 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 1 1 1 1 1 0 0 0 0 0 1 * * 1 0 * * 1 1 * * * * * * 1 1 1 0 1 1 1 1 0 0 0 0 ERC4 EN XSOE AD3 BBST Vup1 SubQD3 DRD11 DADR11 MDP CTL3 EDC7 SCOR SEL CKOUT SL2 AD2 BBST Vup0 SubQD2 DRD10 DADR10 MDP CTL2 EDC6 SCSY CKOUT SL1 AD1 BBST Uth SubQD1 DRD9 DADR9 MDP CTL1 MTSL1 EDC5 SOCT1 SLD BBIN AD0 BBST Lth PDM INV SubQD0 DRD8 DADR8 MDP CTL0 MTSL0 EDC4 TXON DRD7 DADR7 ASYE EDC3 TXOUT DRD6 DADR6 MD2 EDC2 OUTL1 DRD5 DADR5 EDC1 OUTL0 DRD4 DADR4 EDC0 DIV4 DRD3 DADR3 DRD2 DADR2 OUTL2 DRD1 DADR1 DRD0 DADR0 Regis- ter Command Address Data 1 Data 2 Data 3 Data 4 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 Data 5 Data 6 Data 7 Command Table ($4X to EX) cont.

– 29 – CXD3027R FOCUS SERVO OFF, 0V OUT TRACKING GAIN UP FILTER SELECT 1 TRACKING SERVO OFF SLED SERVO OFF SLED KICK LEVEL (±1 · basic value) (default) KRAM DATA ($3400XX to $344fXX) 0 0 0 0 0 0 0 1 0 0 1 0 FOCUS CONTROL TRACKING CONTROL TRACKING MODE Regis- ter Command Address D23 to D20 Data 1 D19 D18 D17 D16 Data 2 D15 D14 D13 D12 Data 3 D11 D10 D9 D8 Data 4 D7 D6 D5 D4 Data 5 D3 D2 D1 D0 Regis- ter Command

3 SELECT

0 0 1 1 0 1 0 0 0 See "Coefficient ROM Preset Values Table". Data 1 D19 D18 D17 D16 Data 2 D15 D14 D13 D12 Data 3 D11 D10 D9 D8 Data 4 D7 D6 D5 D4 Data 5 D3 D2 D0 D0 Address 1 D23 to D20 D19 D18 D17 D16 Address 2 D15 D14 D13 D12 Address 3 D11 D10 D9 D8 Data 1 D7 D6 D5 D4 Data 2 D3 D2 D0 D0 §1-3. CPU Command Presets Command Preset Table ($0X to 34X) —: don’t care

– 30 – CXD3027R Command Preset Table ($348X to 34FX) PGFS, PFOK, RFAC CAV control DOUT Booster Surf Brake Booster Servo DAC output DFCT FCS Bias Limit FCS Bias Data Traverse Center Data SELECT Regis- ter Command Address 1 Address 2 D23 to D20 Address 3 D15 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D1 D0D3 D2 Data 3Data 2Data 1Address 3 D14 D13 D12 Data 1 D11 D10 D9 D8 Data 2 D7 D6 D5 D4 Data 3 D3 D2 D1 D0 0 0 1 1 D19 to D16 0 1 0 0 —: don’t care

– 31 – CXD3027R FCS search, AGF TRK jump, AGT FZC, AGC, SLD move DC measure, cancel Serial data read out FCS Bias, Gain, Surf jump/brake MIRR, DFCT, FOK TZC, COUT, Bottom, MIRR SLD filter Filter Clock, others System GAIN FOCUS SLED SLED SELECT Regis- ter Command Address 2Address 1 D23 to D20 D19 D18 D17 D16 Data 1 D15 D14 D13 D12 Data 2 D11 D10 D9 D8 Data 3 D7 D6 D5 D4 Data 4 D3 D2 D1 D0 Address 2 D19 1 1 1 1 D18 D17 D16 Address 3 D15 D14 D13 D12 Data 1 D11 D10 D9 D8 Data 2 D7 D6 D5 D4 Data 3 D3 D2 D1 D0 0 0 1 1 Command Preset Table ($35X to 3FX) cont.

– 32 – CXD3027R Auto sequence Blind (A, E), Brake (B), Overflow (C, G) Sled KICK, BRAKE (D), KICK (F) Auto sequence (N) track jump count setting MODE specification Function specification Regis- ter Command Address D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 Data 1 Data 2 Data 3 Data 4 Command Preset Table ($4X to EX) —: don’t care

– 33 – CXD3027R Audio CTRL Signal select Bass boost Shock-proof memory setting Shock-proof memory control DOUT subcode-Q setting DRAM I/F Compression setting EFM playability enhancement setting Sync expansion specification Sleep setting Variable pitch setting Spindle servo setting 1 0 1 0 A Regis- ter Command Address D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 Data 1 Data 2 Data 3 Data 4 Command Preset Table ($4X to EX) cont.

– 34 – CXD3027R Traverse monitor counter setting Spindle servo coefficient setting CLV CTRL SPD mode 1 1 0 1 1 1 1 0 B C D E Regis- ter Command Address D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 Data 1 Data 2 Data 3 Data 4 Command Preset Table ($4X to EX) cont.

– 35 – CXD3027R MODE specification Function specification AUDIO CTRL Signal select Bass boost DOUT subcode-Q setting DRAM I/F EFM playability enhancement setting Traverse monitor counter setting Spindle servo coefficient setting CLV CTRL A B C D 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 0 0 0 * * 0 1 0 0 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 1 0 0 0 0 0 1 * * 1 0 * * 1 1 * * * * * * 1 1 1 0 1 1 1 1 0 0 0 0 Regis- ter Command Address Data 1 Data 2 Data 3 Data 4 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 Data 5 Data 6 Data 7 Command Preset Table ($4X to EX) cont. —: don’t care

– 36 – CXD3027R <Coefficient ROM Preset Values Table (1)> ADDRESS K00 K01 K02 K03 K04 K05 K06 K07 K08 K09 K0A K0B K0C K0D K0E K0F SLED INPUT GAIN SLED LOW BOOST FILTER A-H SLED LOW BOOST FILTER A-L SLED LOW BOOST FILTER B-H SLED LOW BOOST FILTER B-L SLED OUTPUT GAIN FOCUS INPUT GAIN SLED AUTO GAIN FOCUS HIGH CUT FILTER A FOCUS HIGH CUT FILTER B FOCUS LOW BOOST FILTER A-H FOCUS LOW BOOST FILTER A-L FOCUS LOW BOOST FILTER B-H FOCUS LOW BOOST FILTER B-L FOCUS PHASE COMPENSATE FILTER A FOCUS DEFECT HOLD GAIN K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K1A K1B K1C K1D K1E K1F K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K2A K2B K2C K2D K2E K2F FOCUS PHASE COMPENSATE FILTER B FOCUS OUTPUT GAIN ANTI SHOCK INPUT GAIN FOCUS AUTO GAIN HPTZC / Auto Gain HIGH PASS FILTER A HPTZC / Auto Gain HIGH PASS FILTER B ANTI SHOCK HIGH PASS FILTER A HPTZC / Auto Gain LOW PASS FILTER B Fix* TRACKING INPUT GAIN TRACKING HIGH CUT FILTER A TRACKING HIGH CUT FILTER B TRACKING LOW BOOST FILTER A-H TRACKING LOW BOOST FILTER A-L TRACKING LOW BOOST FILTER B-H TRACKING LOW BOOST FILTER B-L TRACKING PHASE COMPENSATE FILTER A TRACKING PHASE COMPENSATE FILTER B TRACKING OUTPUT GAIN TRACKING AUTO GAIN FOCUS GAIN DOWN HIGH CUT FILTER A FOCUS GAIN DOWN HIGH CUT FILTER B FOCUS GAIN DOWN LOW BOOST FILTER A-H FOCUS GAIN DOWN LOW BOOST FILTER A-L FOCUS GAIN DOWN LOW BOOST FILTER B-H FOCUS GAIN DOWN LOW BOOST FILTER B-L FOCUS GAIN DOWN PHASE COMPENSATE FILTER A FOCUS GAIN DOWN DEFECT HOLD GAIN FOCUS GAIN DOWN PHASE COMPENSATE FILTER B FOCUS GAIN DOWN OUTPUT GAIN NOT USED NOT USED DATA CONTENTS * Fix indicates that normal preset values should be used.

– 37 – CXD3027R <Coefficient ROM Preset Values Table (2)> ADDRESS K30 K31 K32 K33 K34 K35 K36 K37 K38 K39 K3A K3B K3C K3D K3E K3F SLED INPUT GAIN (Only when TRK gain up2 is accessed with SFSK = 1.) ANTI SHOCK LOW PASS FILTER B NOT USED ANTI SHOCK HIGH PASS FILTER B-H ANTI SHOCK HIGH PASS FILTER B-L ANTI SHOCK FILTER COMPARATE GAIN TRACKING GAIN UP2 HIGH CUT FILTER A TRACKING GAIN UP2 HIGH CUT FILTER B TRACKING GAIN UP2 LOW BOOST FILTER A-H TRACKING GAIN UP2 LOW BOOST FILTER A-L TRACKING GAIN UP2 LOW BOOST FILTER B-H TRACKING GAIN UP2 LOW BOOST FILTER B-L TRACKING GAIN UP PHASE COMPENSATE FILTER A TRACKING GAIN UP PHASE COMPENSATE FILTER B TRACKING GAIN UP OUTPUT GAIN NOT USED K40 K41 K42 K43 K44 K45 K46 K47 K48 K49 K4A K4B K4C K4D K4E K4F TRACKING HOLD FILTER INPUT GAIN TRACKING HOLD FILTER A-H TRACKING HOLD FILTER A-L TRACKING HOLD FILTER B-H TRACKING HOLD FILTER B-L TRACKING HOLD FILTER OUTPUT GAIN TRACKING HOLD FILTER INPUT GAIN (Only when TRK gain up2 is accessed with THSK = 1.) NOT USED FOCUS HOLD FILTER INPUT GAIN FOCUS HOLD FILTER A-H FOCUS HOLD FILTER A-L FOCUS HOLD FILTER B-H FOCUS HOLD FILTER B-L FOCUS HOLD FILTER OUTPUT GAIN NOT USED NOT USED DATA CONTENTS

– 38 – CXD3027R §1-4. Description of SENS Signals SENS output Microcomputer serial register (latching not required) $0X $1X $2X $30 to 37 $38 $38 $3904 $3908 $390C $391C $391D $391F $3A $3B to 3F $4X $5X $6X $A0 to $A8 $AA to $AF $BX $CX $EX $7X, 8X, 9X, DX, FX Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z GFS COMP COUT OV64 Z FZC AS TZC SSTP AGOK * XAVEBSY * TE Avrg Reg. FE Avrg Reg. VC Avrg Reg. TRVSC Reg. FB Reg. RFDC Avrg Reg. FBIAS Count STOP SSTP XBUSY FOK GFS COMP COUT OV64 9 bits 9 bits 9 bits 9 bits 9 bits 8 bits ASEQ = 0 ASEQ = 1 Output data length * $38 outputs AGOK during AGT and AGF command settings, and XAVEBSY during AVRG measurement. SSTP is output in all other cases.

– 39 – CXD3027R Description of SENS Signals The SENS pin is high impedance. Low while the auto sequencer is in operation, high when operation terminates. Outputs the same signal as the FOK pin. High for "focus OK". High when the regenerated frame sync is obtained with the correct timing. Counts the number of tracks set with Reg.B. High when Reg.B is latched, low when COUT is counted for the initial Reg.B number. Counts the number of tracks set with Reg.B. High when Reg.B is latched, toggles each time COUT is counted for the Reg.B number. While $44 and $45 are being executed, toggles with each COUT 8-count instead of the Reg.B number. Low when the EFM signal is lengthened by 64 channel clock pulses or more after passing through the sync detection filter. Z XBUSY FOK GFS COMP COUT OV64 SENS output

– 40 – CXD3027R §1-5. Description of Commands The meaning of the data for each address on the XLAT pin side is explained below. $4X commands Register name Data 1 Command Data 2 MAX timer value Data 3 Timer range AS3 AS2 AS1 AS0 MT3 MT2 MT1 MT0 LSSL 0 0 0 Command Cancel Fine Search Focus-On

1 Track Jump

10 Track Jump

RXF = 0 Forward RXF = 1 Reverse

When the Focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted.
When the Track jump commands ($44, $45 and $48 to $4D) are canceled, $25 is sent and the auto sequence is interrupted.
To disable the MAX timer, set the MAX timer value to 0. $5X commands MAX timer value MT3 23.2ms 1.49s 11.6ms 0.74s 5.8ms 0.37s 2.9ms 0.18s MT2 MT1 MT0 LSSL 0 0 0 Timer range Timer TR3 TR2 TR1 TR0 Blind (A, E), Overflow (C, G) Brake (B) 0.18ms 0.36ms 0.09ms 0.18ms 0.045ms 0.09ms 0.022ms 0.045ms

– 41 – CXD3027R Command Data 1 Data 2 Data 3 Data 4 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20Auto sequence track jump count setting This command is used to set N when a 2N-track jump is executed, to set M when an M-track move is executed and to set the jump count when fine search is executed for auto sequencer.

The maximum track count is 65,535, but note that with a 2N-track jump the maximum track jump count depends on the mechanical limitations of the optical system.
When the track jump count is from 0 to 15, the COUT signal is counted for 2N-track jumps and M-track moves; when the count is 16 or over, the MIRR signal is counted. For fine search, the COUT signal is counted. $7X commands Auto sequence track jump count setting $6X commands Register name Data 1 KICK (D) Data 2 KICK (F) SD3 SD2 SD1 SD0 KF3 KF2 KF1 KF0 Timer SD3 SD2 SD1 SD0 When executing KICK (D) $44 or $45 When executing KICK (D) $4C or $4D 23.2ms 11.6ms 11.6ms 5.8ms 5.8ms 2.9ms 2.9ms 1.45ms Timer KF3 KF2 KF1 KF0 KICK (F) 0.72ms 0.36ms 0.18ms 0.09ms

– 42 – CXD3027R * See "Mute conditions" (1), (2) and (4) to (6) under $AX commands for other mute conditions. * When DTSL1 = 1, the Digital Out from the bass boost or shock-proof is selected. See the description of Digital Out. MD2 Other mute conditions* DOUT Mute DOUT Mute F DOUT output OFF 0dB –∞ dB DA output for 48-bit slot 0dB 0dB –∞ dB 0dB –∞ dB –∞ dB Command Data 1 MODE specification CD- ROM DOUT Mute DOUT Mute-F WSEL D3 D2 D1 D0 Data 2 VCO SEL1 ASHS SOCT0 VCO SEL2 D3 D2 D1 D0 $8X commands Command bit DOUT Mute = 1 DOUT Mute = 0 When Digital Out is on (MD2 pin = 1), DOUT output is muted. When Digital Out is on, DOUT output is not muted. Processing Command bit DOUT Mute F = 1 DOUT Mute F = 0 When Digital Out is on (MD2 pin = 1), DA output is muted. DA output mute is not affected when Digital Out is either on or off. Processing Command bit CDROM = 1 CDROM = 0 C2PO timing 1-3 1-3 CDROM mode; average value interpolation and pre-value hold are not performed. Audio mode; average value interpolation and pre-value hold are performed. Processing

– 43 – CXD3027R Command bit Processing VCOSEL1 = 0 VCOSEL1 = 1 Multiplier PLL VCO1 is set to normal speed. Multiplier PLL VCO1 is set to approximately twice the normal speed. Command bit KSL3 KSL2 Processing Output of multiplier PLL VCO1 selected by VCO CS0 is 1/1 frequency-divided. Output of multiplier PLL VCO1 selected by VCO CS0 is 1/2 frequency-divided. Output of multiplier PLL VCO1 selected by VCO CS0 is 1/4 frequency-divided. Output of multiplier PLL VCO1 selected by VCO CS0 is 1/8 frequency-divided. See above. Command Data 2 MODE specification VCO SEL1 ASHS SOCT0 VCO SEL2 D3 D2 D1 D0 Data 3 KSL3 KSL2 KSL1 KSL0 D3 D2 D1 D0 Command bit Sync protection window width WSEL = 1 WSEL = 0 ±26 channel clock ±6 channel clock Anti-rolling is enhanced. Sync window protection is enhanced. Application * In normal-speed playback, channel clock = 4.3218MHz. Command bit Function ASHS = 0 ASHS = 1 The command transfer rate from the auto sequencer to the DSSP block is set to normal speed. The command transfer rate from the auto sequencer to the DSSP block is set to half speed. * See "§4-8. CD-DSP Block Playback Speed" for settings. Command bit SOCT0 SOCT1 Processing Subcode-Q is output from the SQSO pin. Various signals are output from the SQSO pin. Input the readout clock to SQCK. (See Timing Chart 2-4.) The error rate is output from the SQSO pin. Input the readout clock to SQCK. (See Timing Chart 2-6.) —: don't care* $8X command TXOUT = 0 and $A8X command SDTOOUT = 0 must be set.

– 44 – CXD3027R Command bit Processing VCOSEL2 = 0 VCOSEL2 = 1 Wide-band PLL VCO2 is set to normal speed. Wide-band PLL VCO2 is set to approximately twice the normal speed. Command bit KSL1 KSL0 Processing Output of wide-band PLL VCO2 is 1/1 frequency-divided. Output of wide-band PLL VCO2 is 1/2 frequency-divided. Output of wide-band PLL VCO2 is 1/4 frequency-divided. Output of wide-band PLL VCO2 is 1/8 frequency-divided. * Block Diagram of VCO Internal Path Selector 1/2 Selector To D SP interior KSL3, 2VC O 1C S1, 0 N o.2 VC O 1 N o.3 VC O 1 N o.4 VC O 1 VC O 1SEL N o.1 VC O 1 Low -speed VC O 2 H igh-speed VC O 2 Selector 1/2 Selector To D SP interior KSL1, 0VC O 2C S VC O 2SEL VCO1 internal path VCO2 internal path

– 45 – CXD3027R VCO1 CS1 VCO1 CS0 0 VCO2 CS ERC4 SCOR SEL SCSY SOCT1 TXON TXOUT OUTL1 OUTL0 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 Data 4 Data 5 Data 6 Command MODE specification See page 43. Command bit Processing VCO2 CS = 0 VCO2 CS = 1 Selects the low-speed wide-band PLL VCO2. Selects the high-speed wide-band PLL VCO2. * The CXD3027R has two wide-band PLL VCO2s, and this command selects one of these VCO2s. * The block diagrams for VCO1 and VCO2 including VCOSEL1, VCOSEL2, KSL0 to KSL3, VCO1CS0, VCO1CS1, and VCO2CS are shown on the previous page. * The CXD3027R has four multiplier PLL VCO1s, and this command selects one of these VCO1s. Command bit VCO1CS1 VCO1CS0 Processing Selects the No. 1 VCO1. Selects the No. 2 VCO1. Selects the No. 3 VCO1. Selects the No. 4 VCO1. $8X commands cont.

– 46 – CXD3027R Command bit TXON = 0 Processing When CD TEXT data is not demodulated, set TXON to 0. When CD TEXT data is demodulated, set TXON to 1. * See "§4-15. CD TEXT Data Demodulation". TXON = 1 Command bit Processing SCSY = 0 SCSY = 1 No processing. GRSCOR (protected SCOR) synchronization is applied again. * Used to resynchronize GRSCOR. The rising edge signal of this command bit is used internally, so when resynchronizing GRSCOR, first return the setting to 0 and then set to 1. GRSCOR is the crystal accuracy SCOR signal obtained by removing the motor wow component. This signal is synchronized with PCMDATA. The resynchronization conditions are when GTOP = high or when the GRSRST pin = high. (Same as when SCSY = 1 is sent by the $8X command.) Command bit TXOUT = 0 Processing Various signals except for CD TEXT are output from the SQSO pin. CD TEXT data is output from the SQSO pin. * See "§4-15. CD TEXT Data Demodulation". TXOUT = 1 Command bit OUTL1 = 0 Processing C4M and WDCK are output. C4M and WDCK outputs are set low.OUTL1 = 1 Command bit OUTL0 = 0 OUTL0 = 1 Processing XPCK, PCMD, BCK, LRCK and EMPH are output. XPCK, PCMD, BCK, LRCK and EMPH outputs are set low. Command bit Processing SCOR SEL = 0 SCOR SEL = 1 WDCK signal is output. GRSCOR (protected SCOR) is output. * Used when outputting GRSCOR from the WDCK pin. Command bit Processing ERC4 = 0 ERC4 = 1 C2 error double correction is performed when DSPB = 1. C2 error quadruple correction is performed even when DSPB = 1.

– 47 – CXD3027R Command Data 1 Function specification 1 DSPB ON-OFF A.SEQ ON-OFF 1 D3 D2 D1 D0 Data 2 BiliGL MAIN BiliGL SUB FLFC D3 D2 D1 $9X commands Command bit DSPB = 0 DSPB = 1 Normal-speed playback, C2 error quadruple correction. Double-speed playback, C2 error double correction. (quadruple correction when ERC4 = 1) Processing Normally FLFC = 0. In CAV-W mode, set FLFC to 1 independently of the playback speed. Command bit BiliGL SUB = 0 BiliGL SUB = 1 STEREO SUB MAIN Mute BiliGL MAIN = 0BiliGL MAIN = 1 Definition of bilingual capable MAIN, SUB and STEREO The left channel input is output to the left and right channels for MAIN. The right channel input is output to the left and right channels for SUB. The left and right channel inputs are output to the left and right channels, respectively, for STEREO. Command bit Processing OUTL2 = 0 OUTL2 = 1 WFCK is output. WFCK is set low. Command MODE specification Data 7 0 0 OUTL2 0 D3 D2 D1 D0 Command Data 3 Data 4 Data 5 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 0 0 0 0 1 0 0 1 0 0 0 0Function specification

– 48 – CXD3027R Command Data 6 Function specification 0 0 0 0 D3 D2 D1 D0 Data 7 DIV4 0 0 0 D3 D2 D1 D0 Command bit DIV4 = 0 DIV4 = 1 Digital PLL master clock; conventional mode. (preset) Digital PLL master clock; 2/3 mode. Processing This switches the digital PLL master clock. Either the conventional mode or the 2/3 mode (2/3 of the conventional clock) can be selected. Note) Do not set DIV4 to 1 when DSPB = 0. Command Data 1 Audio CTRL 0 0 Mute ATT D3 D2 D1 D0 Data 2 PCT1 PCT2 D3 D2

0 SOC2

$AX commands Command bit Mute = 0 Mute = 1 Mute off if other mute conditions are not set. Mute on. Peak register reset. Meaning Command bit ATT = 0 ATT = 1 Attenuation off. –12dB Meaning Mute conditions (1) When register A mute = 1. (2) When register 8 DOUT Mute F = 1 and Digital Out is on ($B command MD2 = 1). (3) When GFS stays low for over 35ms (during normal-speed). (4) When register 9 BiliGL MAIN = Sub = 1. (5) When register A PCT1 = 1 and PCT2 = 0. (1) to (3) perform zero-cross muting with a 1ms time limit. Command bit PCT1 PCT2 Normal mode Level meter mode Peak meter mode Normal mode

0dB
0dB Mute
0dB C1: double; C2: quadruple C1: double; C2: quadruple C1: double; C2: double C1: double; C2: double Meaning PCM Gain ECC error correction ability

– 49 – CXD3027R Description of level meter mode(see Timing Chart 1-4.)

When the LSI is set to this mode, it performs digital level meter functions.
When the 96-bit clock is input to SQCK, 96 bits of data are output to SQSO. The initial 80 bits are subcode-Q data (see "[2] Subcode Interface"). The last 16 bits are LSB first, which are 15-bit PCM data (absolute values) and an L/R flag. The final bit (L/R flag) is high when the 15-bit PCM data is from the left channel and low when the data is from the right channel.
The PCM data is reset and the L/R flag is inverted after one readout. Then the measurement for the maximum value continues until the next readout. Description of peak meter mode(see Timing Chart 1-5.)
When the LSI is set to this mode, the maximum PCM data value is detected regardless of if it comes from the left or right channel. The 96-bit clock must be input to SQCK to read out this data.
When the 96-bit clock is input, 96 bits of data are output to SQSO and the value is set in the LSI internal register again. In other words, the PCM maximum value register is not reset by the readout.
To reset the PCM maximum value register to 0, set PCT1 = PCT2 = 0 or set the $AX command Mute.
The subcode-Q absolute time is automatically controlled in this mode. In other words, after the maximum value is generated, the absolute time for CRC to become OK is retained in the memory. Normal operation is conducted for the relative time.
The final bit (L/R flag) of the 96-bit data is normally 0.
The pre-value hold and average value interpolation data are fixed to level (–∞ ) for this mode. SENS output switching
This command is used to output the SQSO pin signal from the SENS pin. When SOC2 = 0, SENS output is performed as usual. When SOC2 = 1, the SQSO pin signal is output from the SENS pin. At this time, the readout clock is input to the SCLK pin. Note) Perform the SOC2 switching when SQCK = SCLK = high. Command bit SOC2 = 0 SOC2 = 1 The SENS signal is output from the SENS pin as usual. The SQSO pin signal is output from the SENS pin. Processing Command Data 3 Data 4 Data 5 Data 6 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0Audio CTRL

– 50 – CXD3027R $A4 commands (preset: $A4C800) Data 1 RSL1 RSL0 DTSL1 DTSL0 MCSL1 MCSL0 SDSL SDSL SDSL (Signal select) Data 2 Data 3 Data 4 Command EN XSOE CKOUT SL2 CKOUT SL1 SLD BBIN D3 D2 D1 D0 D3 D2 D1 D0 Data 5 Data 6 Data 7 RSL1 RSL0 Processing The external buffer RAM is set to 4M bits. The external buffer RAM is set to 16M bits. RSL1, 0: These bits set the external buffer RAM. *: preset DTSL1, DTSL0: See the second half of the description of $A4 commands. MCSL1: This bit sets the DAC block master clock. When 0, the DAC block master clock is set to 16.9344MHz (384fs). (default) When 1, the DAC block master clock is set to 33.8688MHz (768fs). MCSL0: This bit sets the shock-proof memory controller block master clock. When 0, the shock-proof memory controller block master clock is set to 16.9344MHz (384fs). (default) When 1, the shock-proof memory controller block master clock is set to 33.8688MHz (768fs). ENXSOE: This bit switches the command input method. When 0, the command transfer clock and the SENS serial data readout clock are input from the respective pins. (default) When 1, the command transfer clock and the SENS serial data readout clock are input from the CLOK pin. The clock input is switched with the XSOE pin. At this time, connect the SCLK pin to high. ENXSOE XSOE pin CLOK pin SCLK pin Command transfer clock input Command transfer clock input SENS serial data readout clock input Command transfer clock input SENS serial data readout clock input SENS serial data readout clock input Connect to high. Connect to high. L H L H In addition, when ENXSOE is set to 1 and the SQSO pin signal output is read from the SENS pin, the command input method is as follows. At this time, connect the SCLK and SQCK pins to high. See the command descriptions for $A command SOC2 and $8 commands TXOUT, SOCT0 and SOCT1.

– 51 – CXD3027R ENXS OE XSOE pin SOC2 TXOUT SOCT0 SOCT1 CLOK pin SENS pin Command transfer clock input SENS serial data readout clock input Subcode-Q readout clock input Various signal readout clock input Error rate readout clock input CD TEXT data readout clock input Readout clock input of shock-proof memory controller serial data High or low output SENS output*1 Subcode-Q output Various signal output*2 Error rate output*3 CD TEXT data output Shock-proof memory controller serial data output $A8 SDT0 OUT H L L L L L L *: don't care 1 See "§1-4. Description of SENS Signals" for the SENS output. *2 The output signals are PER7 to PER0, FOK, GFS, LOCK, EMPH, ALOCK and VF9 to VF0. For details, see Timing Chart 2-4. *3 For the error rate timing, see Timing Chart 2-6. CKOUTSL2, CKOUTSL1: These bits select the clock output from the R4M pin. When the crystal is 16.9344 MHz and XTSL = high, the output frequency is halved. CKOUTSL2 CKOUTSL1 Processing 4.2336MHz output 8.4672MHz output 4.2336MHz output Changes in CAV-W mode and variable pitch mode. * 0 *: preset DTSL1, DTSL0: These bits select the data output from the DOUT pin. In external mode, the data input through the LRCKI, BCKI and PCMDI pins is used. DOUT output in the following tables is valid when $34A commands DOUT EN and DOUT EN2 are both 1. In this case, see "$34A commands". When $34A commands DOUT EN and DOUT EN2 are both 0, see "§4-5-2. Digital Out from DA Interface Input". At this time, the data from the CD DSP is output from the DOUT pin with a subcode is added. SDSL2, SDSL1: These bits select the data input to the DAC block and the data output from the PCMD pin. SLDBBIN: This bit selects the data input to the DAC block and the data output from the PCMD and DOUT pins.

– 52 – CXD3027R When SLDBBIN = 0, the internally connected data is selected. (default) DTSL1 DSP mode Shock-proof memory controller mode DSP mode Shock-proof memory controller mode DSP mode Shock-proof memory controller mode DSP mode Shock-proof memory controller mode DSP & DAC mode Shock-proof memory controller & DAC mode DSP mode Shock-proof memory controller mode DSP mode External mode DSP mode DSP & DAC mode Shock-proof memory controller mode Shock-proof memory controller & DAC mode DSP mode DSP & DAC mode Shock-proof memory controller mode Shock-proof memory controller & DAC mode DSP mode DSP & DAC mode Shock-proof memory controller mode Shock-proof memory controller & DAC mode DSP mode DSP & DAC mode Shock-proof memory controller mode Shock-proof memory controller & DAC mode DTSL0 SDSL2 SDSL1 SDSL0 Input to DAC block DOUT output PCMD output *: preset *1: The relationship between LRCK, BCK and PCMD changes according to the setting value. When SDSL0 = 0, the LRCK, BCK and PCMD phase difference is constant but the LRCK frequency changes when SDSL0 is switched. When SDSL0 = 1, the LRCK frequency is constant but the phase difference between LRCK, BCK and PCMD changes before and after SDSL1 is switched. When not switching the output data selection, set SDSL1 and SDSL0 to the same value.

– 53 – CXD3027R DTSL1 External mode External & DAC mode DSP mode Shock-proof memory controller mode DSP mode External mode DSP mode External & DAC mode Shock-proof memory controller mode External & DAC mode DSP mode External & DAC mode Shock-proof memory controller mode External & DAC mode DSP mode External & DAC mode Shock-proof memory controller mode External & DAC mode DSP mode External & DAC mode Shock-proof memory controller mode External & DAC mode DTSL0 SDSL2 SDSL1 SDSL0 Input to DAC block DOUT output PCMD output When SLDBBIN = 1, the data input from the LRCKI, BCKI and PCMDI pins is selected. 1: The relationship between LRCK, BCK and PCMD changes according to the setting value. When SDSL0 = 0, the LRCK, BCK and PCMD phase difference is constant but the LRCK frequency changes when SDSL0 is switched. When SDSL0 = 1, the LRCK frequency is constant but the phase difference between LRCK, BCK and PCMD changes before and after SDSL1 is switched. When not switching the output data selection, set SDSL1 and SDSL0 to the same value.

– 54 – CXD3027R $A5 commands (when Data 2 D3 = 0, D2 = 0) (preset: $A50400) Data 1 ZMUTA SMUT AD10 AD9 AD8 AD7 AD6 D1 D0 AD5 AD4A5 (Bass boost) Data 2 Data 3 Data 4 Command AD3 AD2 AD1 AD0 Data 5 ZMUTA: This bit sets the zero detection analog mute on/off. When 0, zero detection analog mute is on. (default) When 1, zero detection analog mute is off. When zero data is detected for both the left and right channels, the LPF block output is set to center output. SMUT: This bit sets the soft mute on/off. When 0, soft mute is off. (default) When 1, soft mute is on. AD10 to AD0: These bits set the attenuation data. The attenuation data consists of 11 bits, and is set as follows. Attenuation data Audio output 7FF (hex) 7FE (hex) 402 (hex) 401 (hex) 400 (hex) 3FF (hex) 3FE (hex) 001 (hex) 000 (hex) +6.02dB +6.016dB +0.017dB +0.0085dB 0dB –0.0085dB –0.017dB –60.206dB The audio output from 001 (h) to 7FF (h) is obtained using the following equation: Audio data output = 20 log [dB] 20 log Attenuation data 1024 *: preset

– 55 – CXD3027R $A5 commands (when Data 2 D3 = 0, D2 = 1) (preset: $A540A4) Data 1 PWDN ZDPL WOC DAC EMPH HiCut FILTER BST CL OBIT1 OBIT0A5 (Bass boost) Data 2 Data 3 Data 4 Command Data 5 PWDN: This bit sets the DAC block operation mode. When 0, the DAC block clock is stopped. This makes it possible to reduce power consumption. (default) When 1, the DAC block operates normally. ZDPL: This bit sets the zero detection flag polarity. When 0, the LRMU pin is set low during mute. (default) When 1, the LRMU pin is set high during mute. WOC: When WOC = 1, the DAC sync window opens. This is used to synchronize the DAC. DAC EMPH: This bit sets the digital de-emphasis on/off. When 0, digital de-emphasis is off. (default) When 1, digital de-emphasis is on. HiCutFILTER: This bit sets the high-cut filter on/off. When 0, the high-cut filter is off. (default) When 1, the high-cut filter is on. BSTCL: This bit sets the bass boost level clear on/off. 1: On; the set bass boost level is cleared to 0dB. 0: Off; normal operation (default) OBIT1, OBIT0:These bits set the word length of the serial data output from the PCMD pin. The serial data word length can be selected only when the data output from the PCMD pin is set to DAC output. OBIT1 OBIT0 Serial data word length 20bit 18bit 16bit *: preset

– 56 – CXD3027R $A5 commands (when Data 2 D3 = 1, D2 = 0) (preset: $A58000) Data 1 BBON1 BBON0 HBON1 HBON0 BBSL1 BBSL0 HBSL1 HBSL0 BBST Vdwn1 BBST Vdwn0 (Bass boost) Data 2 Data 3 Data 4 Command BBST Vup1 BBST Vup0 BBST Uth BBST Lth Data 5 BBON1, BBON0: These bits set the bass boost on/off and the turnover frequency. BBON1 BBON0 Processing Bass boost is off. Bass boost is on and the turnover frequency is set to 125Hz. Bass boost is on and the turnover frequency is set to 160Hz. Bass boost is on and the turnover frequency is set to 200Hz. * 0 *: preset HBON1, HBON0: These bits set the high boost on/off and the turnover frequency. HBON1 HBON0 Processing High boost is off. High boost is on and the turnover frequency is set to 5kHz. High boost is on and the turnover frequency is set to 7kHz. * 0 *: preset BBSL1, BBSL0: These bits set the boost level for bass boost. BBSL1 BBSL0 Processing The boost level for bass boost is set to 10dB. The boost level for bass boost is set to 14dB. The boost level for bass boost is set to 18dB. The boost level for bass boost is set to 22dB. * 0 *: preset HBSL1, HBSL0: These bits set the boost level for high boost. HBSL1 HBSL0 Processing The boost level for high boost is set to 4dB. The boost level for high boost is set to 6dB. The boost level for high boost is set to 8dB. The boost level for high boost is set to 10dB. * 0 *: preset

– 57 – CXD3027R BBST Vdwn1, BBST Vdwn0: These bits set the boost attack time (Vol Down) for bass and high boost. BBST Vdwn1 BBST Vdwn0 Processing The boost attack time for bass and high boost is set to standard. The boost attack time for bass and high boost is set to fast. The boost attack time for bass and high boost is set to slow. * 0 *: preset BBST Vup1, BBST Vup0: These bits set the boost release time (Vol Up) for bass and high boost. BBST Vup1 BBST Vup0 Processing The boost release time for bass and high boost is set to standard. The boost release time for bass and high boost is set to fast. The boost release time for bass and high boost is set to slow. * 0 *: preset BBST Uth: This bit sets the bass and high boost Uth. When 0, Uth is set to –1.9dB. (default) When 1, Uth is set to –0.9dB. BBST Lth: This bit sets the bass and high boost Lth. When 0, Lth is set to –12dB. (default) When 1, Lth is set to –4.4dB. * When the volume rises above Uth, the boost level is reduced. The speed at which the boost level is reduced is the attack time. When the volume falls below Lth, the boost level is increased up to the setting value. The speed at which the boost level is increased is the release time. $A5 commands (when Data 2 D3 = 1, D2 = 1) (preset: $A5C000) Data 1 COMP ON 0A5 (Bass boost) Data 2 Data 3 Data 4 Command PDM INV Data 5 COMP ON: This bit sets the compressor on/off. When 0, the compressor is off. (default) When 1, the compressor is on. PDM INV: This bit sets the DAC block PDM signal polarity. (The HP circuit polarity is also set at the same time.) When 0, the polarity is set to non-inverted. (default) When 1, the polarity is set to inverted.

– 58 – CXD3027R MSL2 The entire DRAM area can be used as audio data. 32K bits 64K bits 128K bits 256K bits 512K bits 1M bits 2M bits MSL1 MSL0 DRAM area that can be accessed from the microcomputer *: preset $A7 commands (preset: $A7200) Data 1 SL XQOK SL XWRE GTOP CHECK NOLIM WDCK SPSL COM READ2 REF SEL REF ON MSL2 MSL1 MSL0 A7(Shock-proof memory setting) Data 2 Data 3 Data 4 Command SL XQOK: This bit sets the XQOK control mode. When 0, XQOK should be controlled for the period from when SCOR goes high until GRSCOR goes high. (default) When 1, XQOK should be controlled for the period while GRSCOR is high. SL XWRE: This bit sets the XWRE control mode. When 0, XWRE should be controlled for the period from when SCOR goes high until GRSCOR goes high. (default) When 1, XWRE should be controlled for the period while GRSCOR is high. GTOP CHECK: This bit controls GRSCOR generation when GTOP is high. When 0, the GRSCOR generation circuit is not resynchronized even when GTOP is high. When 1, the GRSCOR generation circuit is resynchronized when GTOP goes high. (default) NOLIM WDCK: Always set to 1. SPSL COM: This bit sets whether to control XQOK, XWRE and XRDE with pins or serial data. When 0, XQOK, XWRE and XRDE should be controlled with pins. (default) When 1, XQOK, XWRE and XRDE should be controlled with serial data ($A8). READ2: This bit sets the audio data readout speed from the shock-proof memory controller block. When 0, Data is read out at normal speed. (default) When 1, Data is read out at double speed. REF SEL: This bit sets the DRAM refresh rate. When 0, refresh is performed 2048 times/46.44ms. (default) When 1, refresh is performed 2048 times/23.22ms. REF ON: This bit sets the DRAM refresh function on/off. When 0, the refresh function is off. (default) When 1, the refresh function is on. MSL2 to MSL0:These bits set the DRAM area that can be accessed from the microcomputer.

– 59 – CXD3027R $A8 commands (preset: $A8F8) Data 1 XQOK XWRE XRDE XSOEO XSOEO SDTO OUT D3 D2 D1 D0 (Shock-proof memory control) Data 2 Data 3 Data 4 Command XQOK, XWRE, XRDE: When $A7 command SPSL COM = 1, XQOK, XWRE and XRDE are controlled with serial data. XSOEO: This bit controls the serial data from the shock-proof block. Shock-proof block data is loaded to the serial readout register by detecting the falling edge of XSOEO. XSOEO2: This bit is used when the microcomputer reads data from the DRAM. The shock-proof memory controller block loads the data from the DRAM to the serial readout register by detecting the fall of XSOEO2. SDTO OUT: This bit is used to output serial data from the shock-proof block to the SQSO pin. When 0, various signals are output from the SQSO pin. For details on these signals, see $8X commands SOCT1, SOCT0 and TXOUT. (default) When 1, the shock-proof block serial data is output from the SQSO pin.

– 60 – CXD3027R $A9 commands (preset: $A90000) Data 1 SubQA SubQA SubQA SubQA SubQD SubQD SubQD SubQD (DOUT subcode-Q setting) Data 2 Data 3 Data 4 Command SubQD SubQD SubQD SubQD D3 D2 D1 D0 D3 D2 D1 D0 Data 5 Data 6 Data 7 SubQA3 to SubQA0, SubQD7 to SubQD0: These bits set the Ubit inside the DOUT generation circuit in the DAC block. Note that these bits have no effect on the DOUT generation circuit in the CD DSP block. Control, address Movement number INDEX number Elapsed time within a movement (minutes) Elapsed time within a movement (seconds) Elapsed time within a movement (frames) (Set to 0.) Absolute time (minutes) Absolute time (seconds) Absolute time (frames) (Control command) SubQA3 SubQA2 SubQA1 SubQA0 SubQD7 SubQD6 SubQD5 SubQD4 SubQD3 SubQD2 SubQD1 SubQD0 Setting contents Q17 Q25 Q33 Q41 Q49 Q57 Q65 Q73 DON Q10 Q18 Q26 Q34 Q42 Q50 Q58 Q66 Q74 DCL Q11 Q19 Q27 Q35 Q43 Q51 Q59 Q67 Q75 DUP1 Q12 Q20 Q28 Q36 Q44 Q52 Q60 Q68 Q76 DUP0 Q13 Q21 Q29 Q37 Q45 Q53 Q61 Q69 Q77 DLD Q14 Q22 Q30 Q38 Q46 Q54 Q62 Q70 Q78 Q15 Q23 Q31 Q39 Q47 Q55 Q63 Q71 Q79 Q16 Q24 Q32 Q40 Q48 Q56 Q64 Q72 Q80 DON: This bit sets the Ubit output on/off inside the DOUT generation circuit in the DAC block. When 0, Ubit is not output. (default) When 1, Ubit is output. DCL: This bit clears the elapsed time within a movement to 0. The elapsed time is cleared to 0 at the falling edge of DCL (DCL = 1 ﬁ 0). (default: DCL = 1) DUP1: This bit sets the absolute time counter operate/stop. When 0, the absolute time counter is stopped. (default) When 1, the absolute time counter operates. DUP0: This bit sets the elapsed time within a movement counter operate/stop. When 0, the elapsed time within a movement counter is stopped. (default) When 1, the elapsed time within a movement counter operates. DLD: This bit is used when setting the INDEX number, elapsed time within a movement, and absolute time. When 0, the settings cannot be changed. (default) When 1, the settings can be changed. Note that 0 is output for the INDEX number, elapsed time within a movement, and absolute time while DLD = 1. The control, address and movement number settings can be changed regardless of the DLD setting.

– 61 – CXD3027R $A9 commands (preset: $A9E00000) Data 1 DRWR DRADR DRD15 DRD14 DRD13 DRD12A9E (DRAM I/F) Data 2 Data 3 Data 4 Command DRD11 DRD10 DRD9 DRD8 DRD7 DRD6 DRD5 DRD4 DRD3 DRD2 DRD1 DRD0 Data 5 Data 6 Data 7 DRWR: This bit sets write/read for access from the microcomputer to the DRAM. When 0, the read from DRAM mode is set. (default) When 1, the write to DRAM mode is set. DRADR: This bit sets the address control method for access from the microcomputer to the DRAM. When 0, relative address control is set. (default) When 1, absolute address control is set. DRD15 to DRD0: These bits set the data to be written to the DRAM for access from the microcomputer to the DRAM. $A9 commands (preset: $A9F00000) Data 1 DADR19 DADR18 DADR17 DADR16 DADR15 DADR14 DADR13 DADR12A9F (DRAM I/F) Data 2 Data 3 Data 4 Command DADR11 DADR10 DADR9 DADR8 DADR7 DADR6 DADR5 DADR4 DADR3 DADR2 DADR1 DADR0 Data 5 Data 6 Data 7 DADR19 to DADR0: These bits set the DRAM address for access from the microcomputer to the DRAM.

– 62 – CXD3027R $AA commands (preset: $AA004) Data 1 ADPON BITSL1 BITSL0 GRSEL AA(Compression setting) Data 2 Data 3 Data 4 Command ADPON: This bit sets audio data compressed/uncompressed. When 0, the audio data uses uncompressed mode. (default) When 1, the audio mode is compressed mode. BITSL1, BITSL0:These bits set the audio data compression mode. BITSL1 BITSL0 Compression mode 4 bits 6 bits 8 bits * 0 *: preset GRSEL: This bit selects the GRSCOR signal output. Note that GRSCOR is output from the WDCK pin when $8 command SCOR SEL = 1. When 0, the GRSCOR signal generated by the CD DSP block is output. When 1, the GRSCOR signal is output at the timing used inside the shock-proof memory controller block. (default) $AB commands (preset: $AB000000) Data 1 ARDTEN AB (EFM playability enhancement setting) Data 2 Data 3 Data 4 Command Data 5 Data 6 Data 7 ARDTEN: This is the EFM playability enhancement setting. When 0, the EFM playability enhancement function is off. When 1, the EFM playability enhancement function is on. * Set this command in the condition when a disc is not being played back.

– 63 – CXD3027R $AC commands (preset: $AC0C0) Data 1 AVW SFP5 SFP4 SFP3 SFP2 SFP1 SFP0 AC (Sync expansion specification) Data 2 Data 3 Data 4 Command AVW: This bit sets the sync protection window width automatic expansion function. When 0, the sync protection window width automatic expansion function is off. When 1, the sync protection window width automatic expansion function is on. This setting is not affected by the sync forward protection times setting SFP5 to 0. * The sync protection window width (±6 channel clocks when WSEL = 0, ±26 channel clocks when WSEL = 1) is widened 32 channel clocks at a time each time a sync mark is inserted during the interval from the 16th forward protection until GFS goes high. When the maximum window width is reached (when the window width exceeds 588 channel clocks), GTOP goes high. SFP5 to SFP0:These bits set the frame sync forward protection times. The setting range is from 1 to 3F (h). For details on frame sync protection, see "§4-2. Frame Sync Protection". * Part of this command bit register is also used by $C SFP3 to SFP0. Of $AC SFP3 to SFP0 or $C SFP3 to SFP0, the command bit setting made last is valid. When using an existing status, set the value with $C SFP5 to SFP0. When using the $AC commands, set $AC SFP3 to SFP0 to the value set by $C SFP3 to SFP0.

– 64 – CXD3027R $AD commands (preset: $AD00) Data 1 ADCPS DSP SLEEP DSSP SLEEP ASYM SLEEP ESP SLEEP LPF SLEEP DSUB SLEEP D3 D2 D1 D0 AD (Sleep setting) Data 2 Data 3 Data 4 Command ADCPS: This bit sets the operating mode of the DSSP block A/D converter. When 0, the operating mode of the DSSP block A/D converter is set to normal. (default) When 1, the operating mode of the DSSP block A/D converter is set to power saving. DSP SLEEP: This bit sets the operating mode of the DSP block. When 0, the DSP block operates normally. (default) When 1, the DSP block clock is stopped. This makes it possible to reduce power consumption. DSSP SLEEP: This bit sets the operating mode of the DSSP block. When 0, the DSSP block operates normally. (default) When 1, the DSSP block clock is stopped. In addition, the A/D converter and operational amplifier in the DSSP block are set to standby mode. This makes it possible to reduce power consumption. ASYM SLEEP: This bit sets the operating mode of the asymmetry correction circuit and VCO1/VCO2. When 0, the asymmetry correction circuit and VCO1/VCO2 operate normally. (default) When 1, the operational amplifier in the asymmetry correction circuit is set to standby mode. In addition, the multiplier PLL VCO1 and wide-band PLL VCO2 oscillation are stopped. This makes it possible to reduce power consumption. ESP SLEEP: This bit sets the operating mode of the shock-proof memory controller block. When 0, the shock-proof memory controller block operates normally. (default) When 1, the shock-proof memory controller block clock is stopped. This makes it possible to reduce power consumption. LPF SLEEP: This bit sets the operating mode of the analog low-pass filter block. When 0, the analog low-pass filter block operates normally. When 1, the analog low-pass filter block is set to standby mode. (default) This makes it possible to reduce power consumption. DSUB SLEEP: This bit sets the operating mode of the Ubit generation block inside the DOUT generation circuit in the DAC block. This setting has no effect on the DOUT generation circuit in the CD DSP block. When 0, the Ubit generation block operates normally. (default) When 1, The clock for the Ubit generation block inside the DOUT generation circuit in the DAC block is stopped. This makes it possible to reduce power consumption. Also, in this case Ubit is set to 0. * The DAC block clock can be stopped by setting $A5 command PWDN (when Data 2 D3 = 0, D2 = 1).

– 65 – CXD3027R Command bit VARION = 0 Processing Variable pitch mode is off. (The internal clock uses the crystal reference.) Variable pitch mode is on. (The internal clock uses the VCO2 reference.)VARION = 1 Command bit VARIUSE = 0 Processing Set VARIUSE = 0 when not using variable pitch mode. Set VARIUSE = 1 when using variable pitch mode. * See "$DX commands" for the variable pitch range and example of use. VARIUSE = 1 Data 1 VARI ON VARI USE D3 D2 D1 D0 D3 D2 D1 D0 AE (Variable pitch setting) Data 2 Data 3 Data 4 Command $AE commands (preset: $AE0)

– 66 – CXD3027R Data 1 SYG3 EA SYG2 EA SYG1 EA SYG0 EA MDP OUTSL1 MDP OUTSL0 LPWR2 MDS CTL MDP UP MDP CTL4 AF(Spindle servo setting) Data 2 Data 3 Data 4 Command $AF commands (preset: $AF8000) SYG3EA to SYG0EA: These bits set the spindle drive output gain. However, this is valid only in CLV-N mode. SYG3EA 0 (–∞ dB) 0.125 (–18.1dB) 0.250 (–12.0dB) 0.375 (–8.5dB) 0.500 (–6.0dB) 0.625 (–4.1dB) 0.750 (–2.5dB) 0.875 (–1.2dB) 1.000 (0.0dB) 1.125 (+1.0dB) 1.250 (+1.9dB) 1.375 (+2.8dB) 1.500 (+3.5dB) 1.625 (+4.2dB) 1.750 (+4.9dB) 1.875 (+5.5dB) SYG2EA SYG1EA SYG0EA GAIN *: preset MDP OUTSL1, MDP OUTSL0: These bits set the spindle drive output method. MDP CTL3 MDP CTL2 MDP CTL1 MDP CTL0 Data 5 MDP OUTSL1 MDP OUTSL0 Spindle drive output Ternary output from the MDP pin Binary output from the MDS and MDP pins Command-based MDP and MDS output control * 0 *: preset

– 67 – CXD3027R LPWR2: The low output (brake pulse) of the MDP pin can be masked. When 0, binary output is high or low output, and ternary output is high, low or high impedance output. (default) When 1, high or high impedance is output. This makes it possible to mask the brake pulse. MDS CTL: This bit sets the PWM output polarity according to the setting from the microcomputer. (valid when MDPOUTSL1 = 0 and MDPOUTSL0 = 1) When 0, the MDS pin output is set low. When 1, the MDS pin output is set high. MDP UP: This bit switches the MDP pin according to the setting from the microcomputer. (valid when MDPOUTSL1 = 0 and MDPOUTSL0 = 1) When 0, the MDP pin output is set to PWM output. When 1, the MDP pin output is set high. MDP CTL4 to MDP CTL0: These bits set the PWM output value according to the setting from the microcomputer. (valid when MDPOUTSL1 = 0 and MDPOUTSL0 = 1) The carrier frequency is 176.4kHz. (88.2kHz when set to quasi-double speed) At the minimum value (MDP CTL4 to MDP CTL0 = 0), the MDP pin output is set low. At the maximum value (MDP CTL4 to MDP CTL0 = 1F (h)), the MDP pin output is set high for 31/32 intervals. Note that when $AF command MDP UP = 1, the MDP pin output is set high regardless of the MDP CTL4 to MDP CTL0 setting value. Command-based MDP and MDS output control (MDPOUTSL1 = 0, MDPOUTSL0 = 1) (1) Timing Chart 1 LPWR2 = 0, MDPUP = 0, MDPCTL4 to 0 = 10 (hex) 5.67µs (176kH z) M D P (2) Timing Chart 2 LPWR2 = 0, MDPUP = 1, MDPCTL4 to 0 = 10 (hex) M D P H (3) Timing Chart 3 LPWR2 = 1, MDPUP = 0, MDPCTL4 to 0 = 10 (hex) M D P Z The MDP waveform ratio is set by MDP CTL4 to MDP CTL0. When MDP CTL4 to MDP CTL0 = 10 (h), 10 (h)/20 (h) intervals are high. When MDPUP = 1, MDP is fixed high regardless of MDP CTL4 to MDP CTL0. When LPWR2 = 1, the low output of MDP binary output becomes high impedance.

– 68 – CXD3027R $BX commands This command sets the traverse monitor count. Command Data 1 Data 2 Data 3 Data 4 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20Traverse monitor count setting

When the set number of tracks are counted during fine search, the sled control for the traverse cycle control goes off.
The traverse monitor count is set to monitor the traverse status using the SENS outputs COMP and COUT. Command bit MTSL1 MTSL0 Output data XUGF MINT0 RFCK C4M XPCK MNT1 XPCK FSTO GFS MNT2 XROF GFS C2PO MNT3 GTOP C2PO Command Data 5 Traverse monitor count setting 0 0 MTSL1 MTSL0 D3 D2 D1 D0 Data 6 ASYE MD2 0 0 D3 D2 D1 D0 The monitor output is set as follows. Command bit ASYE = 1 ASYE = 0 Asymmetry is on. Asymmetry is off. Processing Command bit MD2 = 0 MD2 = 1 Digital Out on/off control. Off when 0. Digital Out on/off control. On when 1. Processing * However, the $39 command SRO1 must be set to 0.

– 69 – CXD3027R Spindle servo coefficient setting CLV CTRL ($DX) Gain MDP1 Gain MDP0 Gain MDS1 Gain MDS0 Gain CLVS Gain MDS1 Gain MDS0 Gain CLVS GCLVS –12dB –6dB –6dB 0dB 0dB +6dB Command Data 1 D2 D1 D0 Gain DCLV0 Gain DCLV1 PCC1 PCC0 Data 2 D2 D1 D0 $CX commands

CLVS mode gain setting: GCLVS Gain MDP1 Gain MDP0 GMDP –6dB 0dB +6dB Gain DCLV1 Gain DCLV0 GDCLV 0dB +6dB +12dB Gain MDS1 Gain MDS0 GMDS –6dB 0dB +6dB
CLVP mode gain setting: GMDP: GMDS
DCLV overall gain setting: GDCLV Command bit PCC1 PCC0 Processing The VPCO signal is output. The VPCO pin output is high impedance. The VPCO pin output is low. The VPCO pin output is high.
This command controls the VPCO pin signal. The VPCO output can be controlled with this setting.

– 70 – CXD3027R Command Data 3 SFP3 SFP2 SFP1 SFP0 SRP3 SRP2 SRP1 SRP0Spindle servo coefficient setting D2 D1 D0 D3 D2 D1 D0 Data 4 Command Data 5 EDC7 EDC6 EDC5 EDC4 EDC3 EDC2 EDC1 EDC0Spindle servo coefficient setting D2 D1 D0 D3 D2 D1 D0 Data 6 * See "§4-2. Frame Sync Protection" regarding frame sync protection. Command bit SRP3 to 0 Sets the number of frame sync backward protection times. The setting range is from 1 to F (h). Processing Command bit SFP3 to 0 Sets the number of frame sync forward protection times. The setting range is from 1 to F (h). Processing

The CXD3027R can serially output the 40 bits (10 BCD codes) of error rate data selected by EDC7 to EDC0 from the SQSO pin and monitor this data using a microcomputer. In order to output error rate data, set $C commands for C1 and C2 individually, and set $8 commands SOCT0 and SOCT1 to 1. Then, the data can be read out from the SQSO pin by sending 40 SQCK pulses.

– 71 – CXD3027R Command Data 2 CLV CTRL VP7 VP6 VP5 VP4 D3 D2 D1 D0 Data 3 VP3 VP2 VP1 VP0 D3 D2 D1 D0 Data 4 VP CTL1 VP CTL0 0 0 D3 D2 D1 D0 $DX commands See "$CX commands". Command bit TB = 0 TB = 1 TP = 0 TP = 1 Bottom hold at a cycle of RFCK/32 in CLVS mode. Bottom hold at a cycle of RFCK/16 in CLVS mode. Peak hold at a cycle of RFCK/4 in CLVS mode. Peak hold at a cycle of RFCK/2 in CLVS mode.

Description

EDC7 = 0 EDC6 EDC5 EDC4 EDC3 EDC2 EDC1 EDC0 EDC7 = 1 EDC6 EDC5 EDC4 EDC3 EDC2 EDC1 EDC0 The [No C1 errors, pointer reset] count is output when 1. The [One C1 error corrected, pointer reset] count is output when 1. The [No C1 errors, pointer set] count is output when 1. The [One C1 error corrected, pointer set] count is output when 1. The [Two C1 errors corrected, pointer set] count is output when 1. The [C1 correction impossible, pointer set] count is output when 1. 7350-frame count cycle mode* 1 when 0. 73500-frame count cycle mode*2 when 1. The [No C2 errors, pointer reset] count is output when 1. The [One C2 error corrected, pointer reset] count is output when 1. The [Two C2 errors corrected, pointer reset] count is output when 1. The [Three C2 errors corrected, pointer reset] count is output when 1. The [Four C2 errors corrected, pointer reset] count is output when 1. The [C2 correction impossible, pointer copy] count is output when 1. The [C2 correction impossible, pointer set] count is output when 1. Processing Error rate monitor commands

1 The values selected by C1 (EDC1 to EDC6) and C2 (EDC0 to EDC6) are added to C1 and C2, respectively,

and output every 7350 frames. *2 The values selected by C1 (EDC1 to EDC6) and C2 (EDC0 to EDC6) are added to C1 and C2, respectively, and output every 73500 frames.

– 72 – CXD3027R The rotational velocity R of the spindle can be expressed with the following equation. R = · 1256 – n * The above setting should be 0, 0 except for the CAV-W operating mode. Command bit VPCTL1 VPCTL0 Processing The setting of VP0 to VP7 is multiplied by 1. The setting of VP0 to VP7 is multiplied by 2. The setting of VP0 to VP7 is multiplied by 3. The setting of VP0 to VP7 is multiplied by 4. Command bit Processing VP0 to 7 Sets the spindle rotational velocity. R: Relative velocity at normal speed = 1 n: VP0 to VP7 setting value 1: Multiple set by VPCTL0, 1 Command bit VP0 to 7 = F0 (H) VP0 to 7 = E0 (H) VP0 to 7 = C0 (H) Playback at half (normal) speed to Playback at normal (double) speed to Playback at (quadruple) speed Notes) 1. Values when crystal is 16.9344MHz and XTSL is low or when crystal is 33.8688MHz and XTSL is high. 2. Values in parentheses are for when DSPB is 1. F0 E0 0.5 1.5 R – Relative velocity [m ultiple] VP0 to VP7 setting value [h] D 0 2.5 C 0 3.5 D SPB = 0 DSPB = 1 The settings in CAV-W mode are as follows.

– 73 – CXD3027R Command bit Processing VPCTL1 to VPCTL0, VP7 to VP0 Sets the pitch for variable pitch mode. The settings in variable pitch mode are as follows. The pitch setting can be expressed with the following equation. P = [%]–n P: Pitch setting value n: VPCTL1 and VPCTL0, VP7 to VP0 setting value (two's complement, VPCTL1 = sign bit) The pitch setting range is from –48.7 to +51.2%. The plus pitch setting should not exceed the playback speed given in the Recommended Operating Conditions. An example of variable pitch mode commands is shown below. $EX001 (Sets INV VPCO = 1.) $AE4 (Setting to enable variable pitch mode.) $AEC (Turns on variable pitch mode. The internal clock uses the VCO2 reference.) $D60A00 (Sets the pitch to –1.0%.) $D60000 (Sets the pitch to 0.0%.) $AE4 (Turns off variable pitch mode. The internal clock uses the crystal reference.) VPCTL1 VPCTL0 VP7 to 0 00 (H) FF (H) 00 (H) FF (H) 00 (H) FF (H) 00 (H) E7 (H) Pitch setting value [%] +51.2 to +25.7 +25.6 to +0.1 0.0 to –25.5 –25.6 to –48.7 Command setting example $D60080 $D6FF80 $D600C0 $D6FFC0 $D60000 $D6FF00 $D60040 $D6E740 Command bit

– 74 – CXD3027R $EX commands Command Data 1 SPD mode CM3 CM2 CM1 CM0 D3 D2 D1 D0 Data 2 EPWM SPDC ICAP SFSL D3 D2 D1 D0 Data 3 VC2C HIFC LPWR VPON D3 D2 D1 D0 Command bit CM3 CM2 CM1 Spindle stop mode.*1 Spindle forward rotation mode.*1 Spindle reverse rotation mode. Valid only when LPWR = 0 in any mode.*1 Rough servo mode. When the RF-PLL circuit isn't locked, this mode is used to pull the disc rotations within the RF- PLL capture range. PLL servo mode. Automatic CLVS/CLVP switching mode. Used for normal playback. CM0 Mode STOP KICK BRAKE CLVS CLVP CLVA *1 See Timing Charts 1-6 to 1-29. In the digital CLV servo, the sampling frequency of the internal digital filter is switched simultaneously with the switching of CLVP/CLVS. Then, the CLVS mode cut-off frequency fc is 70Hz when $D command TB = 0 or 140Hz when $D command TB = 1. Spindle control can be set to the ternary output of only MDP or the binary outputs of MDP and MDS by $AF commands MDPOUTSL1 and MDPOUTSL0. Command bit EPWM SPDC ICAP Crystal reference CLV servo. VCO2 reference CLV servo. Used for playback in CLV-W mode.* Spindle control with VP0 to VP7. Spindle control with the external PWM. VCO control*3 SFSL VC2C HIFC LPWR VPON INV VPCO Mode CLV-N CLV-N CLV-W CAV-W CAV-W VCO-C 2 Figs. 3-1 and 3-2 show the control flow with the microcomputer software in CLV-W mode. *3 Fig. 3-3 shows the control flow with the microcomputer software in VCO-C mode.

– 75 – CXD3027R Mode CLV-N CLV-W CAV-W LPWR Command KICK BRAKE STOP KICK BRAKE STOP KICK BRAKE STOP KICK BRAKE STOP KICK BRAKE STOP 1-6 (a) 1-6 (b) 1-6 (c) 1-7 (a) 1-7 (b) 1-7 (c) 1-8 (a) 1-8 (b) 1-8 (c) 1-9 (a) 1-9 (b) 1-9 (c) 1-10 (a) 1-10 (b) 1-10 (c) Timing chart – Ternary output Mode CLV-N CLV-W CAV-W LPWR LPWR2 1-11 1-12 1-13 1-14 (EPWM = 0) 1-15 (EPWM = 0) 1-16 (EPWM = 1) 1-17 (EPWM = 1) Timing chart – Ternary output 1-18 (a) 1-18 (b) 1-18 (c) 1-19 (a) 1-19 (b) 1-19 (c) 1-20 (a) 1-20 (b) 1-20 (c) 1-21 (a) 1-21 (b) 1-21 (c) 1-22 (a) 1-22 (b) 1-22 (c) Timing chart – Binary output LPWR2 1-23 1-24 1-25 1-26 (EPWM = 0) 1-27 (EPWM = 0) 1-28 (EPWM = 1) 1-29 (EPWM = 1) Timing chart – Binary output

– 76 – CXD3027R Command SPD mode Data 4

This sets the gain when controlling the spindle with VP7 to VP0 in CAV-W mode. Note)The Gain CAV1, 0 commands are invalid for spindle control with the external PWM. D3 D2 D1 D0 Gain CAV1 Gain CAV0 0 INV VPCO Gain CAV1 Gain CAV0 Gain 0dB –6dB –12dB –18dB See page 75. Mode CLV-W CAV-W LPWR Command KICK BRAKE STOP KICK BRAKE STOP KICK BRAKE STOP KICK BRAKE STOP 1-8 (a) 1-8 (b) 1-8 (c) 1-8 (a) 1-8 (b) 1-8 (c) 1-10 (a) 1-10 (b) 1-10 (c) 1-10 (a) 1-10 (b) 1-10 (c) Timing chart – Ternary output 1-30 (a) 1-30 (b) 1-30 (c) 1-31 (a) 1-31 (b) 1-31 (c) 1-32 (a) 1-32 (b) 1-32 (c) 1-33 (a) 1-33 (b) 1-33 (c) Timing chart – Binary output LPWR2 Mode CLV-W CAV-W LPWR LPWR2 1-13 1-13 1-15 (EPWM = 0) 1-15 (EPWM = 0) 1-17 (EPWM = 1) 1-17 (EPWM = 1) Timing chart – Ternary output 1-34 1-35 1-36 (EPWM = 0) 1-37 (EPWM = 0) 1-38 (EPWM = 1) 1-39 (EPWM = 1) Timing chart – Binary output

– 77 – CXD3027R Timing Chart 1-3 R ch 16-bit C 2 Pointer Lch 16-bit C 2 Pointer If C 2 Pointer = 1, data is N G C 2 Pointer for upper 8 bits C 2 Pointer for low er 8 bits R ch C 2 Pointer C 2 Pointer for upper 8 bits C 2 Pointer for low er 8 bits Lch C 2 Pointer LR C K W D C K C D R O M = 0 C 2PO C D R O M = 1 C 2PO 48 bit slot

– 78 – CXD3027R Timing Chart 1-4 Level M eter Tim ing 96 clock pulses W FC K 1 2 3 96 clock pulses C R C F C R C F 1 2 3 Peak data of this section 16 bits R /LL/R 96 bits data H old section 1 2 3 80 81 96 C R C F SQ C K D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 13 D 14 L/R Peak data L/R flag Sub Q D ata See "Sub C ode Interface" 15-bit peak-data Absolute value display, LSB first 750ns to 120µs SQ C K SQ SO SQ SO

– 79 – CXD3027R Timing Chart 1-5 M easurem ent Peak M eter Tim ing 96 clock pulses C R C F W FC K 1 2 3 M easurem ent M easurem ent 96 clock pulses C R C F C R C F 1 2 3 SQ C K

– 80 – CXD3027R Ternary output from MDP pin ($AF MDPOUTSL1 = 0, MDPOUTSL0 = 0) Timing Chart 1-6 CLV-N mode LPWR = 0, LPWR2 = 0 KIC K M D P H (a) KIC K BR AKE M D P (b) BR AKE STO P M D P (c) STO P Z Z L Z Timing Chart 1-7 CLV-W mode (when following the spindle rotational velocity)LPWR = 0, LPWR2 = 0 KIC K M D P H (a) KIC K BR AKE M D P (b) BR AKE STO P M D P (c) STO P Z Z L Z Timing Chart 1-8 CLV-W mode (when following the spindle rotational velocity)LPWR = 1, LPWR2 = 0 KIC K M D P H (a) KIC K BR AKE M D P (b) BR AKE Z STO P M D P (c) STO P Z Z Timing Chart 1-9 CAV-W mode LPWR = 0, LPWR2 = 0 KIC K M D P H (a) KIC K BR AKE M D P (b) BR AKE STO P M D P (c) STO P ZL Timing Chart 1-10 CAV-W mode LPWR = 1, LPWR2 = 0 KIC K M D P H (a) KIC K BR AKE M D P (b) BR AKE Z STO P M D P (c) STO P Z

– 81 – CXD3027R Timing Chart 1-14 CAV-W mode EPWM = LPWR = 0, LPWR2 = 0 M D P Acceleration Z D eceleration 264kH z 3.8µs Timing Chart 1-11 CLV-N mode LPWR = 0, LPWR2 = 0 M D P Acceleration Z D eceleration 132kH z 7.6µs n • 236 (ns) n = 0 to 31 Timing Chart 1-12 CLV-W mode LPWR = 0, LPWR2 = 0 M D P Acceleration Z D eceleration 264kH z 3.8µs Timing Chart 1-13 CLV-W mode LPWR = 1, LPWR2 = 0 M D P Acceleration Z264kH z 3.8µs The BR AKE pulse is m asked w hen LPW R = 1. Timing Chart 1-15 CAV-W mode EPWM = 0, LPWR = 1, LPWR2 = 0 M D P Acceleration Z264kH z 3.8µs The BR AKE pulse is m asked w hen LPW R = 1.

– 82 – CXD3027R Timing Chart 1-16 CAV-W mode EPWM = 1, LPWR = 0, LPWR2 = 0 PW M I M D P H L H L Acceleration D eceleration Timing Chart 1-17 CAV-W mode EPWM = LPWR = 1, LPWR2 = 0 PW M I M D P H L H Z Acceleration The BR AKE pulse is m asked w hen LPW R = 1. Binary output from MDP and MDS pins ($AF MDPOUTSL1 = 1, MDPOUTSL0 = 0) Timing Chart 1-18 CLV-N mode LPWR = 0, LPWR2 = 0 KIC K M D S M D P H (a) KIC K BR AKE M D S M D P (b) BR AKE STO P M D S M D P (c) STO P L H L L L H Timing Chart 1-19 CLV-W mode (when following the spindle rotational velocity) LPWR = 0, LPWR2 = 0 KIC K M D S M D P H (a) KIC K BR AKE M D S M D P (b) BR AKE STO P M D S M D P (c) STO P L H L L L H

– 83 – CXD3027R Timing Chart 1-20 CLV-W mode (when following the spindle rotational velocity)LPWR = 1, LPWR2 = 0 KIC K M D S M D P H BR AKE M D S M D P STO P M D S M D P L LL H Timing Chart 1-21 CAV-W mode LPWR = 0, LPWR2 = 0 KIC K M D S M D P H (a) KIC K H BR AKE M D S M D P (b) BR AKE STO P M D S M D P (c) STO P L L H Timing Chart 1-22 CAV-W mode LPWR = 1, LPWR2 = 0 KIC K M D S M D P H (a) KIC K BR AKE M D S M D P (b) BR AKE STO P M D S M D P (c) STO P LL H

– 84 – CXD3027R Timing Chart 1-23 CLV-N mode LPWR = 0, LPWR2 = 0 M D S M D P Acceleration D eceleration 132kH z 7.6µs n • 236 (ns) n = 0 to 31 O utput w aveform s w ith D C LV = 1 Timing Chart 1-24 CLV-W mode LPWR = 0, LPWR2 = 0 M D S M D P Acceleration L D eceleration 264kH z 3.8µs O utput w aveform s w ith D C LV = 1 Timing Chart 1-25 CLV-W mode LPWR = 1, LPWR2 = 0 M D S M D P Acceleration L 264kH z 3.8µs O utput w aveform s w ith D C LV = 1 The BR AKE pulse is m asked w hen LPW R = 1. H Timing Chart 1-26 CAV-W mode EPWM = 0, LPWR = 0, LPWR2 = 0 M D P Acceleration L D eceleration 264kH z 3.8µs M D S L

– 85 – CXD3027R Timing Chart 1-27 CAV-W mode EPWM = 0, LPWR=1, LPWR2 = 0 M D P Acceleration L 264kH z 3.8µs The BR AKE pulse is m asked w hen LPW R = 1. M D S H Timing Chart 1-28 CAV-W mode EPWM = 1, LPWR = 0, LPWR2 = 0 PW M I M D P H L H L Acceleration D eceleration M D S H Timing Chart 1-29 CAV-W mode EPWM = 1, LPWR = 1, LPWR2 = 0 PW M I H L M D P H Acceleration M D S H

– 86 – CXD3027R Timing Chart 1-30 CLV-W mode (when following the spindle rotational velocity)LPWR = 0, LPWR2 = 1 KIC K M D S M D P H (a) KIC K BR AKE M D S M D P (b) BR AKE STO P M D S M D P (c) STO P Z H Z L Z H Timing Chart 1-31 CLV-W mode (when following the spindle rotational velocity) LPWR = 1, LPWR2 = 1 KIC K M D S M D P H BR AKE M D S M D P STO P M D S M D PZ ZZ H (a) KIC K (b) BR AKE (c) STO P Timing Chart 1-32 CAV-W mode LPWR = 0, LPWR2 = 1 KIC K M D S M D P H (a) KIC K H BR AKE M D S M D P (b) BR AKE STO P M D S M D P (c) STO P Z L H Timing Chart 1-33 CAV-W mode LPWR = 1, LPWR2 = 1 KIC K M D S M D P H (a) KIC K BR AKE M D S M D P (b) BR AKE STO P M D S M D P (c) STO P ZZ H

– 87 – CXD3027R Timing Chart 1-34 CLV-W mode LPWR = 0, LPWR2 = 1 M D S M D P Acceleration Z D eceleration 264kH z 3.8µs O utput w aveform s w ith D C LV = 1 Timing Chart 1-35 CLV-W mode LPWR = 1, LPWR2 = 1 M D S M D P Acceleration Z264kH z 3.8µs O utput w aveform s w ith D C LV = 1 The BR AKE pulse is m asked w hen LPW R = 1. H Timing Chart 1-36 CAV-W mode EPWM = 0, LPWR = 0, LPWR2 = 1 M D P Acceleration Z D eceleration 264kH z 3.8µs M D S L

– 88 – CXD3027R Timing Chart 1-37 CAV-W mode EPWM = 0, LPWR=1, LPWR2 = 1 M D P Acceleration Z 264kH z 3.8µs The BR AKE pulse is m asked w hen LPW R = 1. M D S H Timing Chart 1-38 CAV-W mode EPWM = 1, LPWR = 0, LPWR2 = 1 PW M I M D P H L H L Acceleration D eceleration M D S H Timing Chart 1-39 CAV-W mode EPWM = 1, LPWR = 1, LPWR2 = 1 PW M I H L M D P H Acceleration M D S H Z

– 89 – CXD3027R [2] Subcode Interface There are two methods for reading out a subcode externally. The 8-bit subcodes P to W can be read out from SBSO by inputting EXCK. The subcode-Q can be read out after checking CRC of the 80 bits in the subcode frame. The subcode-Q can be read out from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR comes correctly and CRCF is high. §2-1. P to W Subcode Readout Data can be read out by inputting EXCK immediately after WFCK falls. (See Timing Chart 2-1.) §2-2. 80-bit Subcode-Q Readout Fig. 2-2 shows the peripheral block of the 80-bit subcode-Q register.

First, subcode-Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check circuit.
96-bit subcode-Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, 80 bits are loaded into the parallel/serial register. When SQSO goes high after SCOR is output, the CPU determines that new data (which passed the CRC check) has been loaded.
When the 80-bit data is loaded, the order of the MSB and LSB is inverted within each byte. As a result, although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first.
Once the 80-bit data load is confirmed, SQCK is input so that the data can be read. The SQCK input is detected, and the retriggerable monostable multivibrator is reset while the input is low.
The retriggerable monostable multivibrator has a time constant from 270 to 400µs. When the duration when SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval, the serial/parallel register is not loaded into the parallel/serial register.
While the monostable multivibrator is being reset, data cannot be loaded in the peak detection parallel/serial register or the 80-bit parallel/serial register. In other words, while reading out with a clock cycle shorter than this time constant, these registers will not be rewritten by CRCOK and others.
The previously mentioned peak detection register can be connected to the shift-in of the 80-bit parallel/serial register. For ring control 1, input and output are shorted during peak meter and level meter modes. For ring control 2, input and output are shorted during peak meter mode. This is because the register is reset with each readout in level meter mode, and to prevent readout destruction in peak meter mode. As a result, the 96-bit clock must be input in peak meter mode.
The absolute time after peak is stored in the memory in peak meter mode as noted in "Description of peak meter mode" on page 49. See Timing Chart 2-3.
The clock is input from the SQCK pin to perform these operations. The high and low intervals of the clock should be between 750ns and 120µs.

– 90 – CXD3027R Timing Chart 2-1 Internal PLL clock 4.3218 ± ΔM H z W FC K SC O R EXC K SBSO 750ns m ax S0 • S1 Q R W FC K SC O R EXC K SBSO S0•S1 Q R S T U V W S0•S1 P1 Q R S T U V W P1 P2 P3 Sam e Sam e

– 91 – CXD3027R Block Diagram 2-2 888888888 O rder inversion Peak detection LO AD C O N TR O L R ing control 2 C R C F M ix M onostable m ultivibratorC R C CABS tim e load control for peak value 16-bit P/S registerR ing control 1 SO SI SQ SO SQ C KSH IFTSH IFT SUBQ LD LD LD LD LD LD LD LD SO H G F E D C B A A B C D E F G H SI 80-bit P/S R egister 80-bit S/P R egister (AFR AM ) (ASEC ) (AM IN ) AD D R S C TR L SINSU BQ

– 92 – CXD3027R Timing Chart 2-3 1 2 3 91 92 93 94 95 96 97 98 W FC K SC O R SQ SO SQ C K M onostable m ultivibrator (Internal) C R C F1 D eterm ined by m ode C R C F2 80 or 96 clocks R egister load forbidder 270 to 400µs w hen SQ C K = high. 750ns to 120µs 300ns m ax C R C F AD R 0 AD R 1 AD R 2 AD R 3 C TL0 C TL1 C TL2 C TL3 SQ C K SQ SO 1 2 3 C R C F1

– 93 – CXD3027R Timing Chart 2-4 Exam ple: $802000 latch Set SQ C K high during this interval. Internal signal latch PER 0 PER 1 PER 2 PER 3 PER 4 PER 5 PER 6 PER 7 C 1F0 C 1F1 C 1F2 C 2F0 C 2F1 C 2F2 FO K G FS LO C K EM PH 750ns or m oreXLAT SQ C K SQ SO ALO C K VF0 VF1 VF2 VF3 VF4 VF5 VF6 VF9VF7 VF8 Signal PER0 to PER7 FOK GFS LOCK EMPH ALOCK VF0 to VF9 RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB. Focus OK. High when the frame sync and the insertion protection timing match. GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low. High when the playback disc has emphasis. GFS is sampled at 460Hz; when GFS is high eight consecutive samples, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low. Used in CAV-W mode. The result obtained by measuring the rotational velocity of the disc. (See Timing Chart 2-5.) VF0 = LSB, VF9 = MSB. No C1 errors; C1 pointer reset One C1 error corrected; C1 pointer reset No C1 errors; C1 pointer set One C1 error corrected; C1 pointer set Two C1 errors corrected; C1 pointer set C1 correction impossible; C1 pointer set C1F1 C1F0 Description C2F2 No C2 errors; C2 pointer reset One C2 error corrected; C2 pointer reset Two C2 errors corrected; C2 pointer reset Three C2 errors corrected; C2 pointer reset Four C2 errors corrected; C2 pointer reset C2 correction impossible; C1 pointer copy C2 correction impossible; C2 pointer set C2F1 C2F0 Description

– 94 – CXD3027R Timing Chart 2-5 M easurem ent interval (approxim ately 3.8µs) R eference w indow (132.2kH z) M easurem ent pulse (V16M /2) M easurem ent counter VF0 to VF9 Load m The relative velocity of the disc can be obtained with the following equation. R = (R: Relative velocity, m: Measurement results) VF0 to VF9 is the result obtained by counting V16M/2 pulses while the reference signal (132.2kHz) generated from XTAL (XTAI, XTAO) (384Fs) is high. This value is 31 when the disc is rotating at normal speed and 63 when it is rotating at double speed (when DSPB is low). m + 1

– 95 – CXD3027R Timing Chart 2-6 18 17C 1 M SB 19 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0537005370 C 1 error rate C 2 error rate XLAT SQ C K SQ SO

– 96 – CXD3027R [3] Description of Modes This LSI has three basic operating modes using a combination of spindle control and the PLL. The operations for each mode are described below. §3-1. CLV-N Mode This mode is compatible with the CXD2510Q, and operation is the same as for conventional control. The PLL capture range is ±150kHz. §3-2. CLV-W Mode This is the wide capture range mode. This mode allows the conventional PLL to follow the rotational velocity of the disc. This rotational following control uses the built-in VCO2. The spindle is the same CLV servo as for the conventional series. Operation using the built-in VCO2 is described below. When starting to rotate the disc and/or speeding up to the lock range from the condition where the disc is stopped, CAV-W mode should be used. Specifically, first send $E665X to set CAV-W mode and kick the disc, then send $E60CX to set CLV-W mode if ALOCK is high, which can be read out serially from the SQSO pin. CLV-W mode can be used while ALOCK is high. The microcomputer monitors the serial data output, and must return the operation to the speed adjusting state (CAV-W mode) when ALOCK becomes low. The control flow according to the microcomputer software in CLV-W mode is shown in Fig. 3-2. In CLV-W mode (normal), low power consumption is achieved by setting LPWR high. Control was formerly performed by applying acceleration and deceleration pulses to the spindle motor. However, when LPWR is set high, deceleration pulses are not output, thereby achieving low power consumption mode. Note) The capture range for this mode is theoretically up to the signal processing limit. §3-3. CAV-W Mode This is CAV mode. In this mode, the external clock is fixed and it is possible to control the spindle to the desired rotational velocity. The rotational velocity is determined by the VP0 to VP7 setting values or the external PWM. When controlling the spindle with VP0 to VP7, setting CAV-W mode with the $E665X command and controlling VP0 to VP7 with the $DX commands allows the rotational velocity to be varied from low speed to quadruple speed. (See "$DX commands".) When controlling the spindle with the external PWM, the PWMI pin is binary input which becomes KICK during high intervals and BRAKE during low intervals. The microcomputer can know the rotational velocity using the internal master clock frequency as the parameter. With XTAL (XTAI, XTAO) (384Fs) as the reference frequency, the result after measuring the high interval by the internal master clock is output in 10 bits (VP0 to VP9) from the new CPU interface. These measurement results are 31 when the disc is rotating at normal speed or 127 when it is rotating at quadruple speed. These values match those of the 256 – n for control with VP0 to VP7. (See Table 2-5 and Fig. 2-6.) In CAV-W mode, the spindle is set to the desired rotational velocity and the operation speed for the entire system follows this rotational velocity. Therefore, the cycles for the Fs system clock, PCM data and all other output signals from this LSI change according to the rotational velocity of the disc. Note) The capture range for this mode is theoretically up to the signal processing limit. Note) Set FLFC to 1 for this mode

– 97 – CXD3027R §3-4. VCO-C Mode This is VCO control mode. In this mode, the oscillation frequency of the internal master clock (VCLK) can be controlled by setting $D commands VP0 to VP7 and VPCTL0, 1. The VCLK oscillation frequency can be expressed by the following equation. VCLK = The VCO1 oscillation frequency is determined by VCLK. The VCO1 frequency can be expressed by the following equation.

When DSPB = 0 VCO1 = VCLK ·
When DSPB = 1 VCO1 = VCLK · 1 (256 – n) n: VP0 to VP7 setting value 1: VPCTL0, 1 setting value

– 98 – CXD3027R C AV-W C LVS C LV-W C LVP R otational velocity Target speed O peration m ode Spindle m ode Tim e KIC K LO C K ALO C K Fig. 3-1. Disc Stop to Regular Playback in CLV-W Mode CLV-W Mode N O YES KIC K $E8000 M ute O FF $A00XXXX ALO C K = H ? N O YES ALO C K = L ? C LV-W M O D E STAR T C AV-W $E665X (C LVA) C LV-W $E60C X (C LVA) (W FC K PLL) Fig. 3-2. CLV-W Mode Flow Chart

– 99 – CXD3027R VCO-C Mode R ? (H ow m any m inutes of absolute tim e?) Access STAR T Transfer $E00510 (C alculate n) Transfer $D X XX Track Jum p Subroutine Transfer $E66500 Access EN D W hat is the playback speed w hen access ends? C alculate VP0 to VP7. Sw itch to VC O control m ode. EPW M = SPD C = IC AP = SFSL = VC 2C = LPW R = 0 H IFC = VPO N = 1 Sw itch to norm al-speed playback m ode. EPW M = SFSL = VC 2C = LPW R = 0 SPD C = IC AP = H IFC = VPO N = 1 Transfer VP0 to VP7. ( corresponds to VP0 to VP7.) Fig. 3-3. Access Flow Chart Using VCO Control

– 100 – CXD3027R [4] Description of other functions §4-1. Channel Clock Recovery by Digital PLL Circuit

The channel clock is necessary for demodulating the EFM signal regenerated by the optical system. Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to 11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a result, T, that is the channel clock, is necessary. In an actual player, a PLL is necessary to recover the channel clock because the fluctuation in the spindle rotation alters the width of the EFM signal pulses. The block diagram of this PLL is shown in Fig. 4-1. The CXD3027R has a built-in three-stage PLL.
The first-stage PLL is a wide-band PLL. When using the internal VCO2, an external LPF is necessary. The output of this first-stage PLL is used as a reference for all clocks within the LSI.
The second-stage PLL generates the high-frequency clock needed by the third-stage digital PLL.
The third-stage PLL is a digital PLL that recovers the actual channel clock.
The digital PLL in CLV-N mode has a secondary loop, and is controlled by the primary loop (phase) and the secondary loop (frequency). When FLFC = 1, the secondary loop can be turned off. High frequency components such as 3T and 4T may contain deviations. In such cases, turning the secondary loop off yields better playability. However, in this case the capture range becomes ±50kHz.
A new digital PLL has been provided for CLV-W mode to follow the rotational velocity of the disc in addition to the conventional secondary loop.

– 101 – CXD3027R Block Diagram 4-1 XTSL 1/2 1/32 1/n1/2 M icrocom puter control n = 1 to 256 (VP7 to VP0) 1/K (KSL1, KSL0) C LV-W C AV-W Spindle rotation inform ation C LV-N C LV-W C AV-W /C LV-N Phase com parator Selector LPF 2/1 M U X VPO N 1/M 1/N VC O SEL2 VC O 2 Phase com parator VC O 1 VC O SEL1 1/K (KSL3, KSL2) D igital PLL R FPLL VPC O VC TL PC O FILI FILO C LTV XTAI C lock input 1/l l = 1, 2, 3, 4 (VPC TL0, VPC TL1)

– 102 – CXD3027R §4-2. Frame sync protection

In normal-speed playback, a frame sync is recorded approximately every 136µs (7.35kHz). This signal is used as a reference to recognize the data within a frame. Conversely, if the frame sync cannot be recognized, the data is processed as error data because the data cannot be recognized. As a result, recognizing the frame sync properly is extremely important for improving playability.
In the CXD3027R, window protection and forward protection/backward protection have been adopted for frame sync protection. These functions achieve very powerful frame sync protection. There are two window widths; one for cases where a rotational disturbance affects the player and the other for cases where there is no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is set to 13*, and the backward protection counter to 3*. Concretely, when the frame sync is being played back normally and then cannot be detected due to scratches, etc., a maximum of 13 frames are inserted. If the frame sync cannot be detected for 13 frames or more, the window opens to resynchronize the frame sync. In addition, immediately after the window opens and the resynchronization is executed, if a proper frame sync cannot be detected within 3 frames, the window opens immediately. * Default values. These values can be set as desired by $C commands SFP3 to SFP0 and SRP3 to SRP0. §4-3. Error Correction
In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the code is created with 28-byte information and 4-byte C1 parity. For C2 correction, the code is created with 24-byte information and 4-byte parity. Both C1 and C2 are Reed-Solomon codes with a minimum distance of 5.
The CXD3027R uses refined super strategy to achieve double correction for C1 and quadruple correction for C2.
In addition, to prevent C2 miscorrection, a C1 pointer is attached to data after C1 correction according to the C1 error status, the playback status of the EFM signal and the operating status of the player.
The correction status can be monitored externally. See Table 4-2.
When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held or an average value interpolation was made for the data. MNT3 No C1 errors; C1 pointer reset One C1 error corrected; C1 pointer reset No C1 errors; C1 pointer set One C1 error corrected; C1 pointer set Two C1 errors corrected; C1 pointer set C1 correction impossible; C1 pointer set No C2 errors; C2 pointer reset One C2 error corrected; C2 pointer reset Two C2 errors corrected; C2 pointer reset Three C2 errors corrected;C2 pointer reset Four C2 errors corrected; C2 pointer reset C2 correction impossible; C1 pointer copy C2 correction impossible; C2 pointer set MNT2 MNT1 MNT0 Description Table 4-2.

– 103 – CXD3027R Timing Chart 4-3 Normal-speed PB 400 to 500ns RFCK MNT3 MNT1 MNT0 t = Dependent on error condition C1 correction C2 correction StrobeStrobe MNT2 §4-4. DA Interface

The DA interface supports the 48-bit slot interface. 48-bit slot interface This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is high, the data is for the left channel. The output format from the bass boost block supports 18 bits and 20 bits in addition to 16 bits.

– 104 – CXD3027R Timing Chart 4-4 LR C K (44.1K) BC K (2.12M ) W D C K PC M D LR C K (88.2K) BC K (4.23M ) W D C K PC M D 48-bit Slot N orm al-Speed Playback 1 24 R 0 Lch M SB (15) L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R ch M SB Lch M SB (15) R ch M SB 2 3 4 5 6 7 8 9 10 11 12 48-bit Slot D ouble-Speed Playback 1 2 L0R 0

– 105 – CXD3027R Timing Chart 4-5 (DAC output selected) LR C K (44.1K) BC K (2.12M ) W D C K PC M D SD SL1 = 1, O BIT1 = 0, O BIT0 = 1 1 24 R 0 Lch M SB (17) L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R ch M SB 2 3 4 5 6 7 8 9 10 11 12 SD SL = 1, O BIT1 = 0, O BIT0 = 0 PC M D R 0 Lch M SB (19) L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R ch M SB L15L16 L15L16L17L18

– 106 – CXD3027R §4-5. Digital Out There are three Digital Out: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. The CXD3027R supports type 2 form 1. This LSI supports two kinds of Digital Out generation methods; generation from the PCM data read out from the disc, and generation from the DA interface inputs (PCMDI, LRCKI, BCKI). §4-5-1. Digital Out from PCM Data The Digital Out is generated from the PCM data which is read out from the disc. The clock accuracy of the channel status is automatically set to level IIwhen the crystal clock is used and to level IIIin CAV-W mode or variable pitch mode. In addition, the subcode-Q data matched twice in succession with CRC check are input to the initial 4 bits (bits 0 to 3). DOUT is output when the crystal is 34MHz and XTSL is high in CLV-N or CLV-W mode with DSPB = 1. Therefore, DOUT is set to off by setting the $B command MD2 to 0. 0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0 ID 0 ID 1 C O PY Em ph 0 0 0 0 1 0 0 0 0 0 0 0 From sub Q0 176 Subcode-Q control bits that m atched tw ice in succession w ith C R C O K D igital O ut C bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VPO N or VAR IO N : 1 X'tal: 0 bits 0 to 3 bit 29 Table 4-5-1.

– 107 – CXD3027R §4-5-2. Digital Out from DA Interface Input The Digital Out is generated from the DA interface input. Validity Flag and User Data The Validity Flag is fixed to 0. The User Data is fixed to 0 or it can be output according to the format by setting 0 data. For the Q data, first set the Q1 to Q80 data using the $A90 to $A99 commands, then the set data can be output according to the digital interface format using the $A9A command. In addition, CRC operations are performed internally on the Q81 to Q96 data and then this data is output. The data is output in the order shown in Table 4-5-2. The setting flow is shown in Figs. 4-5 (a) and 4-5 (b). Fig. 4-5 (a) shows the case when changing all the data, and Fig. 4-5 (b) the case when changing the INDEX, movement time and absolute time. Table 4-5-2. 1164 Q96 0 1 2 3 4 5 6 7 8 9 10 11

– 108 – CXD3027R Channel Status Data For the Channel Status Data, bits 0, 6 and 7 are fixed to 0. The following items can be set by bits 1, 2, 3 and 8. a) Digital data/audio data b) Digital copy enabled/prohibited c) With/without emphasis d) Category code (2 types possible) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 A/D

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Table 4-5-3. Note)In this method, DOUT can be set to off by setting $B command MD2 to 0 and $34A command DOUT EN to 0.

– 109 – CXD3027R STAR T $A900∗∗ $A990∗∗ $A9A0F0 (D O N = H , D U P1 = H , D U P0 = H ) Set the subcode-Q inform ation. Input w ith BC D code. W ait tim e 13.3m s O utput the subcode-Q inform ation. Start the m ovem ent tim e and absolute tim e counts. $A9A040 (D O N = L, D U P1 = L, D U P0 = L) Stop subcode-Q inform ation output to D -out. Stop the m ovem ent tim e and absolute tim e counts. $A900∗∗ $A990∗∗ W ait tim e 13.3m s Input $A9A0F0 (D O N = H , D U P1 = H , D U P0 = H ) (O utput the changed subcode-Q inform ation.) Set the subcode-Q inform ation. Input w ith BC D code. Fig. 4-5(a). Flow Chart for Settings Using Q Data STAR T $A900∗∗ $A990∗∗ $A9A0F0 (D O N = H , D U P1 = H , D U P0 = H ) Set the subcode-Q inform ation. Input w ith BC D code. W ait tim e 13.3m s O utput the subcode-Q inform ation. Start the m ovem ent tim e and absolute tim e counts. $A9A0C 8 (D U P1 = L, D U P0 = L, D LD = H ) (Stop the m ovem ent tim e and absolute tim e counts.) $A920∗∗ Index $A930∗∗ : M ovem ent tim e $A950∗∗ $A970∗∗ : Absolute tim e $A990∗∗ W ait tim e 13.3m s Input $A9A0F0 (D U P1 = H , D U P0 = H , D LD = L) (O utput the changed subcode-Q inform ation.) N ote) The IN D EX, m ovem ent and absolute tim e data output to D -out w hile m aking the settings is all 0. Fig. 4-5(b). Flow Chart for Settings Using Q Data

– 110 – CXD3027R Digital Audio Data Input The input signal of the digital audio data is input through the DAC input signal pins PCMDI, LRCKI and BCKI. The input format supports the 48-bit slot, MSB first. Mute Function By setting the command bit DOUT_DMUT to 1, all the audio data portions in the Digital Out output can be set to 0 without altering the Channel Status Data. Input/Output Synchronization Circuit In normal operation, the DAC automatically synchronizes with the input LRCK. However, synchronization may not be achieved when the input data contains much jitter or during power-on, etc. In such cases, internal operation should be forcibly resynchronized by setting the $34A command DOUT WOD to 1. Forced synchronization is also required when the operating frequency is changed such as switching between CLV and CAV, etc. Be sure to set DOUT WOD to 0 and then to 1 for forced resynchronization. * Resynchronization clears the internal frame counter so that the count starts over from frame 0 after the resynchronization processing. In cases where automatic resynchronization processing is not desirable or the user wants to do it manually, set the $34A command WINEN to 0 to disable the resynchronization circuit. DOUT Circuit Clock System For the DOUT block, the master clock is set using the clock control command MCSL ($A) employed by the DAC block. Set MCSL to 1 for 768fs, and to 0 for 384fs.

– 111 – CXD3027R LR C K BC KI PC M D I 48-bit slot 1 24 R 0 Lch M SB (15) L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R ch M SB 2 3 4 5 6 7 8 9 10 11 12 DOUT Block Input Timing Chart

– 112 – CXD3027R §4-6. Servo Auto Sequence This function performs a series of controls, including auto focus and track jumps. When the auto sequence command is received from the CPU, auto focus, 1-track jump, 2N-track jump, fine search and M-track move are executed automatically. The servo block operates according to the built-in program during the auto sequence execution (when XBUSY = low), so that commands from the CPU, that is $0, 1, 2 and 3 commands, are not accepted. ($4 to E commands are accepted.) In addition, when using the auto sequence, turn the A.SEQ ON-OFF of register 9 on. When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of 100µs after that point. This is to prevent the transfer of erroneous data to the servo when XBUSY changes from low to high by the monostable multivibrator, which is reset by CLOK being low (when XBUSY is low). In addition, a MAX timer is built into this LSI as a countermeasure against abnormal operation due to external disturbances, etc. When the auto sequence command is sent from the CPU, this command assumes a $4XY format, in which X specifies the command and Y sets the MAX timer value and timer range. If the executed auto sequence command does not terminate within the set timer value, the auto sequence is interrupted (like $40). See "[1] $4X commands" concerning the timer value and range. Also, the MAX timer is invalidated by inputting $4X0. Although this command is explained in the format of $4X in the following command descriptions, the timer value and timer range are actually sent together from the CPU. (a) Auto focus ($47) Focus search-up is performed, FOK and FZC are checked, and the focus servo is turned on. If $47 is received from the CPU, the focus servo is turned on according to Fig. 4-6. The auto focus starts with focus search-up, and note that the pickup should be lowered beforehand (focus search-down). In addition, blind E of register 5 is used to eliminate FZC chattering. Concretely, the focus servo is turned on at the falling edge of FZC after FZC has been continuously high for a longer time than E. (b) Track jump 1, 10 and 2N-track jumps are performed respectively. Always use this when the focus, tracking, and sled servos are on. Note that tracking gain-up and braking-on ($17) should be sent beforehand because they are not involved in this sequence.

1-track jump When $48 ($49 for REV) is received from the CPU, a FWD (REV) 1-track jump is performed in accordance with Fig. 4-7. Set blind A and brake B with register 5.
10-track jump When $4A ($4B for REV) is received from the CPU, a FWD (REV) 10-track jump is performed in accordance with Fig. 4-8. The principal difference from the 1-track jump is to kick the sled. In addition, after kicking the actuator, when 5 tracks have been counted through COUT, the brake is applied to the actuator. Then, when the actuator speed is found to have slowed up enough (determined by the COUT cycle becoming longer than the overflow C set with register 5), the tracking and sled servos are turned on.

– 113 – CXD3027R

2N-track jump When $4C ($4D for REV) is received from the CPU, a FWD (REV) 2N-track jump is performed in accordance with Fig. 4-9. The track jump count N is set with register 7. Although N can be set to 2 16 tracks, note that the setting is actually limited by the actuator. COUT is used for counting the number of jumps when N is less than 16, and MIRR is used when N is 16 or more. Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is that after the tracking servo is turned on, the sled continues to move only for "D", set with register 6.
Fine search When $44 ($45 for REV) is received from the CPU, a FWD (REV) fine search (N-track jump) is performed in accordance with Fig. 4-10. The differences from a 2N-track jump are that a higher precision is achieved by controlling the traverse speed, and a longer distance jump can be performed by controlling the sled. The track jump count N is set with register 7. N can be set to 2 16 tracks. After kicking the actuator and sled, the traverse speed is controlled based on the overflow G. Set kick D and F with register 6 and overflow G with register 5. Also, sled speed control during traverse can be turned off by causing COMP to fall. Set the number of tracks during which COMP falls with register B. After N tracks have been counted through COUT, the brake is applied to the actuator and sled. (This is performed by turning on the tracking servo for the actuator, and by kicking the sled in the opposite direction during the time for kick D set with register 6.) Then, the tracking and sled servos are turned on. Set overflow G to the speed required to slow up just before the track jump terminates. (The speed should be such that it will come on-track when the tracking servo turns on at the termination of the track jump.) For example, set the target track count N – a for the traverse monitor counter which is set with register B, and COMP will be monitored. When the falling edge of this COMP is detected, overflow G can be set again.
M-track move When $4E ($4F for REV) is received from the CPU, a FWD (REV) M-track move is performed in accordance with Fig. 4-11. M can be set to 2 16 tracks. Like the 2N-track jump, COUT is used for counting the number of moves when M is less than 16, and MIRR is used when M is 16 or more. The M-track move is executed by moving only the sled, and is therefore suited for moving across several thousand to several ten-thousand tracks. In addition, the track and sled servos are turned off after M tracks have been counted through COUT or MIRR unlike for the other jumps. Transfer $25 from the microcomputer after the actuator has stabilized.

– 114 – CXD3027R Auto focus Focus search up FO K = H N O YES FZC = H N O YES FZC = L N O YES EN D Focus servo O N C heck w hether FZC is continuously high for the period of tim e E set w ith register 5. Fig. 4-6-(a). Auto Focus Flow Chart XLAT $47 Latch $03 Blind E $08 FO K FZC BU SY C om m and for D SSP block Fig. 4-6-(b). Auto Focus Timing Chart

– 115 – CXD3027R

1 Track

(Blind A) C O U T = Track R EV kick W AIT (Brake B) Track, sled servo O N (FW D kick for R EV jum p) (R EV kick for R EV jum p) Fig. 4-7-(a). 1-Track Jump Flow Chart $48 (R EV = $49) Latch $28 ($2C ) Blind A Brake B $2C ($28) $25 BU SY C O U T XLAT C om m and for D SSP block Fig. 4-7-(b). 1-Track Jump Timing Chart

– 116 – CXD3027R

10 Track

Track, sled FW D kick W AIT (Blind A) C O U T = 5 ? Track, R EV kick Track, sled servo O N C hecks w hether the C O U T cycle is longer than overflow C . N O YES C = O verflow ? (C ounts C O U T × 5) Fig. 4-8-(a). 10-Track Jump Flow Chart C O U T $4A (R EV = $4B) Latch Blind A $2A ($2F) C O U T 5 counts $2E ($2B) O verflow C $25 XLAT BU SY C om m and for D SSP block Fig. 4-8-(b). 10-Track Jump Timing Chart

– 117 – CXD3027R 2N Track N O YES EN D Track, sled FW D kick W AIT (Blind A) C O U T (M IR R ) = N Track R EV kick Track servo O N N O YES C = O verflow W AIT (Kick D ) Sled servo O N C ounts C O U T for the first 16 tim es and M IR R for m ore tim es. Fig. 4-9-(a). 2N-Track Jump Flow Chart XLAT Blind A $2A ($2F) C O U T (M IR R ) N counts $2E ($2B) O verflow C Kick D $26 ($27) $25 $4C (R EV = $4D ) Latch C O U T (M IR R ) BU SY C om m and for D SSP block Fig. 4-9-(b). 2N-Track Jump Timing Chart

– 118 – CXD3027R Track Servo O N Sled FW D Kick Fine Search W AIT (Kick D ) Track Sled FW D Kick W AIT (Kick F) Traverse Speed C trl (O verflow G ) C O U T = N ? Track Servo O N Sled R EV Kick W AIT (Kick D ) Track Sled Servo O N EN D YES N O Fig. 4-10-(a). Fine Search Flow Chart Traverse Speed C ontrol (O verflow G ) C O U T N counts Kick FKick D $26 ($27) $2A ($2F) $27 ($26) $25 $44 (R EV = $45) latch XLAT C O U T Kick D BU SY C om m and for D SSP block Fig. 4-10-(b). Fine Search Timing Chart

– 119 – CXD3027R M Track M ove N O YES EN D Track Servo O FF Sled FW D Kick W AIT (Blind A) C O U T (M IR R ) = M Track, Sled Servo O FF C ounts C O U T for M < 16. C ounts M IR R for M ≥ 16. Fig. 4-11-(a). M-Track Move Flow Chart XLAT Blind A $22 ($23) C O U T (M IR R ) M counts $20 $4E (R EV = $4F) Latch C O U T (M IR R ) BU SY C om m and for D SSP block Fig. 4-11-(b). M-Track Move Timing Chart

– 120 – CXD3027R §4-7. Digital CLV Fig. 4-12 shows the block diagram. Digital CLV outputs MDS error and MDP error signals with PWM, with the sampling frequency increased up to 130kHz during normal-speed playback in CLVS, CLVP and other modes. In addition, the digital spindle servo gain is variable. M D P D igital C LV C LVS U /D M D S Error M D P Error C LV P/S M easure M easure 2/1 M U X O ver Sam pling Filter-1 G ain M D S M ux C LV P/S O ver Sam pling Filter-2 N oise Shape M odulationKIC K, BR AKE, STO P M ode Select G ain D C LV G ain M D P LPW R PW M I Fig. 4-12. Block Diagram CLVS U/D: Up/down signal from CLVS servo MDS error:Frequency error for CLVP servo MDP error:Phase error for CLVP servo PWMI: Spindle drive signal from the microcomputer for CAV servo

– 121 – CXD3027R §4-8. CD-DSP Block Playback Speed In the CXD3027R, the following playback modes can be selected through different combinations of the XTAI, XTSL pins, double-speed command (DSPB), VCO1 selection command (VCOSEL1), VCO1 frequency division commands (KSL3, KSL2) and command transfer rate selector (ASHS) in CLV-N or CLV-W mode. Mode XTAI 768Fs 768Fs 768Fs 768Fs 384Fs 384Fs 384Fs XTSL DSPB VCOSEL1 * ASHS Playback speed Error correction*2 C1: double; C2: quadruple C1: double; C2: double C1: double; C2: quadruple C1: double; C2: double C1: double; C2: quadruple C1: double; C2: double C1: double; C2: double 1 Actually, the optimal value should be used together with KSL3 and KSL2. *2 When $8 command ERC4 = 1, C2 is quadruple correction even when DSPB = 1. The playback speed can be varied by setting VP0 to VP7 in CAV-W mode. See "[3] Description of Modes" for details. §4-9. Description of DAC Block and Shock-Proof Memory Controller Block Circuits The CXD3027R inputs data from the CD-DSP block to the DAC block via the shock-proof memory controller block. The data from the shock-proof memory controller block is output externally as bass-boosted data via the DBB circuit. When not using the DAC block, the data from the shock-proof memory controller block can be output directly to the outside of the LSI. Also, when not using the shock-proof memory controller, the data can be input directly from the CD-DSP block to the DAC block. The DAC block output format supports 16, 18 or 20 bits.

– 122 – CXD3027R §4-10. DAC Block Input Timing Fig. 4-13 shows the input timing chart to the DAC block. The CXD3027R can transfer data from the CD-DSP block to the DAC block via an external route. This allows the data to be sent to the DAC block via an audio DSP, etc. N orm al-Speed Playback LR C KI (44.1k) 1 24 PC M D I R 0 Lch M SB (15) L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R M SB PC M D I LR C KI (88.2k) D ouble-Speed Playback R 0 Lch M SB (15) R ch M SB 2 3 4 5 6 7 8 9 10 11 12 1 2 BC KI (4.23M ) BC KI (2.12M ) Fig. 4-13. Input Timing to the DAC Block

– 123 – CXD3027R Attenuation Operation Assuming the attenuation commands X1, X2 and X3, the corresponding audio outputs are Y1, Y2 and Y3 (Y1 > Y3 > Y2). First, the command X1 is sent and then the audio output approaches Y1. When the command X2 is sent before the audio output reaches Y1 (A in the figure), the audio output passes Y1 and approaches Y2. And, when the command X3 is sent before the audio output reaches Y2 (B or C in the figure), the audio output approaches Y3 from the value (B or C in the figure) at that point. A B C 23.2 [m s] – ∞ 000 (H ) 0dB 400 (H ) DAC Block Mute Operation Soft mute Soft mute results and the input data is attenuated to zero when any one of the following conditions is met.

When attenuation data of 000 (h) is set
When $A5 command SMUT is set to 1
When a high signal is input to the SYSM pin Soft m ute on Soft m ute offSoft m ute off 0dB – ∞ dB §4-11. Description of DAC Block Functions Zero Data Detection When the condition where the lower 4 bits of the input data are DC and the remaining upper bits are all 0 or all 1 has continued for about 300ms (16384/44.1kHz), zero data is detected. Zero data detection is performed independently for the left and right channels. Mute flag output The LRMU pin goes active when any one of the following conditions is met. The polarity can be selected by the $A5X command ZDPL.
When zero data is detected
When a high signal is input to the SYSM pin and zero data is detected
When the $A5 command SMUT is set and zero data is detected

– 124 – CXD3027R Zero detection mute Analog mute is applied to the respective channel when $AX command ZMUTA is set to 0 and zero data is detected for the left or right channel. (See "Zero data detection".) When $AX command ZMUTA is set to 0, analog mute is applied even if the mute flag output condition is met. LRCK Synchronization Synchronization is performed at the first rising edge of the LRCK input when reset. After that, synchronization is lost when the LRCK input frequency changes, etc., so resynchronization must be performed. The LRCK input frequency changes when the master clock of the LSI is switched and the playback speed changes such as the following cases.

When the XTSL pin switches between high and low
When the $9 command DSPB setting changes
When the $A4 command MCSL setting changes
When operation switches between CLV mode and CAV mode For resynchronization, set the $A5 command XWOC to 1, wait for one LRCK cycle or more, and then set XWOC to 0. * When setting XWOC to 1, be sure to set the $9X command SYCOF to 0 beforehand. SYCOF When LRCK, PCMD and BCK are connected directly with LRCKI, PCMDI and BCKI, respectively, playback can be performed easily in CAV-W mode by setting the $AX command SYCOF to 1. Normally, the memory proof, etc., is used for playback in CAV-W mode. In CAV-W mode, the LRCK output conforms not to the crystal but to the VCO. Therefore, synchronization is frequently lost. Setting the $AX command SYCOF to 1 ignores the LRCKI input asynchronization, facilitating playback. However, the playback is not perfect because pre-value hold or data skip occurs due to the wow and flutter in the LRCKI input, etc. * Set SYCOF to 0 other than when performing playback in CAV-W mode with LRCK, PCMD and BCK connected directly to LRCKI, PCMDI and BCKI, respectively. Digital High and Bass Boost High and bass boost without external parts is possible using the built-in digital filter. Perform the following operations when turning boost off or when lowering the current boost level. 1.Set $AX command BSTCL to 1. 2.Wait 20ms or more, set the boost level or turn boost off, then set $AX command BSTCL to 0. High-Cut Filter This filter lowers the high-frequency level by approximately 8dB. The frequency response is shown in Fig. 4-14. 0.00 –2.00 –4.00 –6.00 –8.00 10 100 1k 10k Frequency [H z] Gain [dB] Fig. 4-14. High-Cut Filter Frequency Response

– 125 – CXD3027R Compressor, Dynamic High and Bass Boost 1. Frequency Response and I/O Characteristics Fig. 4-15 shows the frequency response for dynamic high boost and bass boost. This figure shows the frequency response for a high boost turnover frequency of 5kHz and a bass boost turnover frequency of 160Hz. The boost level and turnover frequency can be set independently for high boost and bass boost. In addition, all frequencies are lowered by approximately 2dB in order to prevent clipping, so the medium frequencies are –2dB output. The high boost and bass boost levels indicate the relative values from this level. Next, the compressor, high boost and bass boost I/O characteristics are shown in Fig. 4-17. As shown in this figure, the compressor characteristics span all frequencies. In addition, the high boost and bass boost characteristics are for when the input signal is sufficiently higher or lower than the turnover frequency. The boost levels can be set independently. Uth and Lth on the vertical axis are the gain control threshold values, and the desired output value can be taken from the area enclosed by the parallelograms near these levels. The Uth and Lth settings are described hereafter. 20.00 18.00 16.00 14.00 12.00 10.00 8.00 6.00 4.00 2.00 0.00 –2.00 10 100 1k 10k Frequency response [H z] Gain [dB] (4) (3) (2) (1) (1) H BSL1 = 0, H BSL0 = 0, BBSL1 = 0, BBSL0 = 0 (2) H BSL1 = 0, H BSL0 = 1, BBSL1 = 0, BBSL0 = 1 (3) H BSL1 = 1, H BSL0 = 0, BBSL1 = 1, BBSL0 = 0 (4) H BSL1 = 1, H BSL0 = 1, BBSL1 = 1, BBSL0 = 1 Fig. 4-15. Digital Bass Boost Frequency Response

– 126 – CXD3027R 2. Settings When performing dynamic processing, the auditory volume and other characteristics change according to the boost levels and various other settings. The values that can be set by the serial commands and the resulting effects are described below. 2-1. Boost Level The boost level can be set independently for the compressor, high boost and bass boost. Boost level here refers to the maximum boost level when a low level signal is input. The boost level changes over time when a high level signal is input in order to prevent clipping. 2-2. Gain Control Thresholds The gain control thresholds are Uth and Lth. When the level exceeds Uth, the gain is reduced; when the level falls below Lth, the gain is increased. If both Uth and Lth are set to large values, the volume increases and the respective boost effects are emphasized. On the other hand, some sources may be clipped due to the balance with the boost level. These values can be set independently for the compressor and high/bass boost. The same values are shared for high and bass boost. 2-3. Attack Time, Release Time The attack time represents the speed at which the gain is reduced after high level input, and the release time represents the speed at which the gain is increased when the input level suddenly becomes smaller. If these values are set to "fast", the boost effects increase. Like the gain control thresholds, these values can be set independently for the compressor and high/bass boost. 2-4. Envelope Detection Release Time This sets the output signal envelope coefficient used for gain control. When set to "fast", the boost effects increase. This setting is shared by compressor and high/bass boost. High boost Bass boost Attack time Release time Lch Uch +10dB +14dB +18dB +22dB Standard Slow Slow Slow Standard Standard Standard Standard –12dB –12dB –12dB –12dB –1.9dB –1.9dB –1.9dB –1.9dB Table 4-16. Recommended Dynamic Bass and High Boost Settings

– 127 – CXD3027R Input [dB] Lth U th Output [dB] Fig. 4-17. Dynamic Processing I/O Characteristics Compressor High Boost Bass Boost –8.0 –1.9/–0.9 –1.9/–0.9 –23 –12/–4.4 –12/–4.4 4/6/8/10 10/14/18/22 Uth [dB] Lth [dB] Boost level [dB]

– 128 – CXD3027R Analog out C 1 330pF R 3 27k R 1 27k C 2 68pF AO U T1 (2) AIN 1 (2) LO U T1 (2) Vc R 2 27k Fig. 4-18. LPF External Circuit §4-12. LPF Block The CXD3027R contains an initial-stage secondary active LPF with numerous resistors and capacitors and an operational amplifier with reference voltage. The resistors and capacitors are attached externally, allowing the cut-off frequency fc to be determined flexibly. The reference voltage (Vc) is (AV DD – AVSS ) · 0.45. The LPF block application circuit is shown in Fig. 4-18. In this circuit, the cut-off frequency is fc ≈ 40kHz. LPF Block Application Circuit

– 129 – CXD3027R §4-13. Description of Shock-Proof Memory Controller Block Functions §4-13-1. DRAM I/F A 4M DRAM or 16M DRAM can be selected as the external buffer RAM. The 16M DRAM supports either row address 2 12 and column address 210 or row address 211 and column address 211. Refresh is performed by data access, and the refresh cycle is approximately 11.6ms when 4M DRAM is selected, or approximately 46.4ms (2 10 · 212) or 23.2ms (211 · 211) when 16M DRAM is selected. In addition, XRAS-only-refresh is executed 14 times in order to initialize the RAM during power-on reset. Data access to the DRAM is not possible during this period. XR ST XR AS Approxim ately 5.67µs 14 tim es §4-13-2. Switching from Data Through Mode to Shock-Proof The CXD3027R performs refresh by data access. When switching from (1) shock-proof mode to (2) data through mode to (3) shock-proof mode, be sure to reset all of WA, VWA and RA before performing data access for (3). §4-13-3. CPU Serial Data Output Data is read out by setting the XSOEO command low and inputting SQCK. The data contents at the falling edge of the XSOEO command are output from the SQSO pin at the falling edge of SCK. XSO EO SQ C K SQ SO D 1D 0 D 2 D 3 D 4 D 5 D 6 D 7 D 8 D 9 D 10 D 11 Invalid D0: XWPHD Data write to DRAM prohibited signal (low for XFUL + ROF + WRNG) D1: QRCVD Indicates whether XQOK was registered as a defined address after it was sent. (High = registration OK) D2: XEMP Low when the DRAM is empty of valid data. (VWA = RA) D3: AM15 Address monitor; indicates the amount of valid data remaining. D4: AM16 Address monitor; indicates the amount of valid data remaining. D5: AM17 Address monitor; indicates the amount of valid data remaining. D6: AM18 Address monitor; indicates the amount of valid data remaining. D7: AM19 Address monitor; indicates the amount of valid data remaining. D8: AM20 Address monitor; indicates the amount of valid data remaining. D9: AM21 Address monitor; indicates the amount of valid data remaining. D10: XFUL Low when the DRAM is full and there is no write area. D11: ROF High when the DSP RAM has overflowed. Note) When GRSCOR is low, QRCVD is high when data write to the DRAM is enabled, even if a negative pulse is input to XQOK.

– 130 – CXD3027R §4-13-4. Data Linking In order to restart write after PCM data write to the DRAM has been interrupted due to sound skipping or other factors, continuity must be maintained between the data written last and the subsequent data to be written. Conventional systems fix an aim at the data linking point, compare the preceding DRAM reference data with the data read from the disc, and then link the data when matching data is detected. However, when using music software where a fixed pattern is repeated, this system may link the data at an incorrect point. In addition, if pre-value hold or interpolation is performed at the point to be linked, data linking may not be possible at all. In order to eliminate these data linking errors, the CXD3027R generates a crystal accuracy SCOR (= GRSCOR) synchronized to the PCM data to allow data linking along the time axis, thus greatly increasing the data linking accuracy. §4-13-5. Data Processing The CXD3027R accumulates PCM data from the CD-DSP block in an external buffer and then inputs the data to the DAC block in sync with the internally generated Fs system clock. At this time, the PCM data is loaded and read out at the same rate during normal playback, so data does not accumulate in the buffer RAM. Therefore, the loading rate must be increased. This is accomplished by setting the CD-DSP block to double- speed mode and doubling the loading rate until the RAM is full. When the RAM becomes full, data regeneration from the disc stops temporarily and the RAM data is read out to create an empty area, at which point loading is restarted. These operations are then repeated to effectively use the entire area inside the RAM. C D -D SP Shock-Proof D AC 4M D R AM §4-13-6. System Outline (when SLXQOK = 1 and SLXWRE = 1) The addresses for accessing the buffer RAM data consist of a readout address (RA) and a write address (WA). The data to be written is not always correct, and the subcodes, etc. must be constantly checked to make sure the data is correct and there is no sound skipping. The CXD3027R checks subcode-Q using the CPU, and defines the data by inputting a negative pulse to the XQOK pin. This defined address (VWA) is loaded to the internal register and the data between VWA and RA is treated as valid data. WA advances at a speed twice that of RA, and RA is written by WA and read out sequentially in the order registered by VWA. When RA catches up to VWA, there is no more valid data and readout is prohibited (XEMP = low). In addition, when WA catches up to RA, the buffer is full and write is prohibited (XWIH = low). In this manner, write to the RAM is interrupted when the RAM becomes full and there is no write area or when sound skipping caused by scratches, external disturbances or other factors is detected. Data continuity must be ensured in order to restart write. Therefore, the CXD3027R returns to the last defined address, and the CPU accesses the defined address point it sent last (actually the data slightly before that point) and reads the subcode-Q after the rising edge of SCOR. If the subcode-Q matches the last defined address, XWRE is made to fall and write is restarted when GRSCOR comes high within 7ms. Note 1)If XWRE is made to fall when GRSCOR is low, XWIH goes low and the write prohibited state results. Note 2)When GRSCOR is low, VWA is not updated even if a negative pulse is input to XQOK. Therefore, set XQOK high while GRSCOR is low. W A VW A R A Valid data PCM Data Flow (Example for 4M · 1 mode)

– 131 – CXD3027R §4-13-7. Data write (when SLXQOK = 1 and SLXWRE = 1) The PCM data input from the DSP is loaded according to the Fs system clock inputs (BCKI, WDCI and LRCI), and is written sequentially to the external DRAM according to WA when the XWRE pin input goes low and internal write is enabled (XWIH pin output = high). The written data must be checked by some means or other. The CXD3027R assumes data checking with subcode-Q. In this case, the CPU reads subcode-Q triggered by the SCOR signal output from the DSP to determine whether sound skipping occurred. If sound skipping is not detected, the CPU inputs a negative pulse to the XQOK pin during the GRSCOR high interval which comes within 7ms, and the data written to WA thus far is registered to VWA as data without sound skipping. SC O R SU BQ G R SC O R XQ O K N o sound skipping = C R C O K N o sound skipping = C R C N G W A → VW A Write prohibition is determined by the internal status or by an external command. When prohibited by the internal status, the XWIH pin goes low, and this status is established when any one of the following three conditions is met. 1. There is no empty area in the DRAM. XFUL = low 2. The DSP RAM has overflowed. ROF = high 3. XWRE was made to fall when GRSCOR is low.WRNG = high When the XWIH pin goes low due to the above conditions, the CPU must set the XWRE pin high and then the XWIH pin high. After the CPU sends XQOK, it must check whether XQOK was registered as a defined address. This is because if the above conditions arise at the same time XQOK is sent, XQOK becomes invalid and the addresses defined by the CPU and the CXD3027R may not match. Therefore, the XWIH pin output is used as the XQOK recognition signal (QRCVD) while XQOK is low. When QRCVD is high, this indicates that XQOK was correctly registered as a defined address (VWA was updated). When QRCVD is low, this indicates one of the following conditions. 1. Write is prohibited due to the above three conditions. 2. XWRE is high. Regarding condition 2, if XQOK is sent while the XWRE pin is high, WA, VWA and RA are all reset (when GRSCOR is high).

– 132 – CXD3027R §4-13-8. Data Readout (when SLXQOK = 1 and SLXWRE = 1) When data write starts, there is no valid data in the RAM so the XEMP pin is low. The XWRE pin goes from high to low, and if there is no sound skipping or other problems with the CRC check at the next SCOR, XQOK is sent during the GRSCOR high interval which comes within 7ms, and the defined address and valid data are registered. At this point, the XEMP pin goes high for the first time and readout is enabled. Data readout follows RA, and is performed in sync with the internally generated Fs system clocks. The readout data and the Fs system clocks are output from the DATA and the BCK and LRCK pins, respectively. RA is the address for reading out the written data that has been validated by VWA, and the area from VWA to RA is the amount of valid data (|VWA – RA |). The upper 5 bits are output as AM21 to AM17. When RA catches up to VWA and there is no more valid data (|VWA – RA | = 0), the XEMP pin goes low and readout is prohibited. When this state occurs, the CPU must set the XRDE pin high to prohibit readout. To restart readout, valid data must be registered as described above. The XEMP pin is held low until valid data is registered. XW R E XQ O K XEM P XR D E Note) After the XWRE pin goes from high to low, readout is enabled when valid data is registered by the first XQOK. However, ensuring some difference between VWA and RA is recommended in consideration of CRC NG, etc.

– 133 – CXD3027R §4-14. CPU to DRAM Access Function The CXD3027R can establish a special area in the DRAM. This allows a microcomputer to read and write optional 16-bit data to a portion of the DRAM area. This function can be used to store and optionally read out demodulated CD TEXT data, etc. The range of this special area is set by $A7, and can be selected in 8 steps from 32K to 2M bits. Table 4-19 shows the addresses which can be specified according to the used DRAM capacity and the special area setting value. In addition, the address specification method can be selected from absolute and relative specification. 4M setting 16M setting 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 00000 to 007FF 00000 to 00FFF 00000 to 01FFF 00000 to 03FFF 00000 to 07FFF 00000 to 0FFFF 00000 to 1FFFF 00000 to 007FF 00000 to 00FFF 00000 to 01FFF 00000 to 03FFF 00000 to 07FFF 00000 to 0FFFF 00000 to 1FFFF RSL 1 0 MSL 2 1 0 DRDR19 to 0 specification range Table 4-19

– 134 – CXD3027R Write and Read by Absolute Address Specification W R ITE EN D Set $A8 com m ands XSO E2 to 1 and SD TO O U T to 1 L (R eq N G ) Transfer an optional address w ith the $A9F com m and C heck SQ SO H (R eq O K) W rite optional data w ith the $A9E com m and (W R = 1, AD R = 1, ucom = 1) (A) R EAD EN D Set $A8 com m ands XSO E2 to 1 and SD TO O U T to 1 L (R eq N G ) Transfer an optional address w ith the $A9F com m and C heck SQ SO H (R eq O K) G enerate a readout request w ith $A9E com m and (W R = 0, AD R = 1, ucom = 1) (B) L (N G ) H (D ata R eady) R ead 16-bit data from SQ SO and SQ C K C hange $A8 com m and XSO E2 from 1 to 0 C heck SQ SO (1) (2) Set $A8 com m ands XSO E2 to 1 and SD TO O U T to 0 Set $A8 com m ands XSO E2 to 1 and SD TO O U T to 0

– 135 – CXD3027R Write Communication Timing $A8 $A9F $A9E $A8C om m and XSO E2 STD O O U T SQ SO Readout Communication Timing $A8 $A9F $A9E $A8C om m and XSO E2 STD O O U T SQ SO $A8 (2)(1) D 0 D 15 SQ C K Readout Communication Operation (1)Set STDO OUT to 1 to switch the serial communication line for special memory. (2)Send the address command ($A9F), then check whether the DRAM related processing has completed using the SQSO pin. (3)The data read out from the DRAM is loaded to the communication block inside the LSI by sending the read command ($A9E) and causing XSOE2 to fall ($A8). However, the DRAM related processing requires a check as to whether the data was loaded properly using the SQSO pin. (4)The readout data is output from the SQSO pin by inputting 16 clocks from the SQCK pin.

– 136 – CXD3027R Write and Read by Relative Address Specification W R ITE EN D Set $A8 com m ands XSO E2 to 1 and SD TO O U T to 1 L (R eq N G ) C heck SQ SO H (R eq O K) W rite the absolute address∗ (A) on page 135 W rite optional data w ith the $A9E com m and (W R = 1, AD R = 0, ucom = 1) PEN D IN G EN D N EXT N Y R EAD EN D Set $A8 com m ands XSO E2 to 1 and SD TO O U T to 1 L (R eq N G ) C heck SQ SO H (R eq O K) W rite the absolute address∗ (B) on the page 135 G enerate a readout request w ith $A9E com m and (W R = 0, AD R = 0, ucom = 1) PEN D IN G EN D N EXT N Y L (N G ) C heck SQ SO H (D ata R eady) R ead 16-bit data from SQ SO and SQ C K Set $A8 com m ands XSO E2 to 1 and SD TO O U T to 0 C hange $A8 com m and XSO E2 from 1 to 0 and set SD TO O U T to 1 Set $A8 com m ands XSO E2 to 1 and SD TO O U T to 0

– 137 – CXD3027R §4-15. Asymmetry Correction Fig. 4-20 shows the block diagram and circuit example. R FAC R 1 R 1 ASYO ASYI R 1 2 R 2 5= BIAS R 1 R 1 R 2 ASYE com m and Fig. 4-20. Asymmetry Correction Application Circuit.

– 138 – CXD3027R §4-16. CD TEXT Data Demodulation

In order to demodulate the CD TEXT data, set the command $8 Data 6 D3 TXON to 1. While TXON is 1, the CD TEXT demodulation circuit occupies the EXCK and SBSO pins, so connect EXCK to low and do not use the data output from SBSO. Also, 26.7ms (max.) are required to demodulate the CD TEXT data correctly after TXON is set to 1.
The CD TEXT data is output by switching the SQSO pin with the command. The CD TEXT data output is enabled by setting the command $8 Data 6 D2 TXOUT to 1. To read data, the readout clock should be input to SQCK.
The readable data are the CRC counting results for each pack and the CD TEXT data (16 bytes) except for CRC data.
When the CD TEXT data is read, the order of the MSB and LSB is inverted within each byte. As a result, although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first.
Data which can be stored in the LSI is 1 packet (4 packs). Fig. 4-21. Block Diagram of CD TEXT Demodulation Circuit SQ C K SQ SO TXO U T Subcode D ecoder C D TEXT D ecoder TXO N SBSO EXC K

– 139 – CXD3027R C R C C R C C R C C R C 1 0 0 0 0 S2 R 2 W 1 V1 U 1 T1 S1 R 1 U 3 T3 S3 R 3 W 2 V2 U 2 T2 W 4 V4 U 4 T4 S4 C R C D ata ID 1 (Pack1) ID 2 (Pack1) ID 3 (Pack1)

16 Bytes16 Bytes16 Bytes16 Bytes4 bits4 bitsSubcode Q D ata

(com m and) SQ C K SQ SO SQ C K TXO U T (com m and) LSB M SB LSB M SB LSB C R C 0 Pack1 Pack2 Pack3 Pack4 C R C FC R C F

80 C locks

520 C locks

Fig. 4-22. CD TEXT Data Timing Chart

– 140 – CXD3027R [5] Description of Servo Signal Processing System Functions and Commands §5-1. General Description of Servo Signal Processing System (VDD : Supply voltage) Focus servo Sampling rate: 88.2kHz (when MCK = 128Fs) Input range: 1/4VDD to 3/4VDD Output format: 7-bit PWM Other: Offset cancel Focus bias adjustment Focus search Gain-down Defect countermeasure Auto gain control Tracking servo Sampling rate: 88.2kHz (when MCK = 128Fs) Input range: 1/4V DD to 3/4VDD Output format: 7-bit PWM Other: Offset cancel E:F balance adjustment Track jump Gain-up Defect countermeasure Drive cancel Auto gain control Vibration countermeasure Sled servo Sampling rate: 345Hz (when MCK = 128Fs) Input range: 1/4V DD to 3/4VDD Output format: 7-bit PWM Other: Sled move FOK, MIRR, DFCT signal generation RF signal sampling rate:1.4MHz (when MCK = 128Fs) Input range: 1/4VDD to 3/4VDD Other: RF zero level automatic measurement

– 141 – CXD3027R §5-2. Digital Servo Block Master Clock (MCK) The clock with 2/3 frequency of the crystal is supplied to the digital servo block. XT4D and XT2D are $3F commands, and XT1D is a $3E command. (Default is 0 for each command) The digital servo block is designed with an MCK frequency of 5.6448MHz (128Fs) as typical. Mode 384Fs 384Fs 384Fs 768Fs 768Fs 768Fs 768Fs 256Fs 256Fs 256Fs 512Fs 512Fs 512Fs 512Fs 256Fs 128Fs 128Fs 512Fs 256Fs 128Fs 128Fs XTAI FSTO XTSL XT4D XT2D XT1D Frequency division ratioMCK Fs = 44.1kHz, *: don't care Table 5-1.

– 142 – CXD3027R §5-3. DC Offset Cancel [AVRG (Average) Measurement and Compensation] (See Fig. 5-3.) The CXD3027R can measure the averages of RFDC, VC, FE and TE and compensate these signals using the measurement results to control the servo effectively. This AVRG measurement and compensation is necessary to initialize the CXD3027R, and is able to cancel the DC offset. AVRG measurement takes the levels applied to the VC, FE, RFDC and TE pins as the digital average values of 256 samples, and then loads these values into each AVRG register. The AVRG measurement commands are D15 (VCLM), D13 (FLM), D11 (RFLM) and D4 (TLM) of $38. Measurement is on when the respective command is set to 1. AVRG measurement requires approximately 2.9ms to 5.8ms (when MCK = 128Fs) after the command is received. The completion of AVRG measurement operation can be monitored by the SENS pin. (See Timing Chart 5-2.) Monitoring requires that the upper 8 bits of the command register are 38 (h). XLAT SEN S (= XAVEBSY) M ax. 1µs AVR G m easurem ent com pleted 2.9 to 5.8m s Timing Chart 5-2. <Measurement> VC AVRG: The VC DC offset (VC AVRG) which is the center voltage for the system is measured and used to compensate the FE, TE and SE signals. FE AVRG: The FE DC offset (FE AVRG) is measured and used to compensate the FE and FZC signals. TE AVRG: The TE DC offset (TE AVRG) is measured and used to compensate the TE and SE signals. RF AVRG: The RF DC offset (RF AVRG) is measured and used to compensate the RFDC signal. <Compensation> RFLC: (RF signal – RF AVRG) is input to the RF In register. "00" is input when the RF signal is lower than RF AVRG. TCL0: (TE signal – VC AVRG) is input to the TRK In register. TCL1: (TE signal – TE AVRG) is input to the TRK In register. VCLC: (FE signal – VC AVRG) is input to the FCS In register. FLC1: (FE signal – FE AVRG) is input to the FCS In register. FLC0: (FE signal – FE AVRG) is input to the FZC register. Two methods of canceling the DC offset are assumed for the CXD3027R. These methods are shown in Figs. 5-3a and 5-3b. An example of AVRG measurement and compensation commands is shown below. $38 08 00 (RF AVRG measurement) $38 20 00 (FE AVRG measurement) $38 00 10 (TE AVRG measurement) $38 14 0A (Compensation on [RFLC, FLC0, FLC1, TLC1]; corresponds to Fig. 5-3a.) See the description of $38 for these commands.

– 143 – CXD3027R §5-4. E:F Balance Adjustment Function (See Fig. 5-3.) When the disc is rotated with the laser on, and with the FCS (focus) servo on via FCS search, the traverse waveform appears in the TE signal due to disc eccentricity. In this condition, the low-frequency component can be extracted from the TE signal using the built-in TRK hold filter by setting D5 (TBLM) of $38 to 1. The extracted low-frequency component is loaded into the TRVSC register as a digital value, and the TRVSC register value is established when TBLM returns to 0. Next, setting D2 (TLC2) of $38 to 1 compensates the values obtained from the TE and SE input pins with the TRVSC register value (subtraction), allowing the E:F balance offset to be adjusted. (See Fig. 5-3.) §5-5. FCS Bias (Focus Bias) Adjustment Function The FBIAS register value can be added to the FCS servo filter input by setting D14 (FBON) of $3A to 1. (See Fig. 5-3.) When D11 = 0 and D10 = 1 is set by $34F, the FBIAS register value can be written using the 9-bit value of D9 to D1 (D9: MSB). In addition, the RF jitter can be monitored by setting the $8 command SOCT to 1. (See "DSP Block Timing Chart".) The FBIAS register can be used as a counter by setting D13 (FBSS) of $3A to 1. The FBIAS register functions as an up counter when D12 (FBUP) of $3A = 1, and as a down counter when D12 (FBUP) of $3A = 0. The number of up and down steps can be changed by setting D11 and D10 (FBV1 and FBV0) of $3A. When using the FBIAS register as a counter, the counter stops when the value set beforehand in FBL9 to FBL1 of $34 matches the FCSBIAS value. Also, if the upper 8 bits of the command register are $3A at this time, SENS goes high and the counter stop can be monitored. A B C FBIAS setting value (FB9 to FB1) LIM IT value (FBL9 to FBL1) SEN S value A: R egister m ode B: C ounter m ode C : C ounter m ode (w hen stopped) Here, assume the FBIAS setting value FB9 to FB1 and the FBIAS LIMIT value FBL9 to FBL1 are set in status A. For example, if command registers FBUP = 0, FBV1 = 0, FBV0 = 0 and FBSS = 1 are set from this status, down count starts from status A and approaches the set LIMIT value. When the LIMIT value is reached and the FBIAS value matches FBL9 to FBL1, the counter stops and the SENS pin goes high. Note that the up/down counter counts at each sampling cycle of the focus servo filter. The number of steps by which the count value changes can be selected from 1, 2, 4 or 8 steps by FBV1 and FBV0. When converted to FE input, 1 step corresponds to 1/512 · V DD /2.

– 144 – CXD3027R Fig. 5-3a. Fig. 5-3b. TE AVR G register TLC 1 TR VSC register TLC 2 – – to TR K In registerTE from A/D FE AVR G register FLC 1 FBIAS register FBO N to FC S In register FLC 0 to FZC register FE from A/D R FLC to R F In registerR FD C from A/D R F AVR G register – – to SLD In registerSE from A/D TLC 1 • TLD 1 TLC 2 • TLD 2 VC AVR G register TLC 0 TR VSC register TLC 2 – – to TR K In registerTE from A/D FBIAS register FBO N to FC S In register VC LC to FZC register FE from A/D – R FLC to R F In registerR FD C from A/D R F AVR G register – – to SLD In registerSE from A/D TLC 0 • TLD 0 TLC 2 • TLD 2 FE AVR G register FLC 0

– 145 – CXD3027R §5-6. AGCNTL (Automatic Gain Control) Function The AGCNTL function automatically adjusts the filter internal gain in order to obtain the appropriate servo loop gain. AGCNTL not only copes with the sensitivity variation of the actuator and photo diode, etc., but also obtains the optimal gain for each disc. The AGCNTL command is sent when each servo is turned on. During AGCNTL operation, if the upper 8 bits of the command register are 38 (h), the completion of AGCNTL operation can be confirmed by monitoring the SENS pin. (See Timing Chart 5-4 and "Description of SENS Signals".) Setting D9 and D8 of $38 to 1 sets FCS (focus) and TRK (tracking) respectively to AGCNTL operation. Note) During AGCNTL operation, each servo filter gain must be normal, and the anti-shock circuit (described hereafter) must be disabled. XLAT SEN S (= AG O K) M ax. 11.4µs AG C N TL com pletion Timing Chart 5-4 Coefficient K13 changes for AGF (focus AGCNTL) and coefficients K23 and K07 change for AGT (tracking AGCNTL) due to AGCNTL. These coefficients change from 01 to 7F (h), and they must also be set within this range when written externally. After AGCNTL operation has completed, these coefficient values can be confirmed by reading them out from the SENS pin with the serial readout function (described hereafter). AGCNTL related settings The following settings can be changed with $35, $36 and $37. FG6 to FG0;AGF convergence gain setting, effective setting range: 00 to 57 (h) TG6 to TG0;AGT convergence gain setting, effective setting range: 00 to 57 (h) AGS; Self-stop on/off AGJ; Convergence completion judgment time AGGF; Internally generated sine wave amplitude (AGF) AGGT; Internally generated sine wave amplitude (AGT) AGV1; AGCNTL sensitivity 1 (during rough adjustment) AGV2; AGCNTL sensitivity 2 (during fine adjustment) AGHS; Rough adjustment on/off AGHT; Fine adjustment time Note) Converging servo loop gain values can be changed with the FG6 to FG0 and TG6 to TG0 setting values. In addition, these setting values must be within the effective setting range. The default settings aim for 0 dB at 1kHz. However, since convergence values vary according to the characteristics of each constituent element of the servo loop, FG and TG values should be set as necessary.

– 146 – CXD3027R AGCNTL default operation has two stages. In the first stage, rough adjustment is performed with high sensitivity for a certain period of time (select 256/128ms with AGHT, when MCK = 128Fs), and the AGCNTL coefficient approaches the appropriate value. The sensitivity at this time can be selected from two types with AGV1. In the second stage, the AGCNTL coefficient is finely adjusted with relatively low sensitivity to further approach the appropriate value. The sensitivity for the second stage can be selected from two types with AGV2. In the second stage of default operation, when the AGCNTL coefficient reaches the appropriate value and stops changing, the CXD3027R confirms that the AGCNTL coefficient has not changed for a certain period of time (select 63/31ms with AGHJ, when MCK = 128Fs), and then completes AGCNTL operation. (Self-stop mode) This self-stop mode can be canceled by setting AGS to 0. In addition, the first stage is omitted for AGCNTL operation when AGHS is set to 0. An example of AGCNTL coefficient transitions during AGCNTL operation with various settings is shown in Fig. 5-5. Initial value SEN S AG C N TL Start AG C N TL com pletion C onvergence value AG C N TL coefficient value Slope AG V1 AG H T AG J Slope AG V2 Fig. 5-5. Note) Fig. 5-5 shows the case where the AGCCNTL coefficient converges from the initial value to a smaller value.

– 147 – CXD3027R §5-7. FCS Servo and FCS Search (Focus Search) The FCS servo is controlled by the 8-bit serial command $0X. (See Table 5-6.) Register nameCommand D23 to D20 D19 to D16 1 0 * * 1 1 * * 0 * 0 * 0 * 1 * 0 * 1 0 0 * 1 1 FOCUS SE RVO ON (FOCUS GAIN NORMAL) FOCUS SE RVO ON (FOCUS GAIN DOWN) FOCUS SE RVO OFF, 0V OUT FOCUS SE RVO OFF, FOCUS SEARCH VOLTAGE OUT FOCUS SEARCH VOLTAGE DOWN FOCUS SEARCH VOLTAGE UP 0 0 0 0FOCUS CONTROL0 Table 5-6. FCS Search FCS search is required in the course of turning on the FCS servo. Fig. 5-7 shows the signals for sending commands $00 ﬁ $02 ﬁ $03 and performing only FCS search operation. Fig. 5-8 shows the signals for sending $08 (FCS on) after that. FC SD R V R F FO K FE FZC FZC com parator level $00 $02 $03 FC SD R V R F FO K FE FZC $00 $02 $03 $08 Fig. 5-7. Fig. 5-8. *: don't care

– 148 – CXD3027R §5-8. TRK (Tracking) and SLD (Sled) Servo Control The TRK and SLD servos are controlled by the 8-bit command $2X. (See Table 5-9.) When the upper 4 bits of the serial data are 2 (h), TZC is output to the SENS pin. Register name Command D23 to D20 D19 to D16 0 0 * * 0 1 * * 1 0 * * 1 1 * * * * 0 0 * * 0 1 * * 1 0 * * 1 1 TRACKING SE RVO OFF TRACKING SE RVO ON FORWARD TRACK JUMP REVERSE TRACK JUMP SLED SE RVO OFF SLED SE RVO ON FORWARD SLED MOVE REVERSE SLED MOVE 0 0 1 0TRACKING MODE2 Table 5-9. TRK Servo The TRK JUMP (track jump) level can be set with 6 bits (D13 to D8) of $36. In addition, when the TRK servo is on and D17 of $1 is set to 1, the TRK servo filter switches to gain-up mode. The filter also switches to gain-up mode when the LOCK signal goes low or when vibration is detected with the anti-shock circuit (described hereafter) enabled. The CXD3027R has 2 types of gain-up filter structures in TRK gain-up mode which can be selected by setting D16 of $1. (See Table 5-17.) SLD Servo The SLD MOV (sled move) output, composed of a basic value from 6 bits (D13 to D8) of $37, is determined by multiplying this value by 1·, 2·, 3·, or 4· set using D17 and D16 when D18 = D19 = 0 is set with $3. (See Table 5-10.) SLD MOV must be performed continuously for 50µs or more. In addition, if the LOCK input signal goes low when the SLD servo is on, the SLD servo turns off. Note) When the LOCK signal is low, the TRK servo switches to gain-up mode and the SLD servo is turned off. These operations are disabled by setting D6 (LKSW) of $38 to 1. Register name Command D23 to D20 D19 to D16 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 SLED KICK LEVEL (basic value · ±1) SLED KICK LEVEL (basic value · ±2) SLED KICK LEVEL (basic value · ±3) SLED KICK LEVEL (basic value · ±4) 0 0 1 1SELECT3 Table 5-10. *: don't care

– 149 – CXD3027R §5-9. MIRR and DFCT Signal Generation The RF signal obtained from the RFDC pin is sampled at approximately 1.4MHz (when MCK = 128Fs) and loaded. The MIRR and DFCT signals are generated from this RF signal. MIRR Signal Generation The loaded RF signal is applied to peak hold and bottom hold circuits. An envelope is generated from the waveforms generated in these circuits, and the MIRR comparator level is generated from the average of this envelope waveform. The MIRR signal is generated by comparing the waveform generated by subtracting the bottom hold value from the peak hold value with this MIRR comparator level. (See Fig. 5-11.) The bottom hold speed and mirror sensitivity can be selected from four values using D7 and D6, and D5 and D4, respectively, of $3C. R F Peak H old Bottom H old Peak H old – Bottom H old M IR R M IR R C om p (M irror com parator level) H L R F Peak H old1 Peak H old2 Peak H old – Bottom H old D FC T (D efect com parator level) H L SD F Fig. 5-11. DFCT Signal Generation The loaded RF signal is input to two peak hold circuits with different time constants, and the DFCT signal is generated by comparing the difference between these two peak hold waveforms with the DFCT comparator level. (See Fig. 5-12.) The DFCT comparator level can be selected from four values using D13 and D12 of $3B. Fig. 5-12.

– 150 – CXD3027R §5-10. DFCT Countermeasure Circuit The DFCT countermeasure circuit maintains the directionality of the servo so that the servo does not become easily dislocated due to scratches or defects on discs. Specifically, this operation is achieved by detecting scratches and defects with the DFCT signal generation circuit, and when DFCT goes high, applying the low-frequency component of the error signal before DFCT went high to the FCS and TRK servo filter inputs. (See Fig. 5-13.) In addition, these operations are activated by the default. They can be disabled by setting D7 (DFSW) of $38 to 1. Input register H old register EN H old filter Servo filter Error signal D FC T Fig. 5-13. §5-11. Anti-Shock Circuit When vibrations occur in the CD player, this circuit forces the TRK filter to switch to gain-up mode so that the servo does not become easily dislocated. This circuit is for systems which require vibration countermeasures. Concretely, vibrations are detected using an internal anti-shock filter and comparator circuit, and the gain is increased. (See Fig. 5-14.) The comparator level is fixed to 1/16 of the maximum comparator input amplitude. However, the comparator level is practically variable by adjusting the value of the anti-shock filter output coefficient K35. This function can be turned on and off by D19 of $1 when the brake circuit (described hereafter) is off. (See Table 5-17.) This circuit can also support an external vibration detection circuit, and can set the TRK servo filter to gain-up mode by inputting high level to the ATSK pin. When the upper 4 bits of the command register are 1 (h), vibration detection can be monitored from the SENS pin. It can also be monitored from the ATSK pin by setting $3F command ASOT to 1. TE Anti shock filter TR K G ain U p filter TR K G ain N orm al filter TR K PW M G en. ATSK SEN SC om parator Fig. 5-14.

– 151 – CXD3027R §5-12. Brake Circuit Immediately after a long distance track jump it tends to be hard for the actuator to settle and for the servo to turn on. The brake circuit prevents these phenomenon. In principle, the brake circuit uses the tracking drive as a brake by cutting the unnecessary portions utilizing the 180° offset in the RF envelope and tracking error phase relationship which occurs when the actuator traverses the track in the radial direction from the inner track to the outer track and vice versa. (See Figs. 5-15 and 5-16.) Concretely, this operation is achieved by masking the tracking drive using the TRKCNCL signal generated by loading the MIRR signal at the edge of the TZC (Tracking Zero Cross) signal. The brake circuit can be turned on and off by D18 of $1. (See Table 5-17.) In addition, the low frequency for the tracking drive after masking can be boosted. (SFBK1, 2 of $34B) TR K D R V FW D JM P R EV JM P Servo O N R F Trace M IR R TE 0 TZC Edge TR KC N C L 0TR K D R V (SFBK O FF) SEN S TZC out Inner track → O uter track 0TR K D R V (SFBK O N ) TR K D R V R EV JM P FW D JM P Servo O N R F Trace M IR R TE 0 TZC Edge TR KC N C L 0TR K D R V (SFBK O FF) SEN S TZC out O uter track → Inner track 0TR K D R V (SFBK O N ) Fig. 5-15. Fig. 5-16. Register name Command D23 to D20 D19 to D16 1 0 * * 0 * * * * 1 * * * 0 * * * * 0 * * * 1 * * * * 1 * * * 0 ANTI SHOCK ON ANTI SHOCK OFF BRAKE ON BRAKE OFF TRACKING GAIN NORMAL TRACKING GAIN UP TRACKING GAIN UP FILTER SELECT 1 TRACKING GAIN UP FILTER SELECT 2 0 0 0 1TRACKING CONTROL1 Table 5-17. *: don't care

– 152 – CXD3027R §5-13. COUT Signal The COUT signal is output to count the number of tracks during traverse, etc. It is basically generated by loading the MIRR signal at both edges of the TZC signal. The used TZC signal can be selected from among three different phases according to the COUT signal application.

HPTZC: For 1-track jumps Fast phase COUT signal generation with a fast phase TZC signal. (The TZC phase is advanced by a cut-off 1kHz digital HPF; when MCK = 128Fs.)
STZC: For COUT generation when MIRR is externally input and for applications other than COUT generation. This is generated by sampling the TE signal at 700kHz. (when MCK = 128Fs)
DTZC: For high-speed traverse Reliable COUT signal generation with a delayed phase STZC signal. Since it takes some time to generate the MIRR signal, it is necessary to delay the TZC signal in accordance with the MIRR signal delay during high-speed traverse. The COUT signal output method is switched with D15 and D14 of $3C. When D15 = 1: STZC When D15 = 0 and D14 = 0: HPTZC When D15 = 0 and D14 = 1: DTZC When DTZC is selected, the delay can be selected from two values with D14 of $36. §5-14. Serial Readout Circuit The following measurement and adjustment results specified beforehand by serial command $39 can be read out from the SENS pin by inputting the readout clock to the SCLK pin. (See Fig. 5-18, Table 5-19 and "Description of SENS Signals".) Specified commands $390C: VC AVRG measurement result $3953: FCS AGCNTL coefficient result $3908: FE AVRG measurement result $3963: TRK AGCNTL coefficient result $3904: TE AVRG measurement result $391C: TRVSC adjustment result $391F: RF AVRG measurement result $391D: FBIAS register value tDLS tSPW 1/fSCLK MSB LSB XLAT SCLK Serial Readout Data (SENS pin) ... ... Item Symbol Min. Typ. Max. Unit SCLK frequency SCLK pulse width Delay time f SCLK tSPW tDLS 31.3

µs Table 5-19. During readout, the upper 8 bits of the command register must be 39 (h). Fig. 5-18.

– 153 – CXD3027R §5-16. PWM Output FCS, TRK and SLD PWM format outputs are described below. In particular, FCS and TRK use a double oversampling noise shaper. Timing Chart 5-20 and Fig. 5-21 show examples of output waveforms and drive circuits. tMCK = » 180ns Timing Chart 5-20. Fig. 5-21. Drive Circuit 64tM C K 64tM C K 64tM C K AtM C K AtM C KSFD R SR D R SLD 32tM C K 32tM C K 32tM C K 32tM C K32tM C K32tM C K FC S/TR K FFD R / TFD R FR D R / TR D R O utput value +A O utput value –A O utput value 0 tM C KA 2 tM C KA tM C KA 2 tM C KA M C K 5.6448MHz R R R R VEE D R V VC C R D R FD R §5-15. Writing to Coefficient RAM The coefficient RAM can be rewritten by $34. All coefficients have default values in the built-in ROM, and transfer from the ROM to the RAM is completed approximately 40µs (when MCK = 128Fs) after the XRST pin rises. (The coefficient RAM cannot be rewritten during this period.) After that, the characteristics of each built-in filter can be finely adjusted by rewriting the data for each address of the coefficient RAM. The coefficient rewrite command is comprised of 24 bits, with D14 to D8 of $34 as the address (D15 = 0) and D7 to D0 as the data. Coefficient rewriting is completed 11.3µs (when MCK = 128Fs) after the command is received. When rewriting multiple coefficients continuously, be sure to wait 11.3µs (when MCK = 128Fs) before sending the next rewrite command.

– 154 – CXD3027R §5-17. Servo Status Changes Produced by LOCK Signal When the LOCK signal becomes low, the TRK servo switches to the gain-up mode and the SLD servo turns off in order to prevent SLD free-running. Setting D6 (LKSW) of $38 to 1 deactivates this function. In other words, neither the TRK servo nor the SLD servo change even when the LOCK signal becomes low. This enables microcomputer control. §5-18. Description of Commands and Data Sets $34 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 KA6 KA5 KA4 KA3 KA2 KA1 KA0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 PGFS1 PGFS0 PFOK1 PFOK0 0 0 0 MRS MRT1 MRT0 0 0 When D15 = 0. KA6 to KA0: Coefficient address KD7 to KD0: Coefficient data $348 (preset: $348 000) PGFS1 High when the frame sync is at the correct timing, low when not the correct timing. High when the frame sync is at the correct timing, low when continuously not the correct timing for 2ms or longer. High when the frame sync is at the correct timing, low when continuously not the correct timing for 4ms or longer. High when the frame sync is at the correct timing, low when continuously not the correct timing for 8ms or longer. PGFS0 Processing These commands set the GFS signal hold time. The hold time is inversely proportional to the playback speed. PFOK1 High when the RFDC value is higher than the FOK slice level, low when lower than the FOK slice level. High when the RFDC value is higher than the FOK slice level, low when continuously lower than the FOK slice level for 4.35ms or more. High when the RFDC value is higher than the FOK slice level, low when continuously lower than the FOK slice level for 10.16ms or more. High when the RFDC value is higher than the FOK slice level, low when continuously lower than the FOK slice level for 21.77ms or more. PFOK0 Processing These commands set the FOK signal hold time. See $3B for the FOK slice level. These are the values when MCK = 128Fs, and the hold time is inversely proportional to the MCK setting.

– 155 – CXD3027R MRS: This command switches the time constant for generating the MIRR comparator level of the MIRR generation circuit. When 0, the time constant is normal. (default) When 1, the time constant is longer than normal. The time during which MIRR = high due to the effects of RFDC signal pulse noise, etc., can be suppressed by setting MRS = 1. MRT1, 0: These commands limit the time while MIRR = high. MRT2 MRT1 No time limit 1.10 2.20 4.00 MIRR maximum time [ms] *: preset D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 A/D SEL COPY EN EMPH D CAT DOUT EN1 DOUT DMUT DOUT WOD WIN EN DOUT EN2 0 0 0 $34A (preset: $34A 150) Command bit A/DSEL = 0 A/DSEL = 1 Bit 1 of the channel status data is output as audio data. Bit 1 of the channel status data is output as other than audio data. Processing Command bit COPY EN1 = 0 COPY EN1 = 1 Bit 2 of the channel status data is output as digital copy prohibited. Bit 2 of the channel status data is output as digital copy enabled. Processing Command bit EMPH D = 0 EMPH D = 1 Bit 3 of the channel status data is output as without pre-emphasis. Bit 3 of the channel status data is output as with pre-emphasis. Processing Command bit CAT b8 = 0 CAT b8 = 1 Bit 8 of the channel status data is output as 0. Bit 8 of the channel status data is output as 1. Processing Command bit DOUT EN = 0 DOUT EN = 1 The DOUT signal, generated from the PCM data read out from the disc, is output. The DOUT signal, generated from the DA interface input, is output. Processing

– 156 – CXD3027R Command bit DOUT DMUT = 0 DOUT DMUT = 1 Digital Out output is normally output. All the audio data portions are output in zero, with Digital Out output as it is. Processing Command bit DOUT WOD = 0 DOUT WOD = 1 The DOUT sync window is not open. The DOUT sync window is open. Processing Command bit WIN EN = 0 WIN EN = 1 Automatic synchronization to the input LRCK to match the phase with the internal processing is disabled. Automatic synchronization to the input LRCK to match the phase with the internal processing is enabled. Processing Command bit DOUT EN2 = 0 DOUT EN2 = 1 Set to 0 when not generating Digital Out from the DA interface input. Set to 1 when generating Digital Out from the DA interface input. Processing $34A commands cont. * See "Mute conditions" (1) and (3) to (5) of $AX commands for the other mute conditions. * See $8 commands for DOUT Mute and DOUT Mute F. DOUT EN1 DOUT DMUT MD2 pin Other mute conditions DOUT Mute DOUT Mute F DOUT output OFF 0dB The output from the PCM data read out from a disc. –∞ dB The output from the PCM data read out from a disc. 0dB The output from the DA interface input. –∞ dB The output from the DA interface input. —: don't care

– 157 – CXD3027R D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 0 THBON FHBON TLB1ON FLB1ON TLB2ON 0 HBST1 HBST0 LB1S1 LB1S0 LB2S1 LB2S0 $34C (preset: $34C 000) These bits turn on the boost function. (See §5-20. Filter Composition.) There are five boosters (three for the TRK filter and two for the FCS filter) which can be turned on and off independently. THBON: When 1, the high frequency is boosted for the TRK filter. Preset is 0. FHBON: When 1, the high frequency is boosted for the FCS filter. Preset is 0. TLB1ON: When 1, the low frequency is boosted for the TRK filter. Preset is 0. FLB1ON: When 1, the low frequency is boosted for the FCS filter. Preset is 0. TLB2ON: When 1, the low frequency is boosted for the TRK filter. Preset is 0. The difference between TLB1ON and TLB2ON is the position where the low frequency is boosted. For TLB1ON, the low frequency is boosted before the TRK jump, and for TLB2ON, after the TRK jump. The following commands set the boosters. (See §5-20. Filter Composition.) HBST1, HBST0: TRK and FCS HighBooster setting. HighBooster has the configuration shown in Fig. 5-22a, and can select three different combinations of coefficients BK1, BK2 and BK3. (See Table 5-23a.) An example of characteristics is shown in Fig. 5-24a. These characteristics are the same for both the TRK and FCS filters. The sampling frequency is 88.2kHz (when MCK = 128Fs). LB1S1, LB1S0: TRK and FCS LowBooster-1 setting. LowBooster-1 has the configuration shown in Fig. 5-22b, and can select three different combinations of coefficients BK4, BK5 and BK6. (See Table 5-23b.) An example of characteristics is shown in Fig. 5-24b. These characteristics are the same for both the TRK and FCS filters. The sampling frequency is 88.2kHz (when MCK = 128Fs). LB2S1, LB2S0: TRK LowBooster-2 setting. LowBooster-2 has the configuration shown in Fig. 5-22c, and can select three different combinations of coefficients BK7, BK8 and BK9. (See Table 5-23c.) An example of characteristics is shown in Fig. 5-24c. This booster is used exclusively for the TRK filter. The sampling frequency is 88.2kHz (when MCK = 128Fs). Note) Fs = 44.1kHz D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 1 SFBK1 SFBK2 0 0 0 0 0 0 0 0 0 0 $34B (preset: $34B 000) The low frequency can be boosted for brake operation. See §5-12 for brake operation. SFBK1: When 1, brake operation is performed by setting the LowBooster-1 input to 0. This is valid only when TLB1ON = 1. Preset is 0. SFBK2: When 1, brake operation is performed by setting the LowBooster-2 input to 0. This is valid only when TLB2ON = 1. Preset is 0.

– 158 – CXD3027R BK2 Z – 1 Z – 1 BK1 BK3 HBST1 HBST0 HighBooster setting –120/128 –124/128 –126/128 BK1 BK2 BK3 Table 5-23aFig. 5-22a BK5 Z – 1 Z – 1 BK4 BK6 Fig. 5-22b BK8 Z – 1 Z – 1 BK7 BK9 Fig. 5-22c LB1S1 LB1S0 LowBooster-1 setting –255/256 –511/512 –1023/1024 BK4 BK5 BK6 Table 5-23b LB2S1 LB2S0 LowBooster-12 setting –255/256 –511/512 –1023/1024 BK7 BK8 BK9 Table 5-23c

– 159 – CXD3027R –15 Gain [dB] –12 100101 Frequency [H z] 1k 10k 23 1 –90 +90 Phase [degree] –72 –36 +36 +72 100101 Frequency [H z] 1k 10k 23 1 Fig. 5-24a. Servo HighBooster characteristics [FCS, TRK] (MCK = 128Fs) HBST1 = 0 HBST1 = 1, HBST0 = 0 HBST1 = 1, HBST0 = 11 2 3

– 160 – CXD3027R –15 Gain [dB] –12 100101 Frequency [H z] 1k 10k –90 +90 Phase [degree] –72 –36 +36 +72 100101 Frequency [H z] 1k 10k 23 1 Fig. 5-24b. Servo LowBooster-1 characteristics [FCS, TRK] (MCK = 128Fs) LB1S1 = 0 LB1S1 = 1, LB1S0 = 0 LB1S1 = 1, LB1S0 = 11 2 3

– 161 – CXD3027R –15 Gain [dB] –12 100101 Frequency [H z] 1k 10k –90 +90 Phase [degree] –72 –36 +36 +72 100101 Frequency [H z] 1k 10k 2 13 23 1 Fig. 5-24c. Servo LowBooster-2 characteristics [TRK] (MCK = 128Fs) LB2S1 = 0 LB2S1 = 1, LB2S0 = 0 LB2S1 = 1, LB2S0 = 11 2 3

– 162 – CXD3027R D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 0 IDFSL3 IDFSL2 IDFSL1 IDFSL0 0 0 IDFT1 IDFT0 0 0 0 INVRFDC $34E (preset: $34E000) IDFSL3: New DFCT detection output setting. When 0, only the DFCT signal described in §5-9 is detected and output from the DFCT pin. (default) When 1, the DFCT signal described in §5-9 and the new DFCT signal are switched and output from the DFCT pin. The switching timing is as follows. When the §5-9 DFCT signal is low, the new DFCT signal is output from the DFCT pin. When the §5-9 DFCT signal is high, this DFCT signal is output from the DFCT pin. In addition, the time at which the new DFCT signal can be output after the §5-9 DFCT signal switches to low can also be set. (See IDFT1, 0 of $34E.) IDFSL3 §5-9 DFCT L H L H §5-9 DFCT §5-9 DFCT New DFCT §5-9 DFCT DFCT pin IDFSL2: New DFCT detection time setting. DFCT = high is held for a certain time after new DFCT detection. This command sets that time. When 0, a long hold time. (default) When 1, a short hold time. IDFSL1: New DFCT detection sensitivity setting. When 0, a high detection sensitivity. (default) When 1, a low detection sensitivity. IDFSL0: New DFCT release sensitivity setting. When 0, a high release sensitivity. (default) When 1, a low release sensitivity. IDFT1, 0: These commands set the time at which the new DFCT signal can be output (output prohibited time) after the §5-9 DFCT signal switches to low. IDFT1 IDFT0 204.08µs 294.78µs 408.16µs 612.24µs New DFCT signal output prohibited time *: preset INVRFDC: RFDC signal polarity inverted input setting. When 0, the RFDC signal polarity is set to non-inverted. (default) When 1, the RFDC signal polarity is set to inverted.

– 163 – CXD3027R D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 0 1 FB9 FB8 FB7 FB6 FB5 FB4 FB3 FB2 FB1 — When D15 = D14 = D13 = D12 = 1 ($34F) D11 = 0, D10 = 1 FBIAS register write FB9 to FB1: Data;two's complement data, FB9 = MSB. For FE input conversion, FB9 to FB1 = 011111111 corresponds to 255/256 · V DD /4 and FB9 to FB1 = 100000000 to –256/256 · VDD /4 respectively. (VDD : supply voltage) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 1 0 FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1 — When D15 = D14 = D13 = D12 = D11 = 1 ($34F) D10 = 0 FBIAS LIMIT register write FBL9 to FBL1: Data; data compared with FB9 to FB1, FBL9 = MSB. When using the FBIAS register in counter mode, counter operation stops when the value of FB9 to FB1 matches with FBL9 to FBL1. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 0 0 TV9 TV8 TV7 TV6 TV5 TV4 TV3 TV2 TV1 TV0 When D15 = D14 = D13 = D12 = 1 ($34F) D11 = 0, D10 = 0 TRVSC register write TV9 to TV0: Data;two's complement data, TV9 = MSB. For TE input conversion, TV9 to TV0 = 0011111111 corresponds to 255/256 · V DD /4 and TV9 to TV0 = 1100000000 to –256/256 · VDD /4 respectively. (VDD : supply voltage) Notes) •When the TRVSC register is read out, the data length is 9 bits. At this time, data corresponding to each bit TV8 to TV0 during external write are read out.

When reading out internally measured values and then writing these values externally, set TV9 the same as TV8. $34F

– 164 – CXD3027R $35 (preset: $35 58 2D) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FT1 FT0 FS5 FS4 FS3 FS2 FS1 FS0 FTZ FG6 FG5 FG4 FG3 FG2 FG1 FG0 FT1, FT0, FTZ:Focus search-up speed Default value: 010 (0.673 · VDD V/s) Focus drive output conversion FT1 1.35 · V DD 0.673 · VDD 0.449 · VDD 0.336 · VDD 1.79 · VDD 1.08 · VDD 0.897 · VDD 0.769 · VDD FT0 FTZ Focus search speed [V/s] FS5 to FS0: Focus search limit voltage Default value: 011000 ((1 ± 24/64) · VDD /2, VDD : PWM driver supply voltage) Focus drive output conversion FG6 to FG0: AGF convergence gain setting value Default value: 0101101 $36 (preset: $36 0E 2E) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TDZC DTZC TJ5 TJ4 TJ3 TJ2 TJ1 TJ0 SFJP TG6 TG5 TG4 TG3 TG2 TG1 TG0 TDZC: Selects the TZC signal for generating the TRKCNCL signal during brake circuit operation. When 0, the edge of the HPTZC or STZC signal, whichever has the faster phase, is used. When 1, the edge of the HPTZC, STZC signal or the tracking drive signal zero-cross, whichever has the faster phase, is used. (See §5-12.) DTZC: DTZC delay (8.5/4.25µs, when MCK = 128Fs) Default value: 0 (4.25µs) TJ5 to TJ0: Track jump voltage Default value: 001110 ((1 ± 14/64) · V DD /2, VDD : PWM driver supply voltage) Tracking drive output conversion SFJP: Surf jump mode on/off The tracking PWM output is generated by adding the tracking filter output and TJReg (TJ5 to TJ0), by setting D7 to 1 (on) TG6 to TG0: AGT convergence gain setting value Default value: 0101110 *: preset, V DD : PWM driver supply voltage

– 165 – CXD3027R $37 (preset: $37 50 BA) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT FZSH, FZSL: FZC (Focus Zero Cross) slice level Default value: 01 (1/8 · VDD /2, VDD : supply voltage); FE input conversion FZSH 1/4 · V DD /2 1/8 · VDD /2 1/16 · VDD /2 1/32 · VDD /2 FZSL Slice level SM5 to SM0: Sled move voltage Default value: 010000 ((1 ± 16/64) · VDD /2, VDD : PWM driver supply voltage) Sled drive output conversion AGS: AGCNTL self-stop on/off Default value: 1 (on) AGJ: AGCNTL convergence completion judgment time during low sensitivity adjustment (31/63ms, when MCK = 128Fs) Default value: 0 (63ms) AGGF: Focus AGCNTL internally generated sine wave amplitude (small/large) Default value: 1 (large) AGGT: Tracking AGCNTL internally generated sine wave amplitude (small/large) Default value: 1 (large) AGGF 0 (small) 1 (large)* 1/32 · VDD /2 1/16 · VDD /2 1/16 · VDD /2 1/8 · VDD /2AGGT 0 (small) 1 (large)* FE/TE input conversion AGV1: AGCNTL convergence sensitivity during high sensitivity adjustment; high/low Default value: 1 (high) AGV2: AGCNTL convergence sensitivity during low sensitivity adjustment; high/low Default value: 0 (low) AGHS: AGCNTL high sensitivity adjustment on/off Default value: 1 (on) AGHT: AGCNTL high sensitivity adjustment time (128/256ms, when MCK = 128Fs) Default value: 0 (256ms) *: preset *: preset

– 166 – CXD3027R $38 (preset: $38 00 00) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0 DC offset cancel. See §5-3. * VCLM: VC level measurement (on/off) VCLC: VC level compensation for FCS In register (on/off) * FLM: Focus zero level measurement (on/off) FLC0: Focus zero level compensation for FZC register (on/off) * RFLM: RF zero level measurement (on/off) RFLC: RF zero level compensation (on/off) Automatic gain control. See §5-6. AGF: Focus auto gain adjustment (on/off) AGT: Tracking auto gain adjustment (on/off) Misoperation prevention circuit DFSW: Defect disable switch (on/off) Setting this switch to 1 (on) disables the defect countermeasure circuit. LKSW: Lock switch (on/off) Setting this switch to 1 (on) disables the sled free-running prevention circuit. DC offset cancel. See §5-3. TBLM: Traverse center measurement (on/off) * TCLM: Tracking zero level measurement (on/off) FLC1: Focus zero level compensation for FCS In register (on/off) TLC2: Traverse center compensation (on/off) TLC1: Tracking zero level compensation (on/off) TLC0: VC level compensation for TRK/SLD In register (on/off) Note) Commands marked with * are accepted every 2.9ms. (when MCK = 128Fs) All commands are on when 1.

– 167 – CXD3027R Coefficient RAM address D15 D14 D13 D12 D11 D10 D9 D8 DAC SD6 SD5 SD4 SD3 SD2 SD1 SD0 When $3A command SVDA = 0 DAC: Serial data readout DAC mode setting. When 0, serial data cannot be read out. (default) When 1, serial data can be read out. SD6 to SD0: These bits select the serial readout data. $39 (preset: $390000) D14 D13 D12 D11 D10 D9 D8 Readout data Readout data lengthSD6 SD5 SD4 SD3 SD2 SD1 SD0 Coefficient RAM data Data RAM data RF AVRG register RFDC input signal FCS Bias register TRVSC register DFCT count VC AVRG register FE AVRG register TE AVRG register RFDC (Bottom) RFDC (Peak) RFDC (Peak – Bottom) FE input signal TE input signal SE input signal VC input signal 8 bits 16 bits 8 bits 8 bits 9 bits 9 bits 8 bits 8 bits 8 bits 8 bits 9 bits 9 bits 9 bits 8 bits 8 bits 8 bits 8 bits Data RAM address1 *: don't care Note) When $3A SVDA is changed, select the readout data again.

– 168 – CXD3027R Data RAM address When $3A command SVDA = 1 DAC: This command selects whether to set readout data for the left or right channel. When 0, right channel readout data is selected. (default) When 1, left channel readout data is selected. SD6 to SD0: These bits select the data to be output from the left or right channel. D14 D13 D12 D11 D10 D9 D8 Readout data Readout data lengthSD6 SD5 SD4 SD3 SD2 SD1 SD0 Data RAM data RF AVRG register RFDC input signal FCS Bias register TRVSC register VC AVRG register FE AVRG register TE AVRG register FE input signal TE input signal SE input signal VC input signal 16 bits 8 bits 8 bits 9 bits 9 bits 9 bits 9 bits 9 bits 8 bits 8 bits 8 bits 8 bits *: don't care

1 Right channel preset

*2 Left channel preset Note) Coefficient RAM data cannot be output from the audio DAC side. Do not output RFDC (peak, bottom, peak-bottom) or the DFCT count from the audio DAC side. When $3A SVDA is changed, select the readout data again. The DFCT count counts the number of times the DFCT signal rises while $3994 is set. Readout outputs the DFCT count at that time.

– 169 – CXD3027R $3A (preset: $3A0000) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 FBON FBSS FBUP FBV1 FBV0 FIFZC TJD0 FPS1 FPS0 TPS1 TPS0 SVDA SJHD INBK MTI0

FIFZC: This selects the FZC slice level setting command. When 0, the FZC slice level is determined by the $37 FZSH and FZSL setting values. (default) When 1, the FZC slice level is determined by the $3F8 FIFZB3 to FIFZB0 and FIFZA3 to FIFZA0 setting values. This allows more detailed setting and the addition of hysteresis compared to the $37 FZSH and FZSL setting. TJDO: This sets the tracking servo filter data RAM to 0 when switched from track jump to servo on only when SFJP = 1 (during surf jump operation). FPS1, FPS0: Gain setting when transferring data from the focus filter to the PWM block. TPS1, TPS0: Gain setting when transferring data from the tracking filter to the PWM block. These are effective for increasing the overall gain in order to widen the servo band, etc. Operation when FPS1, FPS0 (TPS1, TPS0) = 00 is the same as usual (7-bit shift). However, 6dB, 12dB and 18dB can be selected independently for focus and tracking by setting the relative gain to 0dB when FPS1, FPS0 (TPS1, TPS0) = 00. The counter changes once for each sampling cycle of the focus servo filter. When MCK is 128Fs, the sampling frequency is 88.2kHz. When converted to FE input, 1 step is approximately 1/2 9 · VDD /2, VDD = supply voltage. FBV1 FBV0 Number of steps per cycle FPS1 FPS0 0dB +6dB +12dB +18dB Relative gain TPS1 TPS0 0dB +6dB +12dB +18dB Relative gain *: preset *: preset FBON: FBIAS (focus bias) register operation setting. FBSS FBUP FBON FBIAS (focus bias) register addition off. FBIAS (focus bias) register addition on. FBIAS register acts as a down counter. FBIAS register acts as an up counter. FBSS FBUP Processing FBV1, FBV0: FBIAS (focus bias) counter voltage switching. The number of FCS BIAS count-up/-down steps per cycle is decided by these bits.

– 170 – CXD3027R $3B (preset: $3B E0 50) SFOX, SFO2, SFO1: FOK slice level Default value: 011 (28/256 · V DD /2, VDD = supply voltage) RFDC input conversion SFOX 16/256 · V DD /2 20/256 · VDD /2 24/256 · VDD /2 28/256 · VDD /2 32/256 · VDD /2 40/256 · VDD /2 48/256 · VDD /2 56/256 · VDD /2 SFO2 SFO1 Slice level D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT 0 0 0 *: preset SDF2, SDF1: DFCT slice level Default value: 10 (0.0313 · VDD ) RFDC input conversion SDF2 0.0156 · V DD 0.0234 · VDD 0.0313 · VDD 0.0391 · VDD SDF1 Slice level MAX2, MAX1: DFCT maximum time (MCK = 128Fs) Default value: 00 (no timer limit) MAX2 No timer limit 2.00ms 2.36 2.72 MAX1 DFCT maximum time *: preset, V DD : supply voltage *: preset SVDA: This allows the data set by the $39 command to be output through the audio DAC. When 0, audio is output. (default) When 1, the data set by the $39 command is output. SJHD: This holds the tracking filter output at the value when surf jump starts during surf jump. INBK: When INBK = 0 (off), the brake circuit masks the tracking drive signal with the TRKCNCL signal which is generated by taking the MIRR signal at the TZC edge. When INBK = 1 (on), the tracking filter input is masked instead of the drive output. MTI0: The tracking filter input is masked when the MIRR signal is high by setting MTI0 = 1 (on).

– 171 – CXD3027R D1V2, D1V1: Peak hold 1 for DFCT signal generation Count-down speed setting Default value: 01 (0.688 · V DD /ms, 352.8kHz) [V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the operating frequency of the internal counter. RINT: This initializes the initial-stage registers of the circuits which generate MIRR, DFCT and FOK. D2V2 22.05 44.1 88.2 176.4 0.0431 · V DD 0.0861 · VDD 0.172 · VDD 0.344 · VDD D2V1 Count-down speed [V/ms] [kHz] [V/ms] [kHz] 176.4 352.8 705.6 1411.2 0.344 · V DD 0.688 · VDD 1.38 · VDD 2.75 · VDD D1V2 D1V1 Count-down speed *: preset, VDD : supply voltage *: preset, VDD : supply voltage BTF: Bottom hold double-speed count-up mode for MIRR signal generation On/off (default: off) On when 1. D2V2, D2V1: Peak hold 2 for DFCT signal generation Count-down speed setting Default value: 01 (0.086 · V DD /ms, 44.1kHz) [V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the operating frequency of the internal counter.

– 172 – CXD3027R $3C (preset: $3C 00 80) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 COSS COTS CETZ CETF COT2 COT1 MOT2 0 BTS1 BTS0 MRC1 MRC0 0 0 0 0 COSS, COTS: These select the TZC signal used when generating the COUT signal. STZC is the TZC generated by sampling the TE signal at 700kHz. (when MCK = 128Fs) DTZC is the delayed phase STZC. (The delay time can be selected by D14 of $36.) HPTZC is the fast phase TZC passed through a HPF with a cut-off frequency of 1kHz. See §5-13. CETZ: Normally, the input from the TE pin enters the TRK filter and is used to generate the TZC signal. However, the input from the CE pin can also be used. This function is for the center error servo. When 0, the TZC signal is generated by using the signal input to the TE pin. When 1, the TZC signal is generated by using the signal input to the CE pin. CETF: When 0, the signal input to the TE pin is input to the TRK servo filter. When 1, the signal input to the CE pin is input to the TRK servo filter. These commands output the TZC signal. COT2, COT1: The COUT signal is replaced by the TZC signal. Concretely, the TZC signal is output from the COUT pin and the TZC signal is used for auto sequence instead of the COUT signal. COSS STZC HPTZC DTZC COTS TZC *: preset, —: don't care BTS1 BTS0 Number of count-up steps per cycle MRC1 5.669 * 11.338 22.675 45.351 MRC0 Setting time [µs] *: preset (when MCK = 128Fs) MOT2: The MIRR signal is replaced by the STZC signal. Concretely, the STZC signal is output from the MIRR pin and the STZC signal is used for generating the COUT signal instead of the MIRR signal. These commands set the MIRR signal generation circuit. BTS1, BTS0: These set the count-up speed for the bottom hold value of the MIRR generation circuit. The time per step is approximately 708ns (when MCK = 128Fs). The preset value is BTS1 = 1, BTS0 = 0 like the CXD2586R. These bits are valid only when BTF of $3B is 0. MRC1, MRC0: These set the minimum pulse width for masking the MIRR signal of the MIRR generation circuit. As noted in §5-9, the MIRR signal is generated by comparing the waveform obtained by subtracting the bottom hold value from the peak hold value with the MIRR comparator level. Strictly speaking, however, for MIRR to become high, these levels must be compared continuously for a certain time. These bits set that time. The preset value is MRC1 = 0, MRC0 = 0 like the CXD2586R. COT2 STZC HPTZC COUT COT1 COUT pin output *: preset, —: don't care*

– 173 – CXD3027R $3D (preset: $3D 00 00) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SFID SFSK THID THSK ABEF TLD2 TLD1 TLD0 0 0 0 0 0 0 0 0 SFID: SLED servo filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK filter second-stage output. When the low frequency component of the tracking error signal obtained from the RF amplifier is attenuated, the low frequency can be amplified and input to the SLD servo filter. SFSK: Only during TRK servo gain up2 operation, coefficient K30 is used instead of K00. Normally, the DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain up2, and error occurs in the DC level at M0D. In this case, the DC level of the signal transmitted to M00 can be kept uniform by adjusting the K30 value even during the above switching. THID: TRK hold filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK filter second-stage output. When signals other than the tracking error signal from the RF amplifier are input to the SE input pin, the signal transmitted from the TE pin can be obtained as TRK hold filter input. THSK: Only during TRK servo gain up2 operation, coefficient K46 is used instead of K40. Normally, the DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain up2, and error occurs in the DC level at M0D. In this case, the DC level of the signal transmitted to M18 can be kept uniform by adjusting the K46 value even during the above switching. * See "§5-20. Filter Composition" regarding the SFID, SFSK, THID and THSK commands. ABEF: The focus error (FE) and tracking error (TE) can be generated internally. When 0, the FE and TE signal input mode results. Input each error signal through the FE and TE pins. (default) When 1, the FE and TE signal generation mode results and the FE and TE signals are generated internally. TLD0 to 2: These turn on and off SLD filter correction independently of the TRK filter. See $38 (TLC0 to TLC2) and Fig. 5-3. TLC0 OFF ON OFF OFF ON ON TLD0 VC level correction TRK filter SLD filter *: preset, —: don't care TLC1 OFF ON OFF OFF ON ON TLD1 Tracking zero level correction TRK filter SLD filter TLC2 OFF ON OFF OFF ON ON TLD2 Traverse center correction TRK filter SLD filter

– 174 – CXD3027R

Input coefficient sign inversion when SFID = 1 and THID = 1 The preset coefficients for the TRK filter are negative for input and positive for output. With this, the CXD3027R outputs servo drives which have the reversed phase of input errors. K19 TR K filter K22 N egative input coefficient Positive output coefficient TE K00 SLD filter K05 N egative input coefficient Positive output coefficient SE K40 TR K H old filter K45 Positive input coefficient Positive output coefficient TR K H old When SFID = 1, the TRK filter negative input coefficient is applied to the SLD filter, so the SLD input coefficient (K00) sign must be inverted. (For example, inverting the sign for coefficient K00: E0h results in 20h.) For the same reason, when THID = 1, the TRK hold input coefficient (K40) sign must be inverted. K19 TR K filter K22 N egative input coefficient Positive output coefficient TE K00 SLD filter K05 Positive input coefficient Positive output coefficient SE K40 TR K H old filter K45 N egative input coefficient Positive output coefficient TR K H old M O D * For TRK servo gain normal See §5-20. Filter Composition".

– 175 – CXD3027R $3E (preset: $3E 00 00) F1NM, F1DM: Quasi double accuracy setting for FCS servo filter first-stage On when 1; default is 0. F1NM: Gain normal F1DM: Gain down T1NM, T1UM: Quasi double accuracy setting for TRK servo filter first-stage On when 1; default is 0. T1NM: Gain normal T1UM: Gain up F3NM, F3DM: Quasi double accuracy setting for FCS servo filter third-stage On when 1; default is 0. Generally, the advance amount of the phase increases by partially setting the FCS servo third- stage filter which is used as the phase compensation filter to double accuracy. F3NM: Gain normal F3DM: Gain down T3NM, T3UM: Quasi double accuracy setting for TRK servo filter third-stage On when 1; default is 0. Generally, the advance amount of the phase increases by partially setting the TRK servo third- stage filter which is used as the phase compensation filter to double accuracy. T3NM: Gain normal T3UM: Gain up Note) Filter first- and third-stage quasi double accuracy settings can be set individually. See "§5-20 Filter Composition" at the end of this specification concerning quasi double accuracy. DFIS: FCS hold filter input extraction node selection 0: M05 (Data RAM address 05); default 1: M04 (Data RAM address 04) TLCD: This command masks the TLC2 command set by D2 of $38 only when FOK is low. On when 1; default is 0 LKIN: When 0, the internally generated LOCK signal is output to the LOCK pin. (default) When 1, the LOCK signal can be input from an external source to the LOCK pin. COIN: When 0, the internally generated COUT signal is output to the COUT pin. (default) When 1, the COUT signal can be input from an external source to the COUT pin. The MIRR, DFCT and FOK signals can also be input from an external source. MDFI: When 0, the MIRR, DFCT and FOK signals are generated internally. (default) When 1, the MIRR, DFCT and FOK signals can be input from an external source through the MIRR, DFCT and FOK pins. MIRI: When 0, the MIRR signal is generated internally. (default) When 1, the MIRR signal can be input from an external source through the MIRR pin. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD 0 LKIN COIN MDFI MIRI XT1D XT1D: The input to the servo master clock is used without being frequency-divided by setting XT1D to 1. This command takes precedence over the XTSL pin, XT2D and XT4D. See the description of $3F for XT2D and XT4D. MDFI MIRR, DFCT and FOK are all generated internally. MIRR only is input from an external source. MIRR, DFCT and FOK are all input from an external source. MIRI *: preset, —: don't care

– 176 – CXD3027R $3F (preset: $3F 00 00) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 AGG4 XT4D XT2D 0 DRR2 DRR1 DRR0 0 ASFG FTQ LPAS SRO1 0 AGHF ASOT

XT4D, XT2D: MCK (digital servo master clock) frequency division ratio setting This command forcibly sets the frequency division ratio to 1/4, 1/2 or 1/1 when MCK is generated. See the description of $3E for XT1D. Also, see "§5-2. Digital Servo Block Master Clock (MCK)". AGG4: This varies the amplitude of the internally generated sine wave using the AGGF and AGGT commands during AGC. When AGG4 = 0, the default is used. When AGG4 = 1, the setting is as shown in the table below. AGG4 AGGF AGGT FE input conversion 1/32 · V DD /2 1/16 · VDD /2* TE input conversion 1/16 · VDD /2 1/8 · VDD /2* DRR2 to DRR0: Partially clears the Data RAM values (0 write). The following values are cleared when 1 (on) respectively; default is 0 DRR2: M08, M09, M0A DRR1: M00, M01, M02 DRR0: M00, M01, M02 only when LOCK = low Note) Set DRR1 and DRR0 on for 50µs or more. ASFG: When vibration detection is performed during anti-shock circuit operation, the FCS servo filter is forcibly set to gain normal status. On when 1; default is 0 FTQ: The slope of the output during focus search is 1/4 the conventional output slope. On when 1; default is 0 See $37 for AGGF and AGGT. The presets are AGG4 = 0, AGGF = 1 and AGGT = 1. *: preset, —: don't care XT1D XT2D XT4D According to XTSL Frequency division ratio Sine wave amplitude 1/64 · VDD /2 1/32 · VDD /2 1/16 · VDD /2 1/8 · VDD /2 *: preset, —: don't care

– 177 – CXD3027R SOLK XOLT SOUT Output from XPCK pin. Output from GFS pin. Output from XUGF pin. SRO1 = 1 AGHF: This halves the frequency of the internally generated sine wave during AGC. ASOT: The anti-shock signal, which is internally detected, is output from the ATSK pin. Output when 1; default is 0. Vibration detection when a high signal is output for the anti-shock signal output. LPAS: Built-in analog buffer low-current consumption mode This mode reduces the total analog buffer current consumption for the VC, TE, SE and FE input analog buffers by using a single operational amplifier. On when 1; default is 0 Note) When using this mode, first check whether each error signal is properly A/D converted using data readout, etc. SRO1: This command is used to continuously externally output various data inside the digital servo block which have been specified with the $39 command. (However, D15 (DAC) of $39 must be set to 1.) Digital output (SOCK, XOLT and SOUT) can be obtained from three specified pins by setting this command to 1.

– 178 – CXD3027R $3F8 (preset: $3F8800) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 SYG3 SYG2 SYG1 SYG0 FIFZB3 FIFZB2 FIFZB1 FIFZB0 FIFZA3 FIFZA2 FIFZA1 FIFZA0 SYG3 to SYG0: These simultaneously set the focus drive, tracking drive and sled drive output gains. See the $AF and $CX commands for the spindle drive output gain setting. SYG3 0 (–∞ dB) 0.125 (–18.1dB) 0.250 (–12.0dB) 0.375 (–8.5dB) 0.500 (–6.0dB) 0.625 (–4.1dB) 0.750 (–2.5dB) 0.875 (–1.2dB) 1.000 (0.0dB) 1.125 (+1.0dB) 1.250 (+1.9dB) 1.375 (+2.8dB) 1.500 (+3.5dB) 1.625 (+4.2dB) 1.750 (+4.9dB) 1.875 (+5.5dB) SYG2 SYG1 SYG0 GAIN *: preset FIFZB3 to FIFZB0: This sets the slice level at which FZC changes from high to low. FIFZA3 to FIFZA0: This sets the slice level at which FZC changes from low to high. The FIFZB3 to FIFZB0 and FIFZA3 to FIFZA0 setting values are valid only when $3A FIFZC is 1. Set so that the FIFZB3 to FIFZB0 ≤ FIFZA3 to FIFZA0. Hysteresis can be added to the slice level by setting FIFZB3 to FIFZB0 < FIFZA3 to FIFZA0. FZC slice level = · 0.5 · V DD [V]FIFZB3 to FIFZB0 or FIFZA3 to FIFZA0 setting value

– 179 – CXD3027R Description of Data Readout SO C K (5.6448M H z) XO LT (88.2kH z) SO U T M SB LSB M SB LSB... ... 16-bit register for serial/parallel conversion 16-bit register for latch SO U T SO C K XO LT C LK C LK M SB LSB To the 7-segm ent LED To the 7-segm ent LED D ata is connected to the 7-segm ent LED by 4-bits at a tim e. This enables H ex display using four 7-segm ent LED s. M SB LSB SO U T SO C K XO LT Serial data input C lock input Latch enable input Analog output D /A To an oscilloscope, etc. O ffset adjustm ent, gain adjustm ent W aveform s can be m onitored w ith an oscilloscope using a serial input-type D /A converter as show n above.

– 180 – CXD3027R §5-19. List of Servo Filter Coefficients <Coefficient Preset Value Table (1)> ADDRESS K00 K01 K02 K03 K04 K05 K06 K07 K08 K09 K0A K0B K0C K0D K0E K0F SLED INPUT GAIN SLED LOW BOOST FILTER A-H SLED LOW BOOST FILTER A-L SLED LOW BOOST FILTER B-H SLED LOW BOOST FILTER B-L SLED OUTPUT GAIN FOCUS INPUT GAIN SLED AUTO GAIN FOCUS HIGH CUT FILTER A FOCUS HIGH CUT FILTER B FOCUS LOW BOOST FILTER A-H FOCUS LOW BOOST FILTER A-L FOCUS LOW BOOST FILTER B-H FOCUS LOW BOOST FILTER B-L FOCUS PHASE COMPENSATE FILTER A FOCUS DEFECT HOLD GAIN K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K1A K1B K1C K1D K1E K1F K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K2A K2B K2C K2D K2E K2F FOCUS PHASE COMPENSATE FILTER B FOCUS OUTPUT GAIN ANTI SHOCK INPUT GAIN FOCUS AUTO GAIN HPTZC / Auto Gain HIGH PASS FILTER A HPTZC / Auto Gain HIGH PASS FILTER B ANTI SHOCK HIGH PASS FILTER A HPTZC / Auto Gain LOW PASS FILTER B Fix* TRACKING INPUT GAIN TRACKING HIGH CUT FILTER A TRACKING HIGH CUT FILTER B TRACKING LOW BOOST FILTER A-H TRACKING LOW BOOST FILTER A-L TRACKING LOW BOOST FILTER B-H TRACKING LOW BOOST FILTER B-L TRACKING PHASE COMPENSATE FILTER A TRACKING PHASE COMPENSATE FILTER B TRACKING OUTPUT GAIN TRACKING AUTO GAIN FOCUS GAIN DOWN HIGH CUT FILTER A FOCUS GAIN DOWN HIGH CUT FILTER B FOCUS GAIN DOWN LOW BOOST FILTER A-H FOCUS GAIN DOWN LOW BOOST FILTER A-L FOCUS GAIN DOWN LOW BOOST FILTER B-H FOCUS GAIN DOWN LOW BOOST FILTER B-L FOCUS GAIN DOWN PHASE COMPENSATE FILTER A FOCUS GAIN DOWN DEFECT HOLD GAIN FOCUS GAIN DOWN PHASE COMPENSATE FILTER B FOCUS GAIN DOWN OUTPUT GAIN NOT USED NOT USED DATA CONTENTS * Fix indicates that normal preset values should be used.

– 181 – CXD3027R <Coefficient Preset Value Table (2)> ADDRESS K30 K31 K32 K33 K34 K35 K36 K37 K38 K39 K3A K3B K3C K3D K3E K3F SLED INPUT GAIN (Only when TRK gain up2 is accessed with SFSK = 1.) ANTI SHOCK LOW PASS FILTER B NOT USED ANTI SHOCK HIGH PASS FILTER B-H ANTI SHOCK HIGH PASS FILTER B-L ANTI SHOCK FILTER COMPARATE GAIN TRACKING GAIN UP2 HIGH CUT FILTER A TRACKING GAIN UP2 HIGH CUT FILTER B TRACKING GAIN UP2 LOW BOOST FILTER A-H TRACKING GAIN UP2 LOW BOOST FILTER A-L TRACKING GAIN UP2 LOW BOOST FILTER B-H TRACKING GAIN UP2 LOW BOOST FILTER B-L TRACKING GAIN UP PHASE COMPENSATE FILTER A TRACKING GAIN UP PHASE COMPENSATE FILTER B TRACKING GAIN UP OUTPUT GAIN NOT USED K40 K41 K42 K43 K44 K45 K46 K47 K48 K49 K4A K4B K4C K4D K4E K4F TRACKING HOLD FILTER INPUT GAIN TRACKING HOLD FILTER A-H TRACKING HOLD FILTER A-L TRACKING HOLD FILTER B-H TRACKING HOLD FILTER B-L TRACKING HOLD FILTER OUTPUT GAIN TRACKING HOLD FILTER INPUT GAIN (Only when TRK gain up2 is accessed with THSK = 1.) NOT USED FOCUS HOLD FILTER INPUT GAIN FOCUS HOLD FILTER A-H FOCUS HOLD FILTER A-L FOCUS HOLD FILTER B-H FOCUS HOLD FILTER B-L FOCUS HOLD FILTER OUTPUT GAIN NOT USED NOT USED DATA CONTENTS

– 182 – CXD3027R §5-20. Filter Composition The internal filter composition is shown below. K : Coefficient RAM address, M: Data RAM address K0D K0C K0E K10 Z – 1 K0B K09 K0A M 04M 03 2 – 7 M 06 Z – 1 K11 K13 FC S AU TO G ain M 072 – 1 K06 AG FO N K06 D FC TFC S H old R eg2 FC S In R eg Sin R O M K08 Z – 1 M 05 K29 K28 K2A K2C Z – 1 K27 Z – 1 K25 K26 M 04M 03 2 – 7 2 – 7 M 06 Z – 1 K2D K13 FSC AU TO G ain M 072 – 1 K06 D FC TFC S H old R eg2 FC S In R eg K24 Z – 1 M 05 2 – 7 FC S Servo G ain D ow n fs = 88.2kH z N ote) Set the M SB bit of the K0B and K0D coefficients to 0. N ote) Set the M SB bit of the K27 and K29 coefficients to 0. FC S Servo G ain N orm al fs = 88.2kH z PW M BK2 Z – 1 Z – 1 FC S SR C H BK1 BK5 Z – 1 Z – 1 BK4 FPS1, 0 BK3 BK6 K0F M 1E To FC S H oldK0F M 1F To FC S H old K2B M 1E To FC S H oldK2B M 1F To FC S H old Z – 1

– 183 – CXD3027R K1F K1E K20 K21 K1D K1B K1C M 0CM 0B 2 – 7 M 0E K22 K23 TR K AU TO G ain M 0F2 – 1 K19 AG TO N K19 D FC TTR K H old R eg TR K In R eg Sin R O M K1A M 0D To SLD Servo, TR K H old K3DK1B K3C M 0CM 0B K3E K23 TR K AU TO G ain M 0F2 – 1 K19 D FC T TR K H old R eg TR K In R eg K1A M 0E 2 – 7 TR K Servo G ain U p1 fs = 88.2kH z N ote) Set the M SB bit of the K1D and K1F coefficients to 0. K3B K3A K3C K3D K39 K37 K38 M 0CM 0B 2 – 7 M 0E K3E K23 TR K AU TO G ain M 0F2 – 1 K19 D FC T TR K H old R eg TR K In R eg K36 M 0D 2 – 7 TR K Servo G ain U p2 fs = 88.2kH z N ote) Set the M SB bit of the K39 and K3B coefficients to 0. TR K Servo G ain N orm al fs = 88.2kH z BK2 TR K JM P BK1 BK5BK4 BK8BK7 TPS1, 0 BK9 BK3 BK6 PW M Z – 1Z – 1Z – 1Z – 1Z – 1Z – 1 Z – 1Z – 1 Z – 1 Z – 1 Z – 1Z – 1 Z – 1 Z – 1 Z – 1 Z – 1 Z – 1

– 184 – CXD3027R K0D K0C 80H K10 K0B 7FH K0A M 03 2 – 7 M 06 K11 K13 FC S AU TO G ain M 072 – 1 K06 AG FO N K06 D FC TFC S H old R eg 2 FC S In R eg Sin R O M 81H 2 – 1 K06 D FC T FC S H old R eg 2 FC S In R eg 2 – 7 N ote) Set the M SB bit of the K0B and K0D coefficients during norm al operation, and of the K08, K09 and K0E coefficients during quasi double accuracy to 0. FC S Servo G ain N orm al; fs = 88.2kH z, during quasi double accuracy (Ex.: $3EA XX0) K0E 2 – 7 K09 2 – 7 K08 2 – 7 K29 K28 80H K2C K27 7FH K26 M 03 2 – 7 M 06 K2D K13 FC S AU TO G ain M 07 81H 2 – 7 K2A 2 – 7 K25 2 – 7 K24 2 – 7 N ote) Set the M SB bit of the K27 and K29 coefficients during norm al operation, and of the K24, K25 and K2A coefficients during quasi double accuracy to 0. FC S Servo G ain N orm al; fs = 88.2kH z, during quasi double accuracy (Ex.: $3E5XX0) ∗ ∗ ∗ ∗ ∗ BK2 FC S SR C H BK1 BK5BK4 FPS1, 0 PW M BK3 BK6 ∗ 81h, 7Fh and 80h are each H ex display 8-bit fixed values w hen set to quasi double accuracy. M 04 M 05 M 04 M 05 K0F M 1E To FC S H oldK0F M 1F To FC S H old K2B M 1E To FC S H oldK2B M 1F To FC S H old Z – 1 Z – 1 Z – 1 Z – 1 Z – 1 Z – 1 Z – 1 Z – 1 Z – 1Z – 1Z – 1Z – 1

– 185 – CXD3027R 2 – 1 K19 AG TO N K19 D FC TTR K H old R eg TR K In R eg Sin R O M 2 – 1 K19 D FC TTR K H old R eg TR K In R eg 2 – 1 K19 D FC TTR K H old R eg TR K In R eg K1F K1E 80H K21 K1D 7FH K1C M 0CM 0B 2 – 7 M 0E K22 K23 TR K AU TO G ain M 0F 81H M 0D 2 – 7 K20 2 – 7 K1B 2 – 7 K1A 2 – 7 K3D K3C 7FH 80H M 0CM 0B K3E K23 TR K AU TO G ain M 0F 81H 2 – 7 K1B 2 – 7 K1A 2 – 7 K3B K3A 80H K3D K39 7FH K38 M 0CM 0B 2 – 7 M 0E K3E K23 TR K AU TO G ain M 0F 81H M 0D 2 – 7 K3C 2 – 7 K37 2 – 7 K36 2 – 7 N ote) Set the M SB bit of the K1D and K1F coefficients during norm al operation, and of the K1A, K1B and K20 coefficients during quasi double accuracy to 0. N ote) Set the M SB bit of the K1A, K1B and K3C coefficients during quasi double accuracy to 0. N ote) Set the M SB bit of the K39 and K3B coefficients during norm al operation, and of the K36, K37 and K3C coefficients during quasi double accuracy to 0. TR K Servo G ain N orm al; fs = 88.2kH z, during quasi double accuracy (Ex.: $3EXA X0) TR K Servo gain up1; fs = 88.2kH z, during quasi double accuracy (Ex.: $3EX5X0) TR K Servo gain up2; fs = 88.2kH z, during quasi double accuracy (Ex.: $3EX5X0) ∗ ∗ ∗ M 0E ∗ ∗ ∗ ∗ ∗ ∗ BK2 PW M TR K JM P BK1 BK5BK4 TPS1, 0 BK8BK7 BK3 BK6 BK9 ∗ 81h, 7Fh and 80h are each H ex display 8-bit fixed values w hen set to quasi double accuracy. Z – 1Z – 1 Z – 1Z – 1Z – 1Z – 1 Z – 1Z – 1Z – 1Z – 1Z – 1 Z – 1Z – 1Z – 1 Z – 1Z – 1Z – 1 Z – 1

– 186 – CXD3027R SLD Servo fs = 345Hz K04 K03 Z – 1 K02 Z – 1 K01 K00 M 00 2 – 7 2 – 7 M 01 K05 K07 TR K AU TO G ain PW M SLD M O V M 02 SLD In R eg 2 – 1 K30 SFSK (only w hen TG up2 is used.) SFIDM 0D TR K SER VO FILTER Second-stage output Note) Set the MSB bit of the K02 and K04 coefficients to 0. HPTZC/Auto Gain fs = 88.2kHz K15 K17 Z – 1 K14 M 08 M 09 M 0A Z – 1 AU TO G ain R eg 2 – 1 AG TO N AG FO N AG FO N FC S In R eg TR K In R eg Sin R O M Z – 1 Slice TZC R egSlice 2 – 1

– 187 – CXD3027R Anti Shock fs = 88.2kHz K34 K33 Z – 1Z – 1 K31 K16 Z – 1 M 09M 08 2 – 7 M 0A K35 C om pK12 Anti Shock R eg 2 – 1 TR K In R eg Note) Set the MSB bit of the K34 coefficient to 0. The comparator level is 1/16 the maximum amplitude of the comparator input. AVRG fs = 88.2kHz M 08 AVR G R eg 2 – 1 VC , TE, FE, R FD C Z – 1 2 – 7 TRK Hold fs = 345Hz K44 K43 Z – 1 K42 Z – 1 K41 K40 M 18 2 – 7 2 – 7 M 19 K45 TR K H old R egSLD In R eg 2 – 1 K46 TH SK (only w hen TG up2 is used) TH IDM 0D TR K SER VO FILTER Second-stage output Note)Set the MSB bit of the K42 and K44 coefficients to 0. FCS Hold fs = 345Hz K4C K4B Z – 1 K4A Z – 1 K49 K48 M 10 2 – 7 2 – 7 M 11 K4D FC S H old R eg 2K0FM 05 K2B K2B w hen using the FC S G ain D ow n filterD FIS ($3E)M 04 FC S SER VO FILTER First-stage output FC S SER VO FILTER Second-stage output M 1F M 1E M 12 Note)Set the MSB bit of the K4A and K4C coefficients to 0.

– 188 – CXD3027R §5-21. TRACKING and FOCUS Frequency Response f – Frequency [H z] 20k1k100102.1 –10 G – Gain [dB] –180° φ – Phase [degree] 180° 90° –90° FO C U S frequency response φ G f – Frequency [H z] 20k1k100102.1 –10 G – Gain [dB] –180° φ – Phase [degree] 180° 90° –90° TR A C K IN G frequency response φ G N O R M AL G AIN D O W N N O R M AL G AIN U P When using the preset coefficients with the boost function off. When using the preset coefficients with the boost function off.

– 189 – CXD3027R LO C K TEST1 TEST2 TEST3 C 176 M D S C O U T M IR R LRMU SBSO R4M D FC T D river setting WDCK XUGF XPCK C2PO WFCK DOUT BCK PCMD LRCK XC AS XW E XO E VD D XR AS VSS D 3 D 2 D 1 D 0 XWRE XRDE XEMP XWIH XQOK SQSO SQCK SCSY SCOR XRST MUTE DATA XLAT CLOK SENS SCLK XSOE GFS FOK PWMI LDON VDD GND SLED SPD L G N D SSTP +3.3V FZC FE TE C E FG TD TG FD LD O N VC C G N D R FO VC 70 69 68 67 63646566 61627172737481828384 7576777888 87 86 85 79808990 BCK PCMDI VDD2 WFCK C2PO GFS XUGF WDCK VSS2 XTSL AVDD3 ASYO ASYI BIAS CLTV PCO FILI FILO VCTL VPCO VC FE DOUT XPCK AVSS3 SE RFAC LRCKI LRCK PCMD 100 101 102 103 104 105 106 107 108 111 109 110 112 113 114 115 116 117 118 119 120 D VD D A10 A11 XR AS XW E D 0 D 3 D 2 XC AS XO E AVD D 1 LO U T1 AIN 1 AO U T1 AVSS1 AVSS2 AO U T2 AIN 2 LO U T2 AVD D 2 XTAI XTAO XVSS D 1 XVD D BC KI 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 301A9 XWRE XRDE XEMP XWIH XQOK LRMU SQSO SQCK SCSY SCOR VSS0 SBSO EXCK XRST SYSM DATA XLAT CLOK SENS SCLK XSOE R4M DVSS ATSK M D P C 176 VD D 1 TEST3 TEST2 TEST1 LO C K FO K D FC T M IR R C O U T VD D 0 AVD D 0 TES1 TEST VSS1 FR D R FFD R TR D R TFD R SR D R SFD R SSTP M D S R FD C AVSS0 IG EN PW M I C E TE C XD 3027R 4M D R AM or 16M D R AM [6] Application Circuit Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 190 – CXD3027R Package Outline Unit: mm SO N Y C O D E EIAJ C O D E JED EC C O D E PAC KAG E STR U C TU R E PAC KAG E M ATER IAL LEAD TR EATM EN T LEAD M ATER IAL PAC KAG E M ASS EPO XY R ESIN SO LD ER PLATIN G C O PPER ALLO Y 0.5 0.22 ± 0.05 M0.1 D ETAIL A D ETAIL B 0.22 ± 0.05 (0.2) (0.125) 0.145 ± 0.03

1.7 M AX

1.4 ± 0.1 B A 120PIN LQ FP (PLASTIC ) LQ FP-120P-L01 LQ FP120-P-1616 0.8g 1 30 6190 120 0.1 S S S 18.0 ± 0.2 16.0 ± 0.1 (17.0) (0.5) 0° to 10° 0.1 ± 0.05 0.6 ± 0.15 0.25 120 120PIN LQ FP(PLASTIC ) 0.6 ± 0.15 0° to 8° D ETAIL A 0.1 ± 0.05 0.25 b=0.22 ± 0.05 0.145 – 0.03 D ETAIL B + 0.05 1.7 – 0.1 + 0.2 A S S0.08 B 16.0 ± 0.1 18.0 ± 0.2 90 61 300.5 b M S0.08 SO N Y C O D E EIAJ C O D E JED EC C O D E PAC KAG E STR U C TU R E PAC KAG E M ATER IAL LEAD TR EATM EN T LEAD M ATER IAL PAC KAG E W EIG H T EPO XY R ESIN SO LD ER C O PPER ALLO Y LQ FP-120P-L021 P-LQ FP120-16x16-0.5 0.8g

– 191 – CXD3027R Package Outline Unit: mm 120 120PIN LQ FP(PLASTIC ) (0.5) 0° to 10° D ETAIL A 1.7M AX A S S0.10 B 16.0 ± 0.1 18.0 ± 0.2 90 61 300.5 b M S0.10 SO N Y C O D E EIAJ C O D E JED EC C O D E PAC KAG E STR U C TU R E PAC KAG E M ATER IAL LEAD TR EATM EN T LEAD M ATER IAL PAC KAG E W EIG H T EPO XY R ESIN SO LD ER C O PPER ALLO Y LQ FP-120P-L051 P-LQ FP120-16x16-0.5 0.8g b=0.22 ± 0.05 0.17 D ETAIL B 1.4 ± 0.1 0.1 ± 0.05 (17.0) 1.0 ± 0.2 (0.15) (0.2) + 0.08 - 0.05 0.25 0.6 ± 0.15 Sony Corporation

Product Information

CXD3027R specifications and overview.

Summary

CD Digital Signal Processor with Built-in Digital Servo + Shock-Proof Memory Controller + Digital High & Bass Boost

Description

The CXD3027R is a digital signal processor LSI for CD players. This LSI incorporates a digital servo, high & bass boost, shock-proof memory controller, 1-bit DAC and analog low-pass filter.

Source title CXD3027R Datasheet(PDF) - Sony Corporation

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