CXD2585Q

CXD2585Q SONY | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 127

Technical content

Datasheet sections

Features

• All digital signal processings during playback are performed with a single chip
• Highly integrated mounting possible due to a built- in RAM Digital Signal Processor (DSP) Block
• Playback mode supporting CAV (Constant Angular Velocity)
• Frame jitter free
• 0.5
• to 4· continuous playback possible
• Allows relative rotational velocity readout
• Wide capture range playback mode
• Spindle rotational velocity following method
• Supports 1· to 4· playback variable pitch playback
• Bit clock, which strobes the EFM signal, is generated by the digital PLL.
• EFM data demodulation
• Enhanced EFM frame sync signal protection
• Refined super strategy-based powerful error correction C1: double correction, C2: quadruple correction Supported during 4· playback
• Noise reduction during track jumps
• Auto zero-cross mute
• Subcode demodulation and Sub-Q data error detection
• Digital spindle servo
• 16-bit traverse counter
• Asymmetry correction circuit
• CPU interface on serial bus
• Error correction monitor signal, etc. output from a new CPU interface
• Servo auto sequencer
• Fine search performs track jumps with high accuracy
• Digital audio interface output
• Digital level meter, peak meter
• Bilingual supported
• VCO control mode
• CD TEXT data demodulation Digital Servo (DSSP) Block
• Microcomputer software-based flexible servo control
• Offset cancel function for servo error signal
• Auto gain control function for servo loop
• E:F balance, focus bias adjustment function
• Surf jump function supporting micro two-axis
• Tracking filter: 6 stages Focus filter: 5 stages

Applications

• Supply voltage V DD –0.3 to +7.0 V
• Input voltage V I –0.3 to +7.0 V (VSS – 0.3 to VDD + 0.3) V
• Output voltage V O –0.3 to +7.0 V
• Storage temperature Tstg –40 to +125 °C
• Supply voltage difference VSS – AVSS –0.3 to +0.3 V VDD – AVDD –0.3 to +0.3 V Recommended Operating Conditions
• Supply voltage V DD 2.7 to 5.5 V
• Operating temperature Topr –20 to +75 °C Note) The VDD for the CXD2585Q varies according to the playback speed. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. Playback speed CD-DSP block 4· speed 4.75 to 5.25 2· speed 3.0 to 5.5 1· speed 2.7 to 5.5 VDD [V] Input/Output Capacitance
• Input capacitance C I 12 (Max.) pF
• Output capacitance C O 12 (Max.) pF Note) Measurement conditions VDD = VI= 0V fM = 1MHz

– 2 – CXD2585Q Block Diagram D /A Interface Error C orrector 32K R AM D igital O U T Sub C ode Processor C lock G enerator Asym m etry C orrector D igital PLL D igital C LV C PU Interface Servo Auto Sequencer Signal processor block R FAC ASYO ASYE BIAS XPC K FILO FILI PC O C LTV M D P LO C K SEN S D ATA XLAT C LO K SC O R SBSO EXC K SC SY SQ SO SQ C K XR ST TEST TES1 PW M I ASYI FSTO C 4M Servo block SER VO Interface M IR R D FC T FO K SER VO D SP FO C U S SER VO TR AC KIN G SER VO SLED SER VO PW M G EN ER ATO R FO C U S PW M G EN ER ATO R TR AC KIN G PW M G EN ER ATO R SLED PW M G EN ER ATO R R FD C C E TE SE FE VC IG EN O PAm p Analog SW A/D C onverter ADIO FFD R FR D R TFD R TR D R SFD R SR D R SO U T SO C K XO LT SC LK C O U T SSTP ATSK M IR R D FC T FO K XTAI XTAO XTSL V16M VPCO VCTL M UTE BCK PCM D LRCK C2PO W DCK D O U T M D 2 W FCK EM PH GFS XUGF EFM dem odurator 46 29 31417 6765 661011 13 685859 606971 72

– 3 – CXD2585Q Pin Configuration 4142434445464748495051525354555657585960 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 201 D VD D 2 ASYE M D 2 D O U T LR C K PC M D BC K EM PH XTSL D VSS2 XTAI XTAO SO U T SO C K XO LT SQ SO SQ C K SC SY SBSO EXC K SE FE VC TES1 TEST D VSS1 FR D R FFD R D FC T TR D R TFD R SR D R SFD R D VD D 1 FSTO SSTP M D P FO K VPCO V16M VCTL PCO FILO CLTV TEASYO AV DD0 IGEN AV SS0 ADIO RFDC BIAS AV DD1 RFAC ASYI FILI AV SS1 CE XRST CLOK SCLK XLAT M UTE DATA SENS W FCK DV DD0 ATSK M IRR XUGF XPCK GFS C2PO SCOR C4M W DCK DV SS0 COUT LO C K PW M I

– 4 – CXD2585Q Pin Description Pin No. I I I I I O I I/O O O O O O O O O I/O I/O I/O I/O I I/O O I O O O O O O O 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, Z, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 Digital power supply. System reset. Reset when low. Mute input (low: off, high: on) Serial data input from CPU. Latch input from CPU. Serial data is latched at the falling edge. Serial data transfer clock input from CPU. SENS output to CPU. SENS serial data readout clock input. Anti-shock input/output. WFCK output. XUGF output. MNT0 or RFCK is output by switching with the command. XPCK output. MNT1 is output by switching with the command. GFS output. MNT2 or XROF is output by switching with the command. G2PO output. MNT3 or GTOP is output by switching with the command. Outputs a high signal when either subcode sync S0 or S1 is detected. 4.2336MHz output. 1/4 frequency division output for V16M in CAV-W mode or variable pitch mode. Word clock output. f = 2Fs. GRSCOR is output by the command switching. Digital GND. Track count signal I/O. Mirror signal I/O. Detect signal I/O. Focus OK signal I/O. Spindle motor external control input. GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low. Input when LKIN = 1. Spindle motor servo control output. Disc innermost track detection signal input. 2/3 frequency division output for XTAI pin. Digital power supply. Sled drive output. Sled drive output. Tracking drive output. Tracking drive output. Focus drive output. Focus drive output. Digital GND. DV DD 0 XRST MUTE DATA XLAT CLOK SENS SCLK ATSK WFCK XUGF XPCK GFS C2PO SCOR C4M WDCK DV SS 0 COUT MIRR DFCT FOK PWMI LOCK MDP SSTP FSTO DV DD 1 SFDR SRDR TFDR TRDR FFDR FRDR DV SS 1 Symbol I/O Description

– 5 – CXD2585Q I I I I I I I I O I O I I I O I O I I I/O O I I O O O O O I Analog 1, 0 Analog 1, Z, 0 1, 0 1, Z, 0 1, 0 1, 0 1, 0 1, 0 1, 0 Test. Normally, GND. Test. Normally, GND. Center voltage input. Focus error signal input. Sled error signal input. Tracking error signal input. Center servo analog input. RF signal input. Test. No connected. Analog GND. Constant current input for operational amplifier. Analog power supply. EFM full-swing output. (low = Vss, high = V DD ) Asymmetry comparator voltage input. EFM signal input. Analog GND. Multiplier VCO1 control voltage input. Master PLL filter output (slave = digital PLL). Master PLL filter input. Master PLL charge pump output. Analog power supply. Asymmetry circuit constant current input. Wide-band EFM PLL VCO2 control voltage input. Wide-band EFM PLL VCO2 oscillation output. Serves as wide-band EFM PLL clock input by switching with the command. Wide-band EFM PLL charge pump output. Digital power supply. Asymmetry circuit on/off (low = off, high = on). Digital Out on/off control (low = off, high = on). Digital Out output. D/A interface. LR clock output. f = Fs D/A interface. Serial data output (two's complement, MSB first). D/A interface. Bit clock output. Outputs a high signal when the playback disc has emphasis, and a low signal when there is no emphasis. Crystal selection input. Low when the crystal is 16.9344MHz; high when it is 33.8688MHz. Digital GND. TEST TES1 VC FE SE TE CE RFDC ADIO AV SS 0 IGEN AV DD 0 ASYO ASYI RFAC AV SS 1 CLTV FILO FILI PCO AV DD 1 BIAS VCTL V16M VPCO DV DD 2 ASYE MD2 DOUT LRCK PCMD BCK EMPH XTSL DV SS 2 Pin No. Symbol I/O Description

– 6 – CXD2585Q Notes)

• PCMD is a MSB first, two's complement output.
• GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)
• XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before sync protection.
• XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point coincide.
• The GFS signal goes high when the frame sync and the insertion protection timing match.
• RFCK is derived from the crystal accuracy, and has a cycle of 136µs. (during normal speed)
• C2PO represents the data error status.
• XROF is generated when the 32K RAM exceeds the ±28F jitter margin. I O O O O O I I O I 1, 0 1, 0 1, 0 1, 0 1, 0 Crystal oscillation circuit input. When the master clock is input externally, input it from this pin. Crystal oscillation circuit output. Serial data output in servo block. Serial data readout clock output in servo block. Serial data latch output in servo block. Sub-Q 80-bit, PCM peak or level data outputs. CD TEXT data output. SQSO readout clock input. GRSCOR resynchronization input. Sub-Q P to W serial output. SBSO readout clock input. XTAI XTAO SOUT SOCK XOLT SQSO SQCK SCSY SBSO EXCK Combination of Monitor Pin Outputs Command bit Output data MTSL1 MTSL0 XUGF XPCK GFS C2PO MNT0 MNT1 MNT2 MNT3 RFCK XPCK XROF GTOP Pin No. Symbol I/O Description

– 7 – CXD2585Q

Electrical Characteristics

1. DC Characteristics (VDD = AVDD = 5.0V ± 5%, Vss = AVss = 0V, Topr = –20 to +75°C) Item Input leak current (1) Input leak current (2) Input leak current (3) Input leak current (4) High level input voltage Low level input voltage High level input voltage Low level input voltage Input voltage High level output voltage Low level output voltage High level output voltage Low level output voltage High level output voltage Low level output voltag Input voltage (1) Input voltage (2) Input voltage (3) Output voltage (1) Output voltage (2) Output voltage (3) V IH (1) VIL(1) VIH (2) VIL(2) VIN (3) VOH (1) VOL (1) VOH (2) VOL (2) VOH (3) VOL (3) ILI(1) ILI(2) ILI(3) ILI(4) 0.7VDD 0.8VDD VSS VDD – 0.8 VSS VDD – 0.8 VSS VDD – 0.5 VSS –10 –40 –20 –40 0.3V DD 0.2VDD VDD VDD 0.4 VDD 0.4 VDD 0.4 600 V V V V V V V V V V V µA µA µA µA Conditions Min. Typ. Max. Unit Applicable pins Schmitt input Analog input IOH = –2mA IOL = 4mA IOH = –6mA IOL = 4mA IOH = –0.28mA IOL = 0.36mA VIN = VSS or VDD VIN = VSS or VDD VI= 1.5 to 3.5V VI= 0 to 5.0V *1,*9 *2,*10 *3,*7,*8 *1,*2 *9,*10 Applicable pins *1 MUTE, DATA, XLAT, SSTP, TEST, TES1, MD2, XTSL, SCSY *2 SQCK, XRST, CLOK, ASYE *3 ASYI, RFAC, CLTV, FILI, VCTL *4 SQSO, SBSO, SENS, ATSK, WFCK, XUGF, XPCK, GFS, C2PO, SCOR, C4M, WDCK, COUT, MIRR, DFCT, FOK, LOCK, FSTO, SFDR, SRDR, TFDR, TRDR, FFDR, FRDR, ASYO, V16M, DOUT, LRCK, PCMD, BCK, EMPH, SOUT, SOCK, XOLT

5 MDP, PCO, VPCO

*6 FILO *7 VC, FE, SE, TE, CE *8 RFDC *9 PWMI, EXCK, ATSK, COUT, MIRR, DFCT, FOK, LOCK, V16M *10 SCLK, FSTO

– 8 – CXD2585Q 2. AC Characteristics (1) XTAI pin (a) When using self-excited oscillation (Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%) (b) When inputting pulses to XTAI pin (Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%) (c) When inputting sine waves to XTAI pin via a capacitor (Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%) Oscillation frequency fMAX 7 34 MHz Item Symbol Min. Typ. Max. Unit High level pulse width tWHX 13 500 ns Low level pulse width tWLX 13 500 ns Pulse cycle tCX 26 1000 ns Input high levelVIHX VDD – 1.0 V Input low level VILX 0.8 V Rise time, fall time tR , tF 10 ns Item Symbol Min. Typ. Max. Unit Input amplitude VI 2.0 VDD + 0.3 Vp-p Item Symbol Min. Typ. Max. Unit tR tF tW H X tW LX tC X VILX VIH X × 0.1 VIH X × 0.9 VIH X XTAI VD D /2

– 9 – CXD2585Q (2) CLOK, DATA, XLAT, SQCK and EXCK pins (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C) Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width EXCK SQCK frequency EXCK SQCK pulse width COUT frequency (for input) * COUT pulse width (for input) * f CK tWCK tSU tH tD tWL fT tWT fT tWT 750 300 300 300 750 750 7.5 0.65 0.65 MHz ns ns ns ns ns MHz ns kHz µs Item Symbol Min. Typ. Max. Unit * Only when $44 and $45 are executed. tW C K tW C K 1/fC K tHtSU tW LtD 1/fT tW T tW T tHtSU C LO K D ATA XLAT EXC K SQ C K C O U T SBSO SQ SO

– 10 – CXD2585Q (4) COUT, MIRR and DFCT pins Operating frequency (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C) COUT maximum operating frequency MIRR maximum operating frequency DFCT maximum operating frequency f COUT fMIRR fDFCTH kHz kHz kHz Signal Symbol Min. Typ. Max. Unit Conditions *1 When using a high-speed traverse TZC. When the RF signal continuously satisfies the following conditions during the above traverse.

• A = 0.12VDD to 0.26VDD
• ≤ 25% *3 During complete RF signal omission. When settings related to DFCT signal generation are Typ. (3) SCLK pin SCLK frequency SCLK pulse width Delay time f SCLK tSPW tDLS 31.3

16 MHz

µs Item Symbol Min. Typ. Max. Unit B A + B tSPWtD LS 1/fSC LK M SB LSB•••

• •• XLAT SC LK Serial R ead O ut D ata (SEN S) A B

– 12 – CXD2585Q [1] CPU Interface § 1-1. CPU Interface Timing

• CPU interface This interface uses DATA, CLOK and XLAT to set the modes. The interface timing chart is shown below.
• The internal registers are initialized by a reset when XRST = 0. § 1-2. CPU Interface Command Table Total bit length for each register Register 0 to 2 4 to 6 A B C D E 8 bits 8 to 24 bits 16 bits 20 bits 28 bits 28 bits 28 bits 24 bits 28 bits 20 bits 20 bits Total bit length 750ns or m ore D 18 D 19 D 20 D 21 D 22 D 23 750ns or m ore Valid C LO K D ATA XLAT R egisters D 0 D 1

– 13 – CXD2585Q FOCUS SERVO ON (FOCUS GAIN NORMAL) FOCUS SERVO ON (FOCUS GAIN DOWN) FOCUS SERVO OFF, 0V OUT FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT FOCUS SEARCH VOLTAGE DOWN FOCUS SEACH VOLTAGE UP ANTI SHOCK ON ANTI SHOCK OFF BRAKE ON BRAKE OFF TRACKING GAIN NORMAL TRACKING GAIN UP TRACKING GAIN UP FILTER SELECT 1 TRACKING GAIN UP FILTER SELECT 2 0 0 0 0 0 0 0 1 FOCUS CONTROL TRACKING CONTROL Reg- ister Command Address D23 to D20 Data 1 D19 D18 D17 D16 Data 2 D15 D14 D13 D12 Data 3 D11 D10 D9 D8 Data 4 D7 D6 D5 D4 Data 5 D3 D2 D1 D0 Command Table ($0X to 1X) —: Don't care

– 14 – CXD2585Q TRACKING SERVO OFF TRACKING SERVO ON FORWARD TRACK JUMP REVERSE TRACK JUMP SLED SERVO OFF SLED SERVO ON FORWARD SLED MOVE REVERSE SLED MOVE SLED KICK LEVEL (±1 · basic value) (Default) SLED KICK LEVEL (±2 · basic value) SLED KICK LEVEL (±3 · basic value) SLED KICK LEVEL (±4 · basic value) 0 0 1 0 0 0 1 1 TRACKING MODE SELECT Reg- ister Command Address D23 to D20 Reg- ister Command Address D23 to D20 Data 1 D19 D18 D17 D16 Data 1 D19 D18 D17 D16 Data 2 D15 D14 D13 D12 Data 2 D15 D14 D13 D12 Data 3 D11 D10 D9 D8 Data 4 D7 D6 D5 D4 Data 5 D3 D2 D1 D0 Data 3 D11 D10 D9 D8 Data 4 D7 D6 D5 D4 Data 5 D3 D2 D1 D0 —: Don't care Command Table ($2X to 3X)

– 15 – CXD2585Q KRAM DATA (K00) SLED INPUT GAIN KRAM DATA (K01) SLED LOW BOOST FILTER A-H KRAM DATA (K02) SLED LOW BOOST FILTER A-L KRAM DATA (K03) SLED LOW BOOST FILTER B-H KRAM DATA (K04) SLED LOW BOOST FILTER B-L KRAM DATA (K05) SLED OUTPUT GAIN KRAM DATA (K06) FOCUS INPUT GAIN KRAM DATA (K07) SLED AUTO GAIN KRAM DATA (K08) FOCUS HIGH CUT FILTER A KRAM DATA (K09) FOCUS HIGH CUT FILTER B KRAM DATA (K0A) FOCUS LOW BOOST FILTER A-H KRAM DATA (K0B) FOCUS LOW BOOST FILTER A-L KRAM DATA (K0C) FOCUS LOW BOOST FILTER B-H KRAM DATA (K0D) FOCUS LOW BOOST FILTER B-L KRAM DATA (K0E) FOCUS PHASE COMPENSATE FILTER A KRAM DATA (K0F) FOCUS DEFECT HOLD GAIN KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 3 0 0 1 1 0 1 0 0 0 0 0 0SELECT Reg- ister Command Address 1 D23 to D20 Address 2 D19 to D16 Address 3 D15 to D12 Address 4 D11 D10 D9 D8 Data 1 D7 D6 D5 D4 Data 2 D3 D2 D1 D0 Command Table ($340X)

– 16 – CXD2585Q KRAM DATA (K10) FOCUS PHASE COMPENSATE FILTER B KRAM DATA (K11) FOCUS OUTPUT GAIN KRAM DATA (K12) ANTI SHOCK INPUT GAIN KRAM DATA (K13) FOCUS AUTO GAIN KRAM DATA (K14) HPTZC / AUTO GAIN HIGH PASS FILTER A KRAM DATA (K15) HPTZC / AUTO GAIN HIGH PASS FILTER B KRAM DATA (K16) ANTI SHOCK HIGH PASS FILTER A KRAM DATA (K17) HPTZC / AUTO GAIN LOW PASS FILTER B KRAM DATA (K18) FIX KRAM DATA (K19) TRACKING INPUT GAIN KRAM DATA (K1A) TRACKING HIGH CUT FILTER A KRAM DATA (K1B) TRACKING HIGH CUT FILTER B KRAM DATA (K1C) TRACKING LOW BOOST FILTER A-H KRAM DATA (K1D) TRACKING LOW BOOST FILTER A-L KRAM DATA (K1E) TRACKING LOW BOOST FILTER B-H KRAM DATA (K1F) TRACKING LOW BOOST FILTER B-L KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 3 0 0 1 1 0 1 0 0 0 0 0 1SELECT Reg- ister Command Address 1 D23 to D20 Address 2 D19 to D16 Address 3 D15 to D12 Address 4 D11 D10 D9 D8 Data 1 D7 D6 D5 D4 Data 2 D3 D2 D1 D0 Command Table ($341X)

– 17 – CXD2585Q KRAM DATA (K20) TRACKING PHASE COMPENSATE FILTER A KRAM DATA (K21) TRACKING PHASE COMPENSATE FILTER B KRAM DATA (K22) TRACKING OUTPUT GAIN KRAM DATA (K23) TRACKING AUTO GAIN KRAM DATA (K24) FOCUS GAIN DOWN HIGH CUT FILTER A KRAM DATA (K25) FOCUS GAIN DOWN HIGH CUT FILTER B KRAM DATA (K26) FOCUS GAIN DOWN LOW BOOST FILTER A-H KRAM DATA (K27) FOCUS GAIN DOWN LOW BOOST FILTER A-L KRAM DATA (K28) FOCUS GAIN DOWN LOW BOOST FILTER B-H KRAM DATA (K29) FOCUS GAIN DOWN LOW BOOST FILTER B-L KRAM DATA (K2A) FOCUS GAIN DOWN PHASE COMPENSATE FILTER A KRAM DATA (K2B) FOCUS GAIN DOWN DEFECT HOLD GAIN KRAM DATA (K2C) FOCUS GAIN DOWN PHASE COMPENSATE FILTER B KRAM DATA (K2D) FOCUS GAIN DOWN OUTPUT GAIN KRAM DATA (K2E) NOT USED KRAM DATA (K2F) NOT USED KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 3 0 0 1 1 0 1 0 0 0 0 1 0SELECT Reg- ister Command Address 1 D23 to D20 Address 2 D19 to D16 Address 3 D15 to D12 Address 4 D11 D10 D9 D8 Data 1 D7 D6 D5 D4 Data 2 D3 D2 D1 D0 Command Table ($342X)

– 18 – CXD2585Q KRAM DATA (K30) SLED INPUT GAIN (when TGup2 is accessed with SFSK = 1) KRAM DATA (K31) ANTI SHOCK LOW PASS FILTER B KRAM DATA (K32) NOT USED KRAM DATA (K33) ANTI SHOCK HIGH PASS FILTER B-H KRAM DATA (K34) ANTI SHOCK HIGH PASS FILTER B-L KRAM DATA (K35) ANTI SHOCK FILTER COMPARATE GAIN KRAM DATA (K36) TRACKING GAIN UP2 HIGH CUT FILTER A KRAM DATA (K37) TRACKING GAIN UP2 HIGH CUT FILTER B KRAM DATA (K38) TRACKING GAIN UP2 LOW BOOST FILTER A-H KRAM DATA (K39) TRACKING GAIN UP2 LOW BOOST FILTER A-L KRAM DATA (K3A) TRACKING GAIN UP2 LOW BOOST FILTER B-H KRAM DATA (K3B) TRACKING GAIN UP2 LOW BOOST FILTER B-L KRAM DATA (K3C) TRACKING GAIN UP PHASE COMPENSATE FILTER A KRAM DATA (K3D) TRACKING GAIN UP PHASE COMPENSATE FILTER B KRAM DATA (K3E) TRACKING GAIN UP OUTPUT GAIN KRAM DATA (K3F) NOT USED KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 3 0 0 1 1 0 1 0 0 0 0 1 1SELECT Reg- ister Command Address 1 D23 to D20 Address 2 D19 to D16 Address 3 D15 to D12 Address 4 D11 D10 D9 D8 Data 1 D7 D6 D5 D4 Data 2 D3 D2 D1 D0 Command Table ($343X)

– 19 – CXD2585Q KRAM DATA (K40) TRACKING HOLD FILTER INPUT GAIN KRAM DATA (K41) TRACKING HOLD FILTER A-H KRAM DATA (K42) TRACKING HOLD FILTER A-L KRAM DATA (K43) TRACKING HOLD FILTER B-H KRAM DATA (K44) TRACKING HOLD FILTER B-L KRAM DATA (K45) TRACKING HOLD FILTER OUTPUT GAIN KRAM DATA (K46) TRACKING HOLD INPUT GAIN (when TGup2 is accessed with THSK = 1) KRAM DATA (K47) NOT USED KRAM DATA (K48) FOCUS HOLD FILTER INPUT GAIN KRAM DATA (K49) FOCUS HOLD FILTER A-H KRAM DATA (K4A) FOCUS HOLD FILTER A-L KRAM DATA (K4B) FOCUS HOLD FILTER B-H KRAM DATA (K4C) FOCUS HOLD FILTER B-L KRAM DATA (K4D) FOCUS HOLD FILTER OUTPUT GAIN KRAM DATA (K4E) NOT USED KRAM DATA (K4F) NOT USED KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD7 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD6 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD5 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD4 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD3 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD2 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD1 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 KD0 3 0 0 1 1 0 1 0 0 0 1 0 0SELECT Reg- ister Command Address 1 D23 to D20 Address 2 D19 to D16 Address 3 D15 to D12 Address 4 D11 D10 D9 D8 Data 1 D7 D6 D5 D4 Data 2 D3 D2 D1 D0 Command Table ($344X)

– 20 – CXD2585Q FCS Bias Limit FCS Bias Data Traverse Center Data PGFS, PFOK, RFAC Booster Surf Brake Booster 0010 PGFS SFBK THB ON PGFS SFBK FHB ON RFOK TLB1 ON FBL9 FB9 TV9 RFOK FLB1 ON FBL8 FB8 TV8 TLB2 ON FBL7 FB7 TV7 FBL6 FB6 TV6 HBST FBL5 FB5 TV5 HBST FBL4 FB4 TV4 LB1S FBL3 FB3 TV3 LB1S FBL2 FB2 TV2 LB2S FBL1 FB1 TV1 LB2S TV0 SELECT Reg- ister Command Address 1 D23 to D20 D19 D18 D17 D16 Address 2 D15 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D1 D0D3 D2 Data 3Data 2Data 1Address 2 D14 D13 D12 Data 1 D11 D10 D9 D8 Data 2 D7 D6 D5 D4 Data 3 D3 D2 D1 D0 Command Table ($348X to 34FX) —: Don't care 0 0 1 1

– 21 – CXD2585Q FCS search, AGF TRK jump, AGT FZC, AGC, SLD move DC measure, cancel Serial data read out FCS Bias, Gain, Surf jump/brake Mirr, DFCT, FOK TZC, Cout, Bottom, Mirr SLD filter Filter Clock, others FT1 TDZC FZSH VCLM DAC SFO2 COSS SFID F1NM FT0 DTZC FZSL VCLC SD6 FBON SFO1 COTS SFSK F1DM AGC4 FS5 TJ5 SM5 FLM SD5 FBSS SDF2 CETZ THID F3NM XT4D FS4 TJ4 SM4 FLC0 SD4 FBUP SDF1 CETF THSK F3DM XT2D FS3 TJ3 SM3 RFLM SD3 FBV1 MAX2 COT2 TINM FS2 TJ2 SM2 RFLC SD2 FBV0 MAX1 COT1 TLD2 TIUM DRR2 FS1 TJ1 SM1 AGF SD1 SFOX MOT2 TLD1 T3NM DRR1 FS0 TJ0 SM0 AGT SD0 TJD0 BTF TLD0 T3UM DRR0 FTZ SFJP AGS DFSW FPS1 D2V2 BTS1 DF1S FG6 TG6 AGJ LKSW FPS0 D2V1 BTS0 TLCD ASFG FG5 TG5 AGGF TBLM TPS1 D1V2 MRC1 FTQ FG4 TG4 AGGT TCLM TPS0 D1V1 MRC0 LKIN LPAS FG3 TG3 AGV1 FLC1 RINT COIN FG2 TG2 AGV2 TLC2 SJHD MDFI FG1 TG1 AGHS TLC1 INBK MIRI AGHF FG0 TG0 AGHT TLC0 MTI0 XT1D ASOT SELECT Reg- ister Command Address D23 to D20 D19 D18 D17 D16 Data 1 D15 D14 D13 D12 Data 2 D11 D10 D9 D8 Data 3 D7 D6 D5 D4 Data 4 D3 D2 D1 D0 0 0 1 1 Command Table ($35X to 3FX)

– 22 – CXD2585Q Auto sequence Blind (A, E), Brake (B), Overflow (C, G) Sled KICK, BRAKE (D), KICK (F) Auto sequence (N) track jump count setting MODE specification Function specification Audio CTRL Traverse monitor counter setting Spindle servo coefficient setting CLV CTRL SPD mode AS3 TR3 SD3 32768 CD- ROM VARI ON 32768 Gain MDP1 CM3 AS2 TR2 SD2 16384 DOUT Mute DSPB ON/OFF VARI USE 16384 Gain MDP0 TB CM2 AS1 TR1 SD1 8192 DOUT Mute-F ASEQ ON/OFF Mute 8192 Gain MDS1 TP CM1 AS0 TR0 SD0 4096 WSEL ATT 4096 Gain MDS0 CLVS Gain CM0 MT3 KF3 2048 VCO SEL1 BiliGL MAIN PCT1 2048 Gain DCLV1 VP7 EPWM MT2 KF2 1024 ASHS BiliGL SUB PCT2 1024 Gain DCLV0 VP6 SPDC MT1 KF1 512 SOCT0 FLFC 512 PCC1 VP5 ICAP MT0 KF0 256 VCO SEL2 SOC2 256 PCC0 VP4 SFSL LSSL 128 KSL3 128 SFP3 VP3 VC2C KSL2 SFP2 VP2 HIFC KSL1 SFP1 VP1 LPWR KSL0 SFP0 VP0 VPON SRP3 VP CTL1 Gain CAV1 SRP2 VP CTL0 Gain CAV0 XVCO2 THRU SRP1 SRP0 INV VPCO A B C D E Reg- ister Command Address D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 Data 1 Data 2 Data 3 Data 4 Command Table ($4X to EX) —: Don't care

– 23 – CXD2585Q FOCUS SERVO OFF, 0V OUT TRACKING GAIN UP FILTER SELECT 1 TRACKING SERVO OFF SLED SERVO OFF SLED KICK LEVEL (±1 · basic value) (Default) KRAM DATA ($3400XX to $344fXX) 0 0 0 0 0 0 0 1 0 0 1 0 FOCUS CONTROL TRACKING CONTROL TRACKING MODE Reg- ister Command Address D23 to D20 Data 1 D19 D18 D17 D16 Data 2 D15 D14 D13 D12 Data 3 D11 D10 D9 D8 Data 4 D7 D6 D5 D4 Data 5 D3 D2 D1 D0 Reg- ister Command

3 SELECT

0 0 1 1 0 1 0 0 0 See "Coefficient ROM Preset Values Table". Data 1 D19 D18 D17 D16 Data 2 D15 D14 D13 D12 Data 3 D11 D10 D9 D8 Data 4 D7 D6 D5 D4 Data 5 D3 D2 D0 D0 Address 1 D23 to D20 D19 D18 D17 D16 Address 2 D15 D14 D13 D12 Address 3 D11 D10 D9 D8 Data 1 D7 D6 D5 D4 Data 2 D3 D2 D0 D0 § 1-3. CPU Command Presets Command Preset Table ($0X to 34X) —: Don't care —: Don't care Command Table ($4X to EX) cont. MODE specification 1 0 0 0 ERC4 SCOR SEL SCSY SOCT1 TXON TXOUT OUTLI OUTL08 Function specification Audio CTRL Traverse monitor counter setting Spindle servo coefficient setting 1 0 0 1 1 0 1 0 1 0 1 1 EDC7 EDC6 MTSL1 EDC5 MTSL0 EDC4 EDC3 EDC2 EDC1 EDC0 A B C Reg- ister Command Address Data 1 Data 2 Data 3 Data 4 D7 D6 D5 D4 D3 D2 D1 D0 Data 5 Data 6

– 24 – CXD2585Q Command Preset Table ($348X to 34FX) 0010 PGFS, PFOK, RFAC Booster Surf Brake Booster FCS Bias Limit FCS Bias Data Traverse Center Data SELECT Reg- ister Command Address 1 D23 to D20 D19 D18 D17 D16 Address 2 D15 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D1 D0D3 D2 Data 3Data 2Data 1Address 2 D14 D13 D12 Data 1 D11 D10 D9 D8 Data 2 D7 D6 D5 D4 Data 3 D3 D2 D1 D0 0 0 1 1

– 25 – CXD2585Q FCS search, AGF TRK jump, AGT FZC, AGC, SLD move DC measure, cancel Serial data read out FCS Bias, Gain, Surf jump/brake Mirr, DFCT, FOK TZC, Cout, Bottom, Mirr SLD filter Filter Clock, others SELECT Reg- ister Command Address D23 to D20 D19 D18 D17 D16 Data 1 D15 D14 D13 D12 Data 2 D11 D10 D9 D8 Data 3 D7 D6 D5 D4 Data 4 D3 D2 D1 D0 0 0 1 1 Command Preset Table ($35X to 3FX)

– 26 – CXD2585Q Auto sequence Blind (A, E), Brake (B), Overflow (C, G) Sled KICK, BRAKE (D), KICK (F) Auto sequence (N) track jump count setting MODE specification Function specification Audio CTRL Traverse monitor counter setting Spindle servo coefficient setting CLV CTRL SPD mode A B C D E Reg- ister Command Address D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 Data 1 Data 2 Data 3 Data 4 Command Preset Table ($4X to EX) —: Don't care MODE specification Function specification Audio CTRL Traverse monitor counter setting Spindle servo coefficient setting 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 A B C Reg- ister Command Address Data 1 Data 2 Data 3 Data 4 D7 D6 D5 D4 D3 D2 D1 D0 Data 5 Data 6

– 27 – CXD2585Q ADDRESS K00 K01 K02 K03 K04 K05 K06 K07 K08 K09 K0A K0B K0C K0D K0E K0F SLED INPUT GAIN SLED LOW BOOST FILTER A-H SLED LOW BOOST FILTER A-L SLED LOW BOOST FILTER B-H SLED LOW BOOST FILTER B-L SLED OUTPUT GAIN FOCUS INPUT GAIN SLED AUTO GAIN FOCUS HIGH CUT FILTER A FOCUS HIGH CUT FILTER B FOCUS LOW BOOST FILTER A-H FOCUS LOW BOOST FILTER A-L FOCUS LOW BOOST FILTER B-H FOCUS LOW BOOST FILTER B-L FOCUS PHASE COMPENSATE FILTER A FOCUS DEFECT HOLD GAIN K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K1A K1B K1C K1D K1E K1F K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K2A K2B K2C K2D K2E K2F FOCUS PHASE COMPENSATE FILTER B FOCUS OUTPUT GAIN ANTI SHOCK INPUT GAIN FOCUS AUTO GAIN HPTZC / Auto Gain HIGH PASS FILTER A HPTZC / Auto Gain HIGH PASS FILTER B ANTI SHOCK HIGH PASS FILTER A HPTZC / Auto Gain LOW PASS FILTER B Fix* TRACKING INPUT GAIN TRACKING HIGH CUT FILTER A TRACKING HIGH CUT FILTER B TRACKING LOW BOOST FILTER A-H TRACKING LOW BOOST FILTER A-L TRACKING LOW BOOST FILTER B-H TRACKING LOW BOOST FILTER B-L TRACKING PHASE COMPENSATE FILTER A TRACKING PHASE COMPENSATE FILTER B TRACKING OUTPUT GAIN TRACKING AUTO GAIN FOCUS GAIN DOWN HIGH CUT FILTER A FOCUS GAIN DOWN HIGH CUT FILTER B FOCUS GAIN DOWN LOW BOOST FILTER A-H FOCUS GAIN DOWN LOW BOOST FILTER A-L FOCUS GAIN DOWN LOW BOOST FILTER B-H FOCUS GAIN DOWN LOW BOOST FILTER B-L FOCUS GAIN DOWN PHASE COMPENSATE FILTER A FOCUS GAIN DOWN DEFECT HOLD GAIN FOCUS GAIN DOWN PHASE COMPENSATE FILTER B FOCUS GAIN DOWN OUTPUT GAIN NOT USED NOT USED DATA CONTENTS * Fix indicates that normal preset values should be used. <Coefficient ROM Preset Values Table (1)>

– 28 – CXD2585Q <Coefficient ROM Preset Values Table (2)> ADDRESS K30 K31 K32 K33 K34 K35 K36 K37 K38 K39 K3A K3B K3C K3D K3E K3F SLED INPUT GAIN (Only when TRK Gain Up2 is accessed with SFSK = 1.) ANTI SHOCK LOW PASS FILTER B NOT USED ANTI SHOCK HIGH PASS FILTER B-H ANTI SHOCK HIGH PASS FILTER B-L ANTI SHOCK FILTER COMPARATE GAIN TRACKING GAIN UP2 HIGH CUT FILTER A TRACKING GAIN UP2 HIGH CUT FILTER B TRACKING GAIN UP2 LOW BOOST FILTER A-H TRACKING GAIN UP2 LOW BOOST FILTER A-L TRACKING GAIN UP2 LOW BOOST FILTER B-H TRACKING GAIN UP2 LOW BOOST FILTER B-L TRACKING GAIN UP PHASE COMPENSATE FILTER A TRACKING GAIN UP PHASE COMPENSATE FILTER B TRACKING GAIN UP OUTPUT GAIN NOT USED K40 K41 K42 K43 K44 K45 K46 K47 K48 K49 K4A K4B K4C K4D K4E K4F TRACKING HOLD FILTER INPUT GAIN TRACKING HOLD FILTER A-H TRACKING HOLD FILTER A-L TRACKING HOLD FILTER B-H TRACKING HOLD FILTER B-L TRACKING HOLD FILTER OUTPUT GAIN TRACKING HOLD FILTER INPUT GAIN (Only when TRK Gain Up2 is accessed with THSK = 1.) NOT USED FOCUS HOLD FILTER INPUT GAIN FOCUS HOLD FILTER A-H FOCUS HOLD FILTER A-L FOCUS HOLD FILTER B-H FOCUS HOLD FILTER B-L FOCUS HOLD FILTER OUTPUT GAIN NOT USED NOT USED DATA CONTENTS

– 29 – CXD2585Q § 1-4. Description of SENS Signals SENS output Microcomputer serial register (latching not required) $0X $1X $2X $30 to 37 $38 $38 $3904 $3908 $390C $391C $391D $391F $3A $3B to 3F $4X $5X $6X $AX $BX $CX $EX $7X, 8X, 9X, DX, FX Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z GFS COMP COUT OV64 Z FZC AS TZC SSTP AGOK * XAVEBSY * TE Avrg Reg. FE Avrg Reg. VC Avrg Reg. TRVSC Reg. FB Reg. RFDC Avrg Reg. FBIAS Count STOP SSTP XBUSY FOK GFS COMP COUT OV64 9 bits 9 bits 9 bits 9 bits 9 bits 8 bits ASEQ = 0 ASEQ = 1 Output data length * $38 outputs AGOK during AGT and AGF command settings, and XAVEBSY during AVRG measurement. SSTP is output in all other cases.

– 30 – CXD2585Q Description of SENS Signals The SENS pin is high impedance. Low while the auto sequencer is in operation, high when operation terminates. Outputs the same signal as the FOK pin. High for "focus OK". High when the regenerated frame sync is obtained with the correct timing. Counts the number of tracks set with Reg.B. High when Reg.B is latched, low when the initial Reg.B number is counted through COUT. Counts the number of tracks set with Reg.B. High when Reg.B is latched, toggles each time the Reg.B number is counted through COUT. While $44 and $45 are being executed, toggles with each COUT 8-count instead of the Reg.B number. Low when the EFM signal is lengthened by 64 channel clock pulses or more after passing through the sync detection filter. Z XBUSY FOK GFS COMP COUT OV64 SENS output

– 31 – CXD2585Q The meaning of the data for each address is explained below. $4X commands Register name Data 1 Command Data 2 MAX timer value Data 3 Timer range AS3 AS2 AS1 AS0 MT3 MT2 MT1 MT0 LSSL 0 0 0 Command Cancel Fine Search Focus-On

1 Track Jump

10 Track Jump

RXF = 0 Forward RXF = 1 Reverse

• When the Focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted.
• When the Track jump commands ($44 to $45, $48 to $4D) are canceled, $25 is sent and the auto sequence is interrupted.
• To disable the MAX timer, set the MAX timer value to 0. $5X commands MAX timer value MT3 23.2ms 1.49s 11.6ms 0.74s 5.8ms 0.37s 2.9ms 0.18s MT2 MT1 MT0 LSSL 0 0 0 Timer range Timer TR3 TR2 TR1 TR0 Blind (A, E), Overflow (C, G) Brake (B) 0.18ms 0.36ms 0.09ms 0.18ms 0.045ms 0.09ms 0.022ms 0.045ms

– 32 – CXD2585Q Command Data 1 Data 2 Data 3 Data 4 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20Auto sequence track jump count setting This command is used to set N when a 2N-track jump is executed, to set M when an M-track move is executed and to set the jump count when fine search is executed for auto sequencer.

• The maximum track count is 65,535, but note that with a 2N-track jump the maximum track jump count depends on the mechanical limitations of the optical system.
• When the track jump count is from 0 to 15, the COUT signal is counted for 2N-track jumps and M-track moves; when the count is 16 or over, the MIRR signal is counted. For fine search, the COUT signal is counted. $7X commands Auto sequencer track jump count setting $6X commands Register name Data 1 KICK (D) Data 2 KICK (F) SD3 SD2 SD1 SD0 KF3 KF2 KF1 KF0 Timer SD3 SD2 SD1 SD0 When executing KICK (D) $44 or $45 When executing KICK (D) $4C or $4D 23.2ms 11.6ms 11.6ms 5.8ms 5.8ms 2.9ms 2.9ms 1.45ms Timer KF3 KF2 KF1 KF0 KICK (F) 0.72ms 0.36ms 0.18ms 0.09ms

– 33 – CXD2585Q * See mute conditions (1), (2), and (4) to (6) under $AX commands for other mute conditions. MD2 Other mute conditions* DOUT Mute D.out Mute FDOUT output OFF 0dB –∞ dB DA output for 48-bit slot 0dB 0dB –∞ dB 0dB –∞ dB –∞ dB Command Data 1 MODE specification CD- ROM DOUT Mute DOUT Mute-F WSEL D23 D22 D21 D20 Data 2 VCO SEL1 ASHS SOCT0 VCO SEL2 D19 D18 D17 D16 $8X commands Command bit DOUT Mute = 1 DOUT Mute = 0 When Digital Out is on (MD2 pin = 1), DOUT output is muted. When Digital Out is on, DOUT output is not muted. Processing Command bit D. out Mute F = 1 D. out Mute F = 0 When Digital Out is on (MD2 pin = 1), DA output is muted. DA output mute is not affected when Digital Out is either on or off. Processing Command bit CDROM = 1 CDROM = 0 C2PO timing 1-3 1-3 CDROM mode; average value interpolation and pre-value hold are not performed. Audio mode; average value interpolation and pre-value hold are performed. Processing

– 34 – CXD2585Q Command bit Processing VCOSEL1 = 0 VCOSEL1 = 1 Multiplier PLL VCO1 is set to normal speed. Multiplier PLL VCO1 is set to approximately twice the normal speed. Command bit KSL3 KSL2 Processing Output of multiplier PLL VCO1 is 1/1 frequency-divided. Output of multiplier PLL VCO1 is 1/2 frequency-divided. Output of multiplier PLL VCO1 is 1/4 frequency-divided. Output of multiplier PLL VCO1 is 1/8 frequency-divided. See the previous page. Command Data 2 MODE specification VCO SEL1 ASHS SOCT0 VCO SEL2 D19 D18 D17 D16 Data 3 KSL3 KSL2 KSL1 KSL0 D15 D14 D13 D12 Command bit Sync protection window width WSEL = 1 WSEL = 0 ±26 channel clock ±6 channel clock Anti-rolling is enhanced. Sync window protection is enhanced. Application * In normal-speed playback, channel clock = 4.3218MHz. Command bit Function ASHS = 0 ASHS = 1 The command transfer rate to DSSP block from auto sequencer is set to normal speed. The command transfer rate to DSSP block from auto sequencer is set to half speed. * See "§ 4-8. Playback Speed" for settings. Command bit SOCT0 SOCT1 Processing Sub-Q is output from the SQSO pin. Each signal is output from the SQSO pin. Input the readout clock to SQCK. (See Timing Chart 2-4.) The error rate is output from the SQSO pin. Input the readout clock to SQCK. (See Timing Chart 2-6.) —: Don't care

– 35 – CXD2585Q Command bit Processing VCOSEL2 = 0 VCOSEL2 = 1 Wide-band PLL VCO2 is set to normal speed. Wide-band PLL VCO2 is set to approximately twice the normal speed. Command bit KSL1 KSL0 Processing Output of wide-band PLL VCO2 is 1/1 frequency-divided. Output of wide-band PLL VCO2 is 1/2 frequency-divided. Output of wide-band PLL VCO2 is 1/4 frequency-divided. Output of wide-band PLL VCO2 is 1/8 frequency-divided. Command D11 0 0 VCO2 THRU 0 ERC4 SCOR SEL SCSY SOCT1 TXON TXOUT OUTL1 OUTL0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Data 4 Data 5 Mode specification Data 6 Command bit VCO2 THRU = 0 Processing V16M is output. The wide-band EFM PLL clock can be input from the V16M pin. * These bits select the internal or external connection for the VCO2 used in CAV-W or variable pitch mode. VCO2 THRU = 1 Command bit ERC4 = 0 Processing C2 error double correction is performed when DSPB = 1. C2 error quadruple correction is performed even when DSPB = 1.ERC4 = 1 Command bit SCOR SEL = 0 Processing WDCK signal is output. GRSCOR (protected SCOR) is output. * Used when outputting GRSCOR from the WDCK pin. SCOR SEL = 1

– 36 – CXD2585Q Command bit TXON = 0 Processing When CD TEXT data is not demodulated, set TXON to 0. When CD TEXT data is demodulated, set TXON to 1. * See "$4-10. CD TEXT Data Demodulation" TXON = 1 Command bit SCSY = 0 Processing No processing. GRSCOR (protected SCOR) synchronization is applied again. * Used to resynchronize GRSCOR. The rising edge signal of this commnd bit is used internally. Therefore, when resynchronizing GRSCOR, first return the setting to 0 and then set to 1. GRSCOR achieves the crystal accuracy by removing the jitter components included in the SCOR signal. This signal is synchronized with PCMDATA. The resynchronization conditions are when GTOP = high or when the SCSY pin = high. (same as when SCSY = 1 is sent by the $8X command.) SCSY = 1 Command bit TXOUT = 0 Processing Various signals except for CD TEXT is output from the SQSO pin. CD TEXT data is output from the SQSO pin. * See "$4-10. CD TEXT Data Demodulation" TXOUT = 1 Command bit OUTL1 = 0 Processing WFCK, XPCK C4M, WDCK and FSTO are output. V16M is output when VCO2 THRU = 0. WFCK, XPCK C4M, WDCK and FSTO outputs are set to low. The V16M output is low when VCO2 THRU = 0.OUTL1 = 1 Command bit OUTL0 = 0 OUTL0 = 1 Processing PCMD, BCK, LRCK and EMPH are output. PCMD, BCK, LRCK and EMPH outputs are low.

– 37 – CXD2585Q Command Data 1 Function specification 1 DSPB ON-OFF A.SEQ ON-OFF 1 D23 D22 D21 D20 Data 2 BiliGL MAIN BiliGL SUB FLFC D19 D18 D17 D16 $9X commands Command bit DSPB = 0 DSPB = 1 Normal-speed playback, C2 error quadruple correction. Double-speed playback, C2 error double correction. (quadruple correction when ERC4 = 1) Processing FLFC is normally 0. FLFC is 1 in CAV-W mode, for any playback speed. Command bit BiliGL SUB = 0 BiliGL SUB = 1 STEREO SUB MAIN Mute BiliGL MAIN = 0BiliGL MAIN = 1 Definition of bilingual capable MAIN, SUB and STEREO The left channel input is output to the left and right channels for MAIN. The right channel input is output to the left and right channels for SUB. The left and right channel inputs are output to the left and right channels for STEREO.

– 38 – CXD2585Q Command Data 1 Audio CTRL VARI ON VARI USE Mute ATT D23 D22 D21 D20 Data 2 PCT1 PCT2 D19 D18

0 SOC2

$AX commands Command bit Mute = 0 Mute = 1 Mute off if other mute conditions are not set. Mute on. Peak register reset. Meaning Command bit ATT = 0 ATT = 1 Attenuation off. –12dB Meaning Mute conditions (1) When register A mute = 1. (2) When Mute pin = 1. (3) When register 8 D.out Mute F = 1 and the Digital Out is on (MD2 pin = 1). (4) When GFS stays low for over 35 ms (during normal-speed). (5) When register 9 BiliGL MAIN = Sub = 1. (6) When register A PCT1 = 1 and PCT2 = 0. (1) to (4) perform zero-cross muting with a 1ms time limit. Command bit PCT1 PCT2 Normal mode Level meter mode Peak meter mode Normal mode

• 0dB
• 0dB Mute
• 0dB C1: double; C2: quadruple C1: double; C2: quadruple C1: double; C2: double C1: double; C2: double Meaning PCM Gain ECC error correction ability Description of level meter mode (see Timing Chart 1-4.)
• When the LSI is set to this mode, it performs digital level meter functions.
• When the 96-bit clock is input to SQCK, 96 bits of data are output to SQSO. The initial 80 bits are Sub-Q data (see§ 2. Subcode Interface). The last 16 bits are LSB first, which are 15-bit PCM data (absolute values) and an L/R flag. The L/R flag is high when the 15-bit PCM data is from the left channel and low when the data is from the right channel.
• The PCM data is reset and the L/R flag is reversed after one readout. Then maximum value measuring continues until the next readout. Command bit VARION = 0 Processing Variable pitch mode is turned off. (The crystal is the reference to the internal clock.) Variable pitch mode is turned on. (The VCO2 is the reference to the internal clock.)VARION = 1 Command bit VARIUSE = 0 Processing When the variable pitch mode is not used, set VARIUSE to 0 . When the variable pitch mode is used, set VARIUSE to 1. * See "$DX commands" for the variable range and the usage example of the variable pitch. VARIUSE = 1

– 39 – CXD2585Q Description of peak meter mode(see Timing Chart 1-5.)

• When the LSI is set to this mode, the maximum PCM data value is detected regardless of if it comes from the left or right channel. The 96-bit clock must be input to SQCK to read out this data.
• When the 96-bit clock is input, 96 bits of data are output to SQSO and the value is set in the LSI internal register again. In other words, the PCM maximum value detection register is not reset by the readout.
• To reset the PCM maximum value register to zero, set PCT1 = PCT2 = 0 or set the $AX mute.
• The Sub-Q absolute time is automatically controlled in this mode. In other words, after the maximum value is generated, the absolute time for CRC to become OK is retained in the memory. Normal operation is conducted for the relative time.
• The final bit (L/R flag) of the 96-bit data is normally 0.
• The pre-value hold and average value interpolation data are fixed to level (–∞ ) for this mode. SENS output switching
• This command enables the SQSO pin signal to be output from the SENS pin. When SOC2 = 0, SENS output is performed as usual. When SOC2 = 1, the SQSO pin signal is output from the SENS pin. At this time, the readout clock is input to the SCLK pin. Note)SOC2 should be switched when SQCK = SCLK = high. Command bit SOC2 = 0 SOC2 = 1 The SENS signal is output from the SENS pin as usual. The SQSO pin signal is output from the SENS pin. Processing $BX commands This command sets the traverse monitor count. Command Data 1 Data 2 Data 3 Data 4 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20Traverse monitor count setting
• When the set number of tracks are counted during fine search, the sled control for the traverse cycle control goes off.
• The traverse monitor count is set to monitor the traverse status from the SENS output as COMP and COUT. Command bit MTSL1 MTSL0 Output data XUGF MINT0 RFCK XPCK MNT1 XPCK GFS MNT2 XROF C2PO MNT3 GTOP Command Data 5 Traverse monitor count setting 0 0 MTSL1 MTSL0 D7 D6 D5 D4 This command sets the monitor output switching.

– 40 – CXD2585Q Spindle servo coefficient setting CLV CTRL ($DX) Gain MDP1 Gain MDP0 Gain MDS1 Gain MDS0 Gain CLVS Gain MDS1 Gain MDS0 Gain CLVS GCLVS –12dB –6dB –6dB 0dB 0dB +6dB Command D23 Data 1 D22 D21 D20 Gain DCLV0 Gain DCLV1 PCC1 PCC0 D19 Data 2 D18 D17 D16 $CX commands

• CLVS mode gain setting: GCLVS Gain MDP1 Gain MDP0 GMDP –6dB 0dB +6dB Gain DCLV1 Gain DCLV0 GDCLV 0dB +6dB +12dB Gain MDS1 Gain MDS0 GMDS –6dB 0dB +6dB
• CLVP mode gain setting: GMDP : GMDS
• DCLV overall gain setting: GDCLV Command bit PCC1 PCC0 Processing The VPCO signal is output. The VPCO pin output is high impedance. The VPCO pin output is low. The VPCO pin output is high.
• This command controls the VPCO pin signal. The VPCO output can be controlled with this setting.

– 41 – CXD2585Q Command Data 3 D15 SFP3 SFP2 SFP1 SFP0 SRP3 SRP2 SRP1 SRP0Spindle servo coefficient setting D14 D13 D12 D11 D10 D9 D8 Data 4 * See § 4-2. Frame Sync Protection regarding frame sync protection. Command bit SRP3 to 0 Sets the frame sync backward protection times. The setting range is 1 to F (Hex). Processing Command bit SFP3 to 0 Sets the frame sync forward protection times. The setting range is 1 to F (Hex). Processing

• The CXD2585Q can serially output the 40 bits (10 BCD codes) of error monitor data selected by EDC0 to 7 from the SQSO pin and monitor this data using a microcomputer. The C1 and C2 error rate settings are sent one at a time by the $C commands by setting $8 commands SOCT0 and SOCT1 = 1. Then, the data can be read out from the SQSO pin by sending 40 SQCK pulses. $CX commands Command Data 5 EDC7 EDC6 EDC5 EDC4 EDC3 EDC2 EDC1 EDC0Spindle servo coefficient setting D6 D5 D4 D3 D2 D1 D0 Data 6

– 42 – CXD2585Q Command bit EDC7 = 0 EDC6 EDC5 EDC4 EDC3 EDC2 EDC1 EDC0 EDC7 = 1 EDC6 EDC5 EDC4 EDC3 EDC2 EDC1 EDC0 The [No C1 errors, pointer set] count is output when 0. The [One C1 error corrected, pointer reset] count is output when 0. The [No C1 errors, pointer set] count is output when 0. The [One C1 error corrected, pointer set] count is output when 0. The [Two C1 errors corrected, pointer set] count is output when 0. The [C1 correction impossible, pointer set] count is output when 0. 7350 frame count cycle mode* 1 when 1. 73500 frame count cycle mode*2 when 0. The [No C2 errors, pointer reset] count is output when 0. The [One C2 error corrected, pointer reset] count is output when 0. The [Two C2 errors corrected, pointer reset] count is output when 0. The [Three C2 errors corrected, pointer reset] count is output when 0. The [Four C2 errors corrected, pointer reset] count is output when 0. The [C2 correction impossible, pointer copy] count is output when 0. The [C2 correction impossible, pointer set] count is output when 0. Processing Error monitor commands

1 The number selected by C1 (EDC1 to 6) and C2 (EDC0 to 6) is added to C1 and C2 and output every 7350

frames. *2 The number selected by C1 (EDC1 to 6) and C2 (EDC0 to 6) is added to C1 and C2 and output every 73500 frames. $DX commands See "$CX commands". Command bit TB = 0 TB = 1 TP = 0 TP = 1 Bottom hold at a cycle of RFCK/32 in CLVS mode. Bottom hold at a cycle of RFCK/16 in CLVS mode. Peak hold at a cycle of RFCK/4 in CLVS mode. Peak hold at a cycle of RFCK/2 in CLVS mode.

Description

– 43 – CXD2585Q The rotational velocity R of the spindle can be expressed with the following equation. R: Relative velocity at normal speed = 1 R = · l n: VP0 to 7 setting value l: Multiple set by VPCTL0, 1 256 – n * The above setting should be 0, 0 except for the CAV-W operating mode. The settings are as follows in CAV-W mode. Command bit VPCTL1 VPCTL0 Processing The setting of VP0 to 7 is multiplied by 1. The setting of VP0 to 7 is multiplied by 2. The setting of VP0 to 7 is multiplied by 3. The setting of VP0 to 7 is multiplied by 4. Command Data 2 CLV CTRL VP7 VP6 VP5 VP4 D19 D18 D17 D16 Data 3 VP3 VP2 VP1 VP0 D15 D14 D13 D12 Data 4 VP CTL1 VP CTL0 0 0 D11 D10 D9 D8 Command bit Processing VP0 to 7 The spindle rotational velocity is set. Command bit VP0 to 7 = F0 (H) VP0 to 7 = E0 (H) VP0 to 7 = C0 (H) Playback at 1/2 (1) · speed Playback at 1 (2) · speed Playback at (4) · speed Notes) 1.Values when crystal is 16.9344MHz and XTSL is low or when crystal is 33.8688MHz and XTSL is high. 2.The values in parentheses are for when DSPB is 1. R – Relative velocity [M ultiple] 1.5 0.5 F0 E0 VP0 to VP7 setting value [H EX] DSPB = 1 D SPB = 0 2.5 3.5 D 0 C 0

– 44 – CXD2585Q Command bit Processing VPCTL1 to 0, VP7 to 0The pitch of variable pitch mode is set. The setting in variable pitch mode is as shown below. The setting of the pitch can be expressed with the equation below. P = [%]–n P:Setting value of pitch n:Setting value for VPCTL1, VPCTL0 and VP7 to VP0 (two's complementary, VPCTL1 is sign bit) The setting range of the pitch is –48.7 to +51.2%. The pitch setting for + side should be within the playback speed of the recommended operating conditions. The following is the example of the command in variable pitch mode. $A4XXXXX (Sets to use variable pitch mode) $ACXXXXX (Variable pitch mode is turned on. The VCO2 is the reference to the internal clock.) $D60A00 (The pitch is set to +1.0%) $D60000 (The pitch is set to 0.0%) $A4XXXXX (Variable pitch mode is turned off. The crystal is the reference to the internal clock.) VPCTL1 VPCTL0 VP7 to 0 00 (H) FF (H) 00 (H) FF (H) 00 (H) FF (H) 00 (H) FF (H) Setting value of pitch [%] +51.2 +25.7 +25.6 +0.1 0.0 –25.5 –25.6 –48.7 Example of command setting $D60080 $D6FF80 $D600C0 $D6FFC0 $D60000 $D6FF00 $D60040 $D6E740 Command bit

– 45 – CXD2585Q $EX commands Command Data 1 SPD mode CM3 CM2 CM1 CM0 D23 D22 D21 D20 Data 2 EPWM SPDC ICAP SFSL D19 D18 D17 D16 Data 3 VC2C HIFC LPWR VPON D15 D14 D13 D12 Command bit CM3 CM2 CM1 Spindle stop mode.*1 Spindle forward rotation mode.*1 Spindle reverse rotation mode. Valid only when LPWR = 0 in any mode.*1 Rough servo mode. When the RF-PLL circuit isn't locked, this mode is used to pull the disc rotations within the RF- PLL capture range. PLL servo mode. Automatic CLVS/CLVP switching mode. Used for normal playback. CM0 Mode STOP KICK BRAKE CLVS CLVP CLVA *1 See Timing Charts 1-6 to 1-12. Command bit EPWM SPDC ICAP Crystal reference CLV servo. Used for playback in CLV-W mode.*2 Spindle control with VP0 to 7. Spindle control with the external PWM. VCO control*3 SFSL VC2C HIFC LPWR VPON INV VPCO Mode CLV-N CLV-W CAV-W CAV-W VCO-C 2 Figs. 3-1 and 3-2 show the control flow with the microcomputer software in CLV-W mode. *3 Fig. 3-3 shows the control flow with the microcomputer software in VCO-C mode.

– 46 – CXD2585Q Command SPD mode Data 4

• This sets the gain when controlling the spindle with the phase comparator in CAV-W mode. D11 D10 D9 D8 Gain CAV1 Gain CAV0 0 0 Gain CAV1 Gain CAV0 Gain 0dB –6dB –12dB –18dB Mode CLV-N CLV-W CAV-W LPWR Command KICK BRAKE STOP KICK BRAKE STOP KICK BRAKE STOP KICK BRAKE STOP KICK BRAKE STOP 1-6 (a) 1-6 (b) 1-6 (c) 1-7 (a) 1-7 (b) 1-7 (c) 1-8 (a) 1-8 (b) 1-8 (c) 1-9 (a) 1-9 (b) 1-9 (c) 1-10 (a) 1-10 (b) 1-10 (c) Timing chart Mode CLV-N CLV-W CAV-W LPWR 1-11 1-12 1-13 1-14 (EPWM = 0) 1-15 (EPWM = 0) 1-16 (EPWM = 1) 1-17 (EPWM = 1) Timing chart

– 47 – CXD2585Q Timing Chart 1-3 R ch 16bit C 2 Pointer Lch 16bit C 2 Pointer If C 2 Pointer = 1, data is N G C 2 Pointer for upper 8bits C 2 Pointer for low er 8bits R ch C 2 Pointer C 2 Pointer for upper 8bits C 2 Pointer for low er 8bits Lch C 2 Pointer LR C K W D C K C D R O M = 0 C 2PO C D R O M = 1 C 2PO 48 bit slot

– 48 – CXD2585Q Timing Chart 1-4 Level M eter Tim ing 96 clock pulses W FC K 1 2 3 96 clock pulses C R C F C R C F 1 2 3 Peak data of this section 16 bit R /LL/R 96 bit data H old section 1 2 3 80 81 96 C R C F SQ C K D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 13 D 14 L/R Peak data L/R flag Sub Q D ata See "Sub C ode Interface" 15-bit peak-data Absolute value display, LSB first 750ns to 120µs SQ C K SQ SO SQ SO

– 49 – CXD2585Q Timing Chart 1-5 M easurem ent Peak M eter Tim ing 96 clock pulses C R C F W FC K 1 2 3 M easurem ent M easurem ent 96 clock pulses C R C F C R C F 1 2 3 SQ C K

– 50 – CXD2585Q Timing Chart 1-6 CLV-N mode LPWR = 0 Timing Chart 1-7 CLV-W mode (when following the spindle rotational velocity) LPWR = 0 Timing Chart 1-8 CLV-W mode (when following the spindle rotational velocity) LPWR = 1 Timing Chart 1-9 CAV-W mode LPWR = 0 Timing Chart 1-10 CAV-W mode LPWR = 1 KIC K M D P H (a) KIC K BR AKE M D P (b) BR AKE STO P M D P (c) STO P Z Z L Z KIC K M D P H (a) KIC K BR AKE M D P (b) BR AKE STO P M D P (c) STO P Z Z L Z KIC K M D P H (a) KIC K BR AKE M D P (b) BR AKE Z STO P M D P (c) STO P Z Z KIC K M D P H (a) KIC K BR AKE M D P (b) BR AKE STO P M D P (c) STO P ZL KIC K M D P H (a) KIC K BR AKE M D P (b) BR AKE Z STO P M D P (c) STO P Z

– 51 – CXD2585Q Timing Chart 1-14 CAV-W mode EPWM = LPWR = 0 Timing Chart 1-11 CLV-N mode LPWR = 0 Timing Chart 1-12 CLV-W mode LPWR = 0 Timing Chart 1-13 CLV-W mode LPWR = 1 Timing Chart 1-15 CAV-W mode EPWM = LPWR = 1 M D P Acceleration Z D eceleration 264kH z 3.8µs M D P Acceleration Z D eceleration 132kH z 7.6µs n · 236 (ns) n = 0 to 31 M D P Acceleration Z D eceleration 264kH z 3.8µs M D P Acceleration Z264kH z 3.8µs The BR AKE pulse is m asked w hen LPW R = 1. M D P Acceleration Z264kH z 3.8µs The BR AKE pulse is m asked w hen LPW R = 1.

– 52 – CXD2585Q Timing Chart 1-16 CAV-W mode EPWM = 1, LPWR = 0 Timing Chart 1-17 CAV-W mode EPWM = LPWR = 1 PW M I M D P H L H L Acceleration D eceleration PW M I M D P H L H Z Acceleration The BR AKE pulse is m asked w hen LPW R = 1.

– 53 – CXD2585Q [2] Subcode Interface There are two methods for reading out a subcode externally. The 8-bit subcodes P to W can be read out from SBSO by inputting EXCK. Sub-Q can be read out after checking CRC of the 80 bits in the subcode frame. Sub-Q can be read out from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR comes correctly and CRCF is high. § 2-1. P to W Subcode Readout Data can be read out by inputting EXCK immediately after WFCK falls. (See Timing Chart 2-1.) § 2-2. 80-bit Sub-Q Readout Fig. 2-2 shows the peripheral block of the 80-bit Sub-Q register.

• First, Sub-Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check circuit.
• 96-bit Sub-Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, 80 bits are loaded into the parallel/serial register. When SQSO goes high after SCOR is output, the CPU determines that new data (which passed the CRC check) has been loaded.
• When the 80-bit data is loaded, the order of the MSB and LSB is inverted within each byte. As a result, although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first.
• Once the 80-bit data load is confirmed, SQCK is input so that the data can be read. The SQCK input is detected, and the retriggerable monostable multivibrator is reset while the input is low.
• The retriggerable monostable multivibrator has a time constant from 270 to 400µs. When the duration when SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval, the serial/parallel register is not loaded into the parallel/serial register.
• While the monostable multivibrator is being reset, data cannot be loaded in the peak detection parallel/serial register or the 80-bit parallel/serial register. In other words, while reading out with a clock cycle shorter than this time constant, the register will not be rewritten by CRCOK and others.
• The previously mentioned peak detection register can be connected to the shift-in of the 80-bit parallel/serial register. For ring control 1, input and output are shorted during peak meter and level meter modes. For ring control 2, input and output are shorted during peak meter mode. This is because the register is reset with each readout in level meter mode, and to prevent readout destruction in peak meter mode. As a result, the 96-bit clock must be input in peak meter mode.
• The absolute time after peak is stored in the memory in peak meter mode. (See Timing Chart 2-3.)
• The high and low intervals for SQCK should be between 750ns and 120µs.

– 54 – CXD2585Q Timing Chart 2-1 Internal PLL clock 4.3218 ± ΔM H z W FC K SC O R EXC K SBSO 750ns m ax S0 · S1 Q R W FC K SC O R EXC K SBSO S0·S1 Q R S T U V W S0·S1 P1 Q R S T U V W P1 P2 P3 Sam e Sam e

– 55 – CXD2585Q Block Diagram 2-2 888888888 O rder Inversion Peak detection LO AD C O N TR O L R ing control 2 C R C F M ix M onostable m ultivibratorC R C CABS tim e load control for peak value 16 bit P/S registerR ing control 1 SO SI SQ SO SQ C KSH IFTSH IFT SU BQ LD SOH G F E D C B A A B C D E F G H SI 80 bit P/S R egister 80 bit S/P R egister (AFR AM ) (ASEC ) (AM IN ) AD D R S C TR L SINSU BQ LD LD LD LD LD LD LD

– 56 – CXD2585Q Timing Chart 2-3 1 2 3 91 92 93 94 95 96 97 98 W FC K SC O R SQ SO SQ C K M onostable M ultivibrator (Internal) C R C F1 D eterm ined by m ode C R C F2 80 or 96 C lock R egister load forbidder 270 to 400µs w hen SQ C K = high. 750ns to 120µs 300ns m ax C R C F AD R 0 AD R 1 AD R 2 AD R 3 C TL0 C TL1 C TL2 C TL3 SQ C K SQ SO 1 2 3 C R C F1

– 57 – CXD2585Q Timing Chart 2-4 Signal PER0 to 7 FOK GFS LOCK EMPH ALOCK VF0 to 9 RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB. Focus OK. High when the frame sync and the insertion protection timing match. GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low. High when the playback disc has emphasis. GFS is sampled at 460Hz; when GFS is high eight consecutive samples, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low. Used in CAV-W mode. The result obtained by measuring the rotational velocity of the disc. (See Timing Chart 2-5.) VF0 = LSB, VF9 = MSB. No C1 errors; C1 pointer reset One C1 error corrected; C1 pointer reset No C1 errors; C1 pointer set One C1 error corrected; C1 pointer set Two C1 errors corrected; C1 pointer set C1 correction impossible; C1 pointer set C1F1 C1F0 Description C2F2 No C2 errors; C2 pointer reset One C2 error corrected; C2 pointer reset Two C2 errors corrected; C2 pointer reset Three C2 errors corrected; C2 pointer reset Four C2 errors corrected; C2 pointer reset C2 correction impossible; C1 pointer copy C2 correction impossible; C2 pointer set C2F1 C2F0 Description Exam ple: $802000 latch Set SQ C K high during this interval. Internal signal latch PER 0 PER 1 PER 2 PER 3 PER 4 PER 5 PER 6 PER 7 C 1F0 C 1F1 C 1F2 C 2F0 C 2F1 C 2F2 FO K G FS LO C K EM PH 750ns or m oreXLAT SQ C K SQ SO ALO C K VF0 VF1 VF2 VF3 VF4 VF5 VF6 VF9VF7 VF8

– 58 – CXD2585Q Timing Chart 2-5 The relative velocity of the disc can be obtained with the following equation. R = (R: Relative velocity, m: Measurement results) VF0 to 9 is the result obtained by counting V16M/2 pulses while the reference signal (132.2kHz) generated from XTAL (XTAI, XTAO) (384Fs) is high. This value is 31 when the disc is rotating at normal speed and 63 when it is rotating at double speed (when DSPB is low). (m + 1) M easurem ent interval (approxim ately 3.8µs) R eference w indow (132.2kH z) M easurem ent pulse (V16M /2) M easurem ent counter VF0 to 9 Load m

– 59 – CXD2585Q Timing Chart 2-6 18 17C 1 M SB 19 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0537005370 C 1 error rate C 2 error rate XLAT SQ C K SQ SO

– 60 – CXD2585Q [3] Description of Modes This LSI has three basic operating modes using a combination of spindle control and the PLL. The operations for each mode are described below. § 3-1. CLV-N Mode This mode is compatible with the CXD2510Q, and operation is the same as for conventional control. The PLL capture range is ±150kHz. § 3-2. CLV-W Mode This is the wide capture range mode. This mode allows the PLL to follow the rotational velocity of the disc. This rotational following control has two types: using the built-in VCO2 or providing an external VCO. The spindle is the same CLV servo as for the conventional series. Operation using the built-in VCO2 is described below. (When using an external VCO, input the signal from the VPCO pin to the low-pass filter, use the output from the low-pass filter as the control voltage for the external VCO, and input the oscillation from the VCO to the V16M pin.) When starting to rotate the disc and/or speeding up to the lock range from the condition where the disc is stopped, CAV-W mode should be used. Specifically, first send $E665X to set CAV-W mode and kick the disc, then send $E60CX to set CLV-W mode if ALOCK is high, which can be read out serially from the SQSO pin. CLV-W mode can be used while ALOCK is high. The microcomputer monitors the serial data output, and must return the operation to the speed adjusting state (CAV-W mode) when ALOCK becomes low. The control flow according to the microcomputer software in CLV-W mode is shown in Fig. 3-2. In CLV-W mode (normal), low power consumption is achieved by setting LPWR to high. Control was formerly performed by applying acceleration and deceleration pulses to the spindle motor. However, when LPWR is set high, deceleration pulses are not output, thereby achieving low power consumption mode. Note)The capture range for this mode is theoretically up to the signal processing limit. § 3-3. CAV-W Mode This is CAV mode. In this mode, the external clock is fixed and it is possible to control the spindle to the desired rotational velocity. The rotational velocity is determined by the VP0 to VP7 setting values or the external PWM. When controlling the spindle with VP0 to VP7, setting CAV-W mode with the $E665X command and controlling VP0 to VP7 with the $DX commands allows the rotational velocity to be varied from low speed to 4· speed. (See "$DX commands".) Also, when controlling the spindle with the external PWM, the PWMI pin is binary input which becomes KICK during high intervals and BRAKE during low intervals. The microcomputer can know the rotational velocity using V16M. The reference frequency for the velocity measurement is a signal of 132.3kHz obtained by dividing XTAL (XTAI, XTAO) (384Fs) by 128. The velocity is obtained by counting the half of V16M pulses while the reference is high, and the result is output from the new CPU interface as 10 bits (VP0 to VP9). These measurement results are 31 when the disc is rotating at normal speed or 127 when it is rotating at 4· speed. These values match those of the 256 - n for control with VP0 to VP7. (See Table 2-5 and Fig. 2-6.) In CAV-W mode, the spindle is set to the desired rotational velocity and the operation speed for the entire system follows this rotational velocity. Therefore, the cycles for the Fs system clock, PCM data and others output from this LSI change according to the rotational velocity of the disc. Note)The capture range for this mode is theoretically up to the signal processing limit. Note)Set FLFC to 1 for this mode

– 61 – CXD2585Q § 3-4. VCO-C Mode This is VCO control mode. In this mode, the V16M oscillation frequency can be controlled by setting $D commands VP0 to VP7 and VPCTL0, 1. The V16M oscillation frequency can be expressed by the following equation. n: VP0 to 7 setting value l: VPCTL0, 1 setting value The VCO1 oscillation frequency is determined by V16M. The VCO1 frequency can be expressed by the following equation.

• When DSPB = 0
• When DSPB = 1 l (256 – n)V16M = 32 49VCO1 = V16M · 24 49VCO1 = V16M · 16

– 62 – CXD2585Q Fig. 3-1. Disc Stop to Regular Playback in CLV-W Mode CLV-W Mode Fig. 3-2. CLV-W Mode Flow Chart C AV-W C LVS C LV-W C LVP R otational velocity Target speed O peration m ode Spindle m ode Tim e KIC K LO C K ALO C K N O YES KIC K $E8000 M ute O FF $A00XXXX ALO C K = H ? N O YES ALO C K = L ? C LV-W M O D E STAR T C AV-W $E665X (C LVA) C LV-W $E60C X (C LVA) (W FC K PLL)

– 63 – CXD2585Q VCO-C Mode Fig. 3-3. Access Flow Chart Using VCO Control R ? (H ow m any m inutes of absolute tim e?) Access STAR T Transfer $E00510 (C alculate n) Transfer $D X XX Track Jum p Subroutine Transfer $E66500 Access EN D W hat is the ultim ate speed m ultiple? C alculate VP0 to VP7. Sw itch to VC O control m ode. EPW M = SPD C = IC AP = SFSL = VC 2C = LPW R = 0 H IFC = VPO N = 1 Transfer VP0 to VP7. ( corresponds to VP0 to VP7.) Sw itch to norm al-speed playback m ode. EPW M = SFSL = VC 2C = LPW R = 0 SPD C = IC AP = H IFC = VPO N = 1

– 64 – CXD2585Q [4] Description of other functions § 4-1. Channel Clock Regeneration by Digital PLL Circuit

• The channel clock is necessary for demodulating the EFM signal regenerated by the optical system. Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to 11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a result, T, that is the channel clock, is necessary. In an actual player, a PLL is necessary for regenerating the channel clock because the fluctuation in the spindle rotation alters the width of the EFM signal pulses. The block diagram of this PLL is shown in Fig. 4-1. The CXD2585Q has a built-in three-stage PLL.
• The first-stage PLL is a wide-band PLL. When using the internal VCO2, an external LPF is necessary; when not using the internal VCO2, external LPF and VCO are necessary. The output of this first-stage PLL is used as a reference for all clocks within the LSI.
• The second-stage PLL regenerates the high-frequency clock needed by the third-stage digital PLL.
• The third-stage PLL is a digital PLL that regenerates the actual channel clock.
• The digital PLL in CLV-N mode has a secondary loop, and is controlled by the primary loop (phase) and the secondary loop (frequency). When FLFC = 1, the secondary loop can be turned off. High frequency components such as 3T and 4T may contain deviations. In such cases, turning the secondary loop off yields better playability. However, in this case the capture range becomes –50kHz.
• A new digital PLL has been provided for CLV-W mode to follow the rotational velocity of the disc in addition to the conventional secondary loop.

– 65 – CXD2585Q Block Diagram 4-1 XTSL 1/2 1/32 1/n1/2 M icrocom puter control n = 1 to 256 (VP7 to 0) 1/K (KSL1, 0) C LV-W C AV-W Spindle rotation inform ation C LV-N C LV-W C AV-W /C LV-N Phase com parator Selector LPF 2/1 M U X VPO N 1/M 1/N VC O SEL2 VC O 2 Phase com parator VC O 1 VC O SEL1 1/K (KSL3, 2) D igital PLL R FPLL VPC O VC TL V16M PC O FILI FILO C LTV XTAI C lock input 1/l l = 1, 2, 3, 4 (VPC TL0, 1)

§ 4-2. Frame sync protection

• In normal speed playback, a frame sync is recorded approximately every 136µs (7.35kHz). This signal is used as a reference to recognize the data within a frame. Conversely, if the frame sync cannot be recognized, the data is processed as error data because the data cannot be recognized. As a result, recognizing the frame sync properly is extremely important for improving playability.
• In the CXD2585Q, window protection and forward protection/backward protection have been adopted for frame sync protection. These functions achieve very powerful frame sync protection. There are two window widths; one for cases where a rotational disturbance affects the player and the other for cases where there is no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is set to 13 *, and the backward protection counter to 3*. Concretely, when the frame sync is being played back normally and then cannot be detected due to scratches, a maximum of 13 frames are inserted. If the frame sync cannot be detected for 13 frames or more, the window opens to resynchronize the frame sync. In addition, immediately after the window opens and the resynchronization is executed, if a proper frame sync cannot be detected within 3 frames, the window opens immediately. * Default values. These values can be set as desired by $C commands SFP0 to SFP3 and SRP0 to SRP3. § 4-3. Error Correction
• In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the code is created with 28-byte information and 4-byte C1 parity. For C2 correction, the code is created with 24-byte information and 4-byte parity. Both C1 and C2 are Reed Solomon codes with a minimum distance of 5.
• The CXD2585Q uses refined super strategy to achieve double correction for C1 and quadruple correction for C2.
• In addition, to prevent C2 miscorrection, a C1 pointer is attached to data after C1 correction according to the C1 error status, the playback status of the EFM signal, and the operating status of the player.
• The correction status can be monitored externally. See Table 4-2.
• When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held or an average value interpolation was made for the data. MNT3 No C1 errors; C1 pointer reset One C1 error corrected; C1 pointer reset No C1 errors; C1 pointer set One C1 error corrected; C1 pointer set Two C1 errors corrected; C1 pointer set C1 correction impossible; C1 pointer set No C2 errors; C2 pointer reset One C2 error corrected; C2 pointer reset Two C2 errors corrected; C2 pointer reset Three C2 errors corrected; C2 pointer reset Four C2 errors corrected; C2 pointer reset C2 correction impossible; C1 pointer copy C2 correction impossible; C2 pointer set MNT2 MNT1 MNT0 Description Table 4-2. – 66 –

– 67 – CXD2585Q Timing Chart 4-3 § 4-4. DA Interface

• The CXD2585Q supports the 48-bit slot interface as the DA interface. 48-bit slot interface This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is high, the data is for the left channel. N orm al-speed PB 400 to 500ns R FC K M N T3 M N T1 M N T0 t = D ependent on error condition C 1 correction C 2 correction StrobeStrobe M N T2

– 68 – CXD2585Q Timing Chart 4-4 LR C K (44.1K) D A15 (2.12M ) W D C K D A16 LR C K (88.2K) D A15 (4.23M ) W D C K D A16 48bit slot N orm al-Speed Playback PSSL = L 1 24 R 0 Lch M SB (15) L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R ch M SB Lch M SB (15) R ch M SB 2 3 4 5 6 7 8 9 10 11 12 48bit slot D ouble-Speed Playback 1 2 L0R 0

– 69 – CXD2585Q § 4-5. Digital Out There are three Digital Out: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. The CXD2585Q supports type 2 form 1. The channel status clock accuracy is automatically set to level II when using the crystal clock and to level III in CAV-W mode or variable pitch mode. In addition, Sub-Q data which are matched twice in succession after a CRC check are input to the first four bits (bits 0 to 3). DOUT is output when the crystal is 34MHz and DSPB is set to 1 with XTSL high in CLV-N or CLV-W mode. Therefore, set MD2 to 0 and turn DOUT off. Table 4-5. 0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0 ID 0 ID 1 C O PY Em ph 0 0 0 0 1 0 0 0 0 0 0 0 From sub Q0 176 Sub-Q control bits that m atched tw ice w ith C R C O K D igital O ut C bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VPO N or VAR IO N : 1 X'tal: 0 bit0 to 3 bit29

– 70 – CXD2585Q § 4-6. Servo Auto Sequence This function performs a series of controls, including auto focus and track jumps. When the auto sequence command is received from the CPU, auto focus, 1-track jump, 2N-track jump, fine search and M-track move are executed automatically. The servo block operates according to the built-in program during the auto sequence execution (when XBUSY = low), so that commands from the CPU, that is $0, 1, 2 and 3 commands, are not accepted. ($4 to E commands are accepted.) In addition, when using the auto sequence, turn the A.SEQ of register 9 on. When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of 100µs after that point. This is to prevent the transfer of erroneous data to the servo when XBUSY changes from low to high by the monostable multivibrator, which is reset by CLOK being low (when XBUSY is low). In addition, a MAX timer is built into this LSI as a countermeasure against abnormal operation due to external disturbances, etc. When the auto sequence command is sent from the CPU, this command assumes a $4XY format, in which X specifies the command and Y sets the MAX timer value and timer range. If the executed auto sequence command does not terminate within the set timer value, the auto sequence is interrupted (like $40). See [1] "$4X commands" concerning the timer value and range. Also, the MAX timer is invalidated by inputting $4X0. Although this command is explained in the format of $4X in the following command descriptions, the timer value and timer range are actually sent together from the CPU. (a) Auto focus ($47) Focus search-up is performed, FOK and FZC are checked, and the focus servo is turned on. If $47 is received from the CPU, the focus servo is turned on according to Fig. 4-6. The auto focus starts with focus search-up, and note that the pickup should be lowered beforehand (focus search-down). In addition, blind E of register 5 is used to eliminate FZC chattering. Concretely, the focus servo is turned on at the falling edge of FZC after FZC has been continuously high for a longer time than E. (b) Track jump 1, 10 and 2N-track jumps are performed respectively. Always use this when the focus, tracking, and sled servos are on. Note that tracking gain-up and braking-on ($17) should be sent beforehand because they are not involved in this sequence.

• 1-track jump When $48 ($49 for REV) is received from the CPU, a FWD (REV) 1-track jump is performed in accordance with Fig. 4-7. Set blind A and brake B with register 5.
• 10-track jump When $4A ($4B for REV) is received from the CPU, a FWD (REV) 10-track jump is performed an accordance with Fig. 4-8. The principal difference from the 1-track jump is to kick the sled. In addition, after kicking the actuator, when 5 tracks have been counted through COUT, the brake is applied to the actuator. Then, when the actuator speed is found to have slowed up enough (determined by the COUT cycle becoming longer than the overflow C set with register 5), the tracking and sled servos are turned on.

– 71 – CXD2585Q

• 2N-track jump When $4C ($4D for REV) is received from the CPU, a FWD (REV) 2N-track jump is performed in accordance with Fig. 4-9. The track jump count N is set with register 7. Although N can be set to 2 16 tracks, note that the setting is actually limited by the actuator. COUT is used for counting the number of jumps when N is less than 16, and MIRR is used with N is 16 or more. Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is that after the tracking servo is turned on, the sled continues to move only for "D", set with register 6.
• Fine search When $44 ($45 for REV) is received from the CPU, a FWD (REV) fine search (N-track jump) is performed in accordance with Fig. 4-10. The differences from a 2N-track jump are that a higher precision is achieved by controlling the traverse speed, and a longer distance jump is achieved by controlling the sled. The track jump count is set with register 7. N can be set to 2 16 tracks. After kicking the actuator and sled, the traverse speed is controlled based on the overflow G. Set kick D and F with register 6 and overflow G with register 5. Also, sled speed control during traverse can be turned off by causing COMP to fall. Set the number of tracks during which COMP falls with register B. After N tracks have been counted through COUT, the brake is applied to the actuator and sled. (This is performed by turning on the tracking servo for the actuator, and by kicking the sled in the opposite direction during the time for kick D set with register 6.) Then, the tracking and sled servos are turned on. Set overflow G to the speed required to slow up just before the track jump terminates. (The speed should be such that it will come on-track when the tracking servo turns on at the termination of the track jump.) For example, set the target track count N – a for the traverse monitor counter which is set with register B, and COMP will be monitored. When the falling edge of this COMP is detected, overflow G can be reset.
• M-track move When $4E ($4F for REV) is received from the CPU, a FWD (REV) M-track move is performed in accordance with Fig. 4-11. M can be set to 2 16 tracks. Like the 2N-track jump, COUT is used for counting the number of moves when M is less than 16, and MIRR is used when M is 16 or more. The M-track move is executed by moving only the sled, and is therefore suited for moving across several thousand to several ten-thousand tracks. In addition, the track and sled servos are turned off after M tracks have been counted through COUT or MIRR unlike for the other jumps. Transfer $25 from the microcomputer after the actuator has stabilized.

– 72 – CXD2585Q Fig. 4-6-(a). Auto Focus Flow Chart Fig. 4-6-(b). Auto Focus Timing Chart Auto focus Focus search up FO K = H N O YES FZC = H N O YES FZC = L N O YES EN D Focus servo O N C heck w hether FZC is continuously high for the period of tim e E set w ith register 5. XLAT $47 Latch $03 Blind E $08 FO K FZC BU SY C om m and for D SSP

– 73 – CXD2585Q Fig. 4-7-(a). 1-Track Jump Flow Chart Fig. 4-7-(b). 1-Track Jump Timing Chart

1 Track

(Blind A) C O U T = Track R EV kick W AIT (Brake B) Track, sled servo O N (FW D kick for R EV jum p) (R EV kick for R EV jum p) XLAT C O U T BU SY C om m and for D SSP $48 (R EV = $49) Latch $28 ($2C ) Blind A Brake B $2C ($28) $25

– 74 – CXD2585Q Fig. 4-8-(a). 10-Track Jump Flow Chart Fig. 4-8-(b). 10-Track Jump Timing Chart

10 Track

Track, sled FW D kick W AIT (Blind A) C O U T = 5 ? Track, R EV kick Track, sled servo O N C hecks w hether the C O U T cycle is longer than overflow C . (C ounts C O U T × 5) N O YES C = O verflow ? C O U T $4A (R EV = $4B) Latch Blind A $2A ($2F) C O U T 5 count $2E ($2B) O verflow C $25 XLAT BU SY C om m and for D SSP

– 75 – CXD2585Q Fig. 4-9-(a). 2N-Track Jump Flow Chart Fig. 4-9-(b). 2N-Track Jump Timing Chart 2N Track N O YES EN D Track, sled FW D kick W AIT (Blind A) C O U T (M IR R ) = N Track R EV kick Track servo O N N O YES C = O verflow W AIT (Kick D ) Sled servo O N C ounts C O U T for the first 16 tim es and M IR R for m ore tim es. XLAT Blind A $2A ($2F) C O U T (M IR R ) N count $2E ($2B) O verflow C Kick D $26 ($27) $25 $4C (R EV = $4D ) Latch C O U T (M IR R ) BU SY C om m and for D SSP

– 76 – CXD2585Q Fig. 4-10-(a). Fine Search Flow Chart Fig. 4-10-(b). Fine Search Timing Chart Track Servo O N Sled FW D Kick Fine Search W AIT (Kick D ) Track Sled FW D Kick W AIT (Kick F) Traverse Speed C trl (O verflow G ) C O U T = N ? Track Servo O N Sled R EV Kick W AIT (Kick D ) Track Sled Servo O N EN D YES N O Traverse Speed C ontrol (O verflow G ) C O U T N count Kick FKick D $26 ($27) $2A ($2F) $27 ($26) $25 $44 (R EV = $45) latch XLAT C O U T Kick D BU SY C om m and for D SSP

– 77 – CXD2585Q Fig. 4-11-(a). M-Track Move Flow Chart Fig. 4-11-(b). M-Track Move Timing Chart M Track M ove N O YES EN D Track Servo O FF Sled FW D Kick W AIT (Blind A) C O U T (M IR R ) = M Track, Sled Servo O FF C ounts C O U T for M < 16. C ounts M IR R for M ≥ 16. XLAT Blind A $22 ($23) C O U T (M IR R ) M count $20 $4E (R EV = $4F) Latch C O U T (M IR R ) BU SY C om m and for D SSP

– 78 – CXD2585Q § 4-7. Digital CLV Fig. 4-12 shows the block diagram. Digital CLV outputs MDS error and MDP error signals with PWM, with the sampling frequency increased up to 130kHz during normal-speed playback in CLVS, CLVP and other modes. In addition, the digital spindle servo gain is variable. Fig. 4-12. Block Diagram CLVS U/D: Up/down signal from CLVS servo MDS error: Frequency error for CLVP servo MDP error: Phase error for CLVP servo PWMI: Spindle drive signal from the microcomputer for CAV servo M D P D igital C LV C LVS U /D M D S Error M D P Error C LV P/S M easure M easure 2/1 M U X O ver Sam pling Filter-1 G ain M D S M ux C LV P/SO ver Sam pling Filter-2 N oise Shape M odulationKIC K, BR AKE, STO P M ode Select G ain D C LV G ain M D P LPW R PW M I

– 79 – CXD2585Q § 4-8. Playback Speed In the CXD2585Q, the following playback modes can be selected through different combinations of XTAI, XTSL pin, double-speed command (DSPB), VCO1 selection command (VCOSEL1), VCO1 frequency division commands (KSL3, KSL2) and command transfer rate selector (ASHS) in CLV-N or CLV-W mode. Mode XTAI 768Fs 768Fs 768Fs 768Fs 384Fs 384Fs 384Fs XTSL DSPB VCOSEL1 * ASHS Playback speed Error correction*2 C1: double; C2: quadruple C1: double; C2: double C1: double; C2: quadruple C1: double; C2: double C1: double; C2: quadruple C1: double; C2: double C1: double; C2: double 1 Actually, the optimal value should be used together with KSL3 and KSL2. *2 When $8 ERC4 = 1, C2 is for quadruple correction with DSPB = 1. The playback speed can be varied by setting VP0 to VP7 in CAV-W mode. See "[3] Description of Modes" for details.

– 80 – CXD2585Q § 4-9. Asymmetry Correction Fig. 4-13 shows the block diagram and circuit example. Fig. 4-15. Asymmetry Correction Application Circuit ASYE R FAC R 1 R 1 ASYO ASYI R 1 2 R 2 5 BIAS R 1 R 1 R 2

– 81 – CXD2585Q §4-10. CD TEXT Data Demodulation

• In order to demodulate the CD TEXT data, set the command $8 Data 6 D3 TXON to 1. During TXON = 1, connect EXCK to low and do not use the data output from SBSO because the CD TEXT demodulation circuit uses EXCK and the SBSO pin exclusively. It requires 26.7ms (max.) to demodulate the CD TEXT data correctly after TXON is set to 1.
• The CD TEXT data is output by switching the SQSO pin with the command. The CD TEXT data output is enabled by setting the command $8 Data 6 D2 TXOUT to 1. To read data, the readout clock should be input to SQCK.
• The readable data are the CRC counting results for the each pack and the CD TEXT data (16 bytes) except for CRC data.
• When the CD TEXT data is read, the order of the MSB and LSB is inverted within each byte. As a result, although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first.
• Data which can be stored in the LSI is 1 packet (4 packs). Fig. 4-14. Block Diagram of CD TEXT Demodulation Circuit SQ C K SQ SO TXO U T Subcode D ecoder C D TEXT D ecoder TXO N SBSO EXC K

– 82 – CXD2585Q Fig. 4-15. CD TEXT Data Timing Chart C R C C R C C R C C R C 1 0 0 0 0 S2 R 2 W 1 V1 U 1 T1 S1 R 1 U 3 T3 S3 R 3 W 2 V2 U 2 T2 W 4 V4 U 4 T4 S4 C R C D ata ID 1 (Pack1) ID 2 (Pack1) ID 3 (Pack1) 16Byte16Byte16Byte16Byte4bit4bitSubcode Q D ata SC O R TXO U T (com m and) SQ C K SQ SO SQ C K TXO U T (com m and) LSB M SB LSB M SB LSB C R C 0 Pack1 Pack2 Pack3 Pack4 C R C FC R C F

80 C lock

520 C lock

– 83 – CXD2585Q [5] Description of Servo Signal Processing System Functions and Commands §5-1. General Description of Servo Signal Processing System (VDD : Supply voltage) Focus servo Sampling rate: 88.2kHz (when MCK = 128Fs) Input range: 0.3VDD to 0.7VDD Output format: 7-bit PWM Other: Offset cancel Focus bias adjustment Focus search Gain-down function Defect countermeasure Auto gain control Tracking servo Sampling rate: 88.2kHz (when MCK = 128Fs) Input range: 0.3V DD to 0.7VDD Output format: 7-bit PWM Other: Offset cancel E:F balance adjustment Track jump Gain-up function Defect countermeasure Drive cancel Auto gain control Vibration countermeasure Sled servo Sampling rate: 345Hz (when MCK = 128Fs) Input range: 0.3V DD to 0.7VDD Output format: 7-bit PWM Other: Sled move FOK, MIRR, DFCT signal generation RF signal sampling rate:1.4MHz (when MCK = 128Fs) Input range: 0.43VDD to VDD Other: RF zero level automatic measurement

– 84 – CXD2585Q §5-2. Digital Servo Block Master Clock (MCK) The clock with the 2/3 frequency of the crystal is supplied to the digital servo block. XT4D and XT2D are $3F commands, and XT1D is $3E command. (Default = 0) The digital servo block is designed with an MCK frequency of 5.6448MHz (128Fs) as typical. Mode 384Fs 384Fs 384Fs 768Fs 768Fs 768Fs 768Fs 256Fs 256Fs 256Fs 512Fs 512Fs 512Fs 512Fs 256Fs 128Fs 128Fs 512Fs 256Fs 128Fs 128Fs XTAI FSTO XTSL XT4D XT2D XT1D Frequency division ratioMCK Fs = 44.1kHz, *: Don’t care Table 5-1.

– 85 – CXD2585Q § 5-3. DC Offset Cancel [AVRG (Average) Measurement and Compensation] (See Fig. 5-3.) The CXD2585Q can measure the average of RFDC, VC, FE and TE and compensate these signals using the measurement results to control the servo effectively. This AVRG measurement and compensation is necessary to initialize the CXD2585Q, and is able to cancel the DC offset. AVRG measurement takes the levels applied to the VC, FE, RFDC and TE pins as the digital average of 256 samples, and then loads these values into each AVRG register. The AVRG measurement commands are D15 (VCLM), D13 (FLM), D11 (RFLM) and D4 (TLM) of $38. Measurement is on when the respective command is set to 1. AVRG measurement requires approximately 2.9ms to 5.8ms (when MCK = 128Fs) after the command is received. The completion of AVRG measurement operation can be monitored by the SENS pin. (See Timing Chart 5-2.) Monitoring requires that the upper 8 bits of the command register are 38 (Hex). Timing Chart 5-2. <Measurement> VC AVRG: The VC DC offset (VC AVRG) which is the center voltage for the system is measured and used to compensate the FE, TE and SE signals. FE AVRG: The FE DC offset (FE AVRG) is measured and used to compensate the FE and FZC signals. TE AVRG: The TE DC offset (TE AVRG) is measured and used to compensate the TE and SE signals. RF AVRG: The RF DC offset (RF AVRG) is measured and used to compensate the RFDC signal. <Compensation> RFLC: (RF signal – RF AVRG) is input to the RF In register. "00" is input when the RF signal is lower than RF AVRG. TLC0: (TE signal – VC AVRG) is input to the TRK In register. TLC1: (TE signal – TE AVRG) is input to the TRK In register. VCLC: (FE signal – VC AVRG) is input to the FCS In register. FLC1: (FE signal – FE AVRG) is input to the FCS In register. FLC0: (FE signal – FE AVRG) is input to the FZC register. Two methods of canceling the DC offset are assumed for the CXD2585Q. These methods are shown in Figs. 5-3a and 5-3b. An example of AVRG measurement and compensation commands is shown below. $38 08 00 (RF AVRG measurement) $38 20 00 (FE AVRG measurement) $38 00 10 (TE AVRG measurement) $38 14 0A (Compensation on [RFLC, FLC0, FLC1, TLC1], corresponds to Fig. 5-3a.) See the description of $38 for these commands. XLAT SEN S ( = XAVEBSY) M ax. 1µs AVR G m easurem ent com pleted 2.9 to 5.8m s

– 86 – CXD2585Q § 5-4. E:F Balance Adjustment Function (See Fig. 5-3.) When the disc is rotated with the laser on, and with the FCS (focus) servo on via FCS Search (focus search), the traverse waveform appears in the TE signal due to disc eccentricity. In this condition, the low-frequency component can be extracted from the TE signal using the built-in TRK hold filter by setting D5 (TBLM) of $38 to 1. The extracted low-frequency component is loaded into the TRVSC register as a digital value, and the TRVSC register value is established when TBLM returns to "0". Next, setting D2 (TLC2) of $38 to 1 compensates the values obtained from the TE and SE input pins with the TRVSC register value (subtraction), allowing the E:F balance offset to be adjusted. (See Fig. 5-3.) § 5-5. FCS Bias (Focus Bias) Adjustment Function The FBIAS register value can be added to the FCS servo filter input by setting D14 (FBON) of $3A to 1. (See Fig. 5-3.) When D11 = 0 and D10 = 1 is set by $34F, the FBIAS register value can be written using the 9-bit value of D9 to D1 (D9: MSB). In addition, the RF jitter can be monitored by setting the $8 command SOCT to 1. (See "DSP Block Timing Chart".) The FBIAS register can be used as a counter by setting D13 (FBSS) of $3A to 1. The FBIAS register functions as an up counter when D12 (FBUP) of $3A = 1, and as a down counter when D12 (FBUP) of $3A = 0. The number of up and down steps can be changed by setting D11 and D10 (FBV1 and FBV0) of $3A. When using the FBIAS register as a counter, the counter stops when the value set beforehand in FBL9 to FBL1 of $34 matches the FCSBIAS value. Also, if the upper 8 bits of the command register are $3A at this time, SENS goes to high and the counter stop can be monitored. Here, assume the FBIAS setting value FB9 to FB1 and the FBIAS LIMIT value FBL9 to FBL1 are set in status A. For example, if command registers FBUP = 0, FBV1 = 0, FBV0 = 0 and FBSS = 1 are set from this status, down count starts from status A and approaches the set LIMIT value. When the LIMIT value is reached and the FBIAS value matches FBL9 to FBL1, the counter stops and the SENS pin goes to high. Note that the up/down counter counts at each sampling cycle of the focus servo filter. The number of steps by which the count value changes can be selected from 1, 2, 4 or 8 steps by FBV1 and FBV0. When converted to FE input, 1 step corresponds to 1/512 · V DD · 0.4. A B C FBIAS setting value (FB9 to FB1) LIM IT value (FBL9 to FBL1) SEN S pin A: R egister m ode B: C ounter m ode C : C ounter m ode (w hen stopped)

– 87 – CXD2585Q Fig. 5-3a. Fig. 5-3b. TE AVR G register TLC 1 TR VSC register TLC 2 – – To TR K In registerTE from A/D FE AVR G register FLC 1 FBIAS register FBO N To FC S In register FLC 0 To FZC register FE from A/D R FLC To R F In registerR FD C from A/D R F AVR G register – – Tp SLD In registerSE from A/D TLC 1 · TLD 1 TLC 2 · TLD 2 VC AVR G register TLC 0 TR VSC register TLC 2 – – To TR K In registerTE from A/D FBIAS register FBO N To FC S In register VC LC To FZC register FE from A/D – R FLC To R F In registerR FD C from A/D R F AVR G register – – To SLD In registerSE from A/D TLC 0 · TLD 0 TLC 2 · TLD 2 +FE AVR G register FLC 0

– 88 – CXD2585Q § 5-6. AGCNTL (Automatic Gain Control) Function The AGCNTL function automatically adjusts the filter internal gain in order to obtain the appropriate servo loop gain. AGCNTL not only copes with the sensitivity variation of the actuator and photo diode, etc., but also obtains the optimal gain for each disc. The AGCNTL command is sent when each servo is turned on. During AGCNTL operation, if the upper 8 bits of the command register are 38 (Hex), the completion of AGCNTL operation can be confirmed by monitoring the SENS pin. (See Timing Chart 5-4 and "Description of SENS Signals".) Setting D9 and D8 of $38 to 1 set FCS (focus) and TRK (tracking) respectively to AGCNTL operation. Note)During AGCNTL operation, each servo filter gain must be normal, and the anti-shock circuit (described hereafter) must be disabled. Timing Chart 5-4. Coefficient K13 changes for AGF (focus AGCNTL) and coefficients K23 and K07 change for AGT (tracking AGCNTL) due to AGCNTL. These coefficients change from 01 to 7F (Hex), and they must also be set within this range when written externally. After AGCNTL operation has completed, these coefficient values can be confirmed by reading them out from the SENS pin with the serial readout function (described hereafter). AGCNTL related settings The following settings can be changed with $35, $36 and $37. FG6 to FG0;AGF convergence gain setting, effective setting range: 00 to 57 (Hex) TG6 to TG0;AGT convergence gain setting, effective setting range: 00 to 57 (Hex) AGS; Self-stop on/off AGJ; Convergence completion judgment time AGGF; Internally generated sine wave amplitude (AGF) AGGT; Internally generated sine wave amplitude (AGT) AGV1; AGCNTL sensitivity 1 (during rough adjustment) AGV2; AGCNTL sensitivity 2 (during fine adjustment) AGHS; Rough adjustment on/off AGHT; Fine adjustment time Note)Converging servo loop gain values can be changed with the FG6 to FG0 and TG6 to TG0 setting values. In addition, these setting values must be within the effective setting range. The default settings aim for 0dB at 1kHz. However, since convergence values vary according to the characteristics of each constituent element of the servo loop, FG and TG values should be set as necessary. XLAT SEN S ( = AG O K) M ax. 11.4µs AG C N TL com pletion

– 89 – CXD2585Q AGCNTL and default operation have two stages. In the first stage, rough adjustment is performed with high sensitivity for a certain period of time (select 256/128ms with AGHT, when MCK = 128Fs), and the AGCNTL coefficient approaches the appropriate value. The sensitivity at this time can be selected from two types with AGV1. In the second stage, the AGCNTL coefficient is finely adjusted with relatively low sensitivity to further approach the appropriate value. The sensitivity for the second stage can be selected from two types with AGV2. In the second stage of default operation, when the AGCNTL coefficient reaches the appropriate value and stops changing, the CXD2585Q confirms that the AGCNTL coefficient has not changed for a certain period of time (select 63/31ms with AGHJ, when MCK = 128Fs), and then completes AGCNTL operation. (Self stop mode) This self-stop mode can be canceled by setting AGS to 0. In addition, the first stage is omitted for AGCNTL operation when AGHS is set to 0. An example of AGCNTL coefficient transitions during AGCNTL operation with various settings is shown in Fig. 5-5. Fig. 5-5. Note)Fig. 5-5 shows the case where the AGCNTL coefficient converges from the initial value to a smaller value. Initial value SEN S AG C N TL start AG C N TL com pletion C onvergence value AG C N TL coefficient value Slope AG V1 AG H T AG J Slope AG V2

– 90 – CXD2585Q § 5-7. FCS Servo and FCS Search (Focus Search) The FCS servo is controlled by the 8-bit serial command $0X. (See Table 5-6.) Register name Command D23 to D20 D19 to D16 1 0 * * 1 1 * * 0 * 0 * 0 * 1 * 0 * 1 0 0 * 1 1 FOCUS SERVO ON (FOCUS GAIN NORMAL) FOCUS SERVO ON (FOCUS GAIN DOWN) FOCUS SERVO OFF, 0V OUT FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT FOCUS SEARCH VOLTAGE DOWN FOCUS SEARCH VOLTAGE UP 0 0 0 0FOCUS CONTROL0 Table 5-6. FCS Search FCS search is required in the course of turning on the FCS servo. Fig. 5-7shows the signals for sending commands $00 fi $02 fi $03 and performing only FCS search operation. Fig. 5-8 shows the signals for sending $08 (FCS on) after that. Fig. 5-7. Fig. 5-8. *: Don't care FC SD R V R F FO K FE FZC FZC com parator level $00 $02 $03 FC SD R V R F FO K FE FZC $00 $02 $03 $08

– 91 – CXD2585Q § 5-8. TRK (Tracking) and SLD (Sled) Servo Control The TRK and SLD servos are controlled by the 8-bit command $2X. (See Table 5-9.) When the upper 4 bits of the serial data are 2 (Hex), TZC is output to the SENS pin. Register name Command D23 to D20 D19 to D16 TRACKING SE RVO OFF TRACKING SE RVO ON FORWARD TRACK JUMP REVERSE TRACK JUMP SLED SE RVO OFF SLED SE RVO ON FORWARD SLED MOVE REVERSE SLED MOVE 0 0 1 0TRACKING MODE2 Table 5-9. TRK Servo The TRK JUMP (track jump) level can be set with 6 bits (D13 to D8) of $36. In addition, when the TRK servo is on and D17 of $1 is set to 1, the TRK servo filter switches to gain-up mode. The filter also switches to gain-up mode when the LOCK signal goes low or when vibration is detected with the anti-shock circuit (described hereafter) enabled. The CXD2585Q has 2 types of gain-up filter structures in TRK gain-up mode which can be selected by setting D16 of $1. (See Table 5-17.) SLD Servo The SLD MOV (sled move) output, composed of a basic value from 6 bits (D13 to D8) of $37, is determined by multiplying this value by 1·, 2·, 3·, or 4· magnification set using D17 and D16 when D18 = D19 = 0 is set with $3. (See Table 5-10.) SLD MOV must be performed continuously for 50µs or more. In addition, if the LOCK input signal goes low when the SLD servo is on, the SLD servo turns off. Note)When the LOCK signal is low, the TRK servo switches to gain-up mode and the SLD servo is turned off. These operations are disabled by setting D6 (LKSW) of $38 to 1. Register name Command D23 to D20 D19 to D16 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 SLED KICK LEVEL (basic value · –1) SLED KICK LEVEL (basic value · –2) SLED KICK LEVEL (basic value · –3) SLED KICK LEVEL (basic value · –4) 0 0 1 1SELECT3 Table 5-10. *: Don't care 0 0 * * 0 1 * * 1 0 * * 1 1 * * * * 0 0 * * 0 1 * * 1 0 * * 1 1

– 92 – CXD2585Q § 5-9. MIRR and DFCT Signal Generation The RF signal obtained from the RFDC pin is sampled at approximately 1.4MHz (when MCK = 128Fs) and loaded. The MIRR and DFCT signals are generated from this RF signal. MIRR Signal Generation The loaded RF signal is applied to peak hold and bottom hold circuits. An envelope is generated from the waveforms generated in these circuits, and the MIRR comparator level is generated from the average of this envelope waveform. The MIRR signal is generated by comparing the waveform generated by subtracting the bottom hold value from the peak hold value with this MIRR comparator level. (See Fig. 5-11.) The bottom hold speed and mirror sensitivity can be selected from 4 values using D7 and D6, and D5 and D4, respectively, of $3C. Fig. 5-11. DFCT Signal Generation The loaded RF signal is input to two peak hold circuits with different time constants, and the DFCT signal is generated by comparing the difference between these two peak hold waveforms with the DFCT comparator level. (See Fig. 5-12.) The DFCT comparator level can be selected from four values using D13 and D12 of $3B. Fig. 5-12. R F Peak H old Bottom H old Peak H old – Bottom H old M IR R M IR R C om p (M irror com parator level) H L R F Peak H old1 Peak H old2 Peak H old2 – Peak H old1 D FC T (D efect com parator level) H L SD F

– 93 – CXD2585Q § 5-10. DFCT Countermeasure Circuit The DFCT countermeasure circuit maintains the directionality of the servo so that the servo does not become easily dislocated due to scratches or defects on discs. Specifically, these operations are achieved by detecting scratches and defects with the DFCT signal generation circuit, and when DFCT goes high, applying the low frequency component of the error signal before DFCT went high to the FCS and TRK servo filter inputs. (See Fig. 5-13.) In addition, these operations are activated by the default. They can be disabled by setting D7 (DFSW) of $38 to 1. Fig. 5-13. § 5-11. Anti-Shock Circuit When vibrations occur in the CD player, this circuit forces the TRK filter to switch to gain-up mode so that the servo does not become easily dislocated. This circuit is for systems which require vibration countermeasures. Concretely, vibrations are detected using an internal anti-shock filter and comparator circuit, and the gain is increased. (See Fig. 5-14.) The comparator level is fixed to 1/16 of the maximum comparator input amplitude. However, the comparator level is practically variable by adjusting the value of the anti-shock filter output coefficient K35. This function can be turned on and off by D19 of $1 when the brake circuit (described hereafter) is off. (See Table 5-17.) This circuit can also support an external vibration detection circuit, and can set the TRK servo filter to gain-up mode by inputting high level to the ATSK pin. When the upper 4 bits of the command register are 1 (Hex), vibration detection can be monitored from the SENS pin. It also can be monitored from the ATSK pin by setting the ASOT command of $3F to 0. Fig. 5-14. Input register H old register EN H old Filter Servo Filter Error signal D FC T TE Anti Shock Filter TR K G ain U p Filter TR K G ain N orm al Filter TR K PW M G en ATSK SEN SC om parator

– 94 – CXD2585Q § 5-12. Brake Circuit Immediately after a long distance track jump it tends to be hard for the actuator to settle and for the servo to turn on. The brake circuit prevents these phenomenon. In principle, the brake circuit uses the tracking drive as a brake by cutting the unnecessary portions utilizing the 180° offset in the RF envelope and tracking error phase relationship which occurs when the actuator traverses the track in the radial direction from the inner track to the outer track and vice versa. (See Figs. 5-15 and 5-16.) Concretely, this operation is achieved by masking the tracking drive using the TRKCNCL signal generated by loading the MIRR signal at the edge of the TZC (Tracking Zero Cross) signal. The brake circuit can be turned on and off by D18 of $1. (See Fig. 5-17.) In addition, the low frequency for the tracking drive after masking can be boosted. (SFBK1, 2 of $34B) Fig. 5-15. Fig. 5-16. Register name Command D23 to D20 D19 to D16 1 0 * * 0 * * * * 1 * * * 0 * * * * 0 * * * 1 * * * * 1 * * * 0 ANTI SHOCK ON ANTI SHOCK OFF BRAKE ON BRAKE OFF TRACKING GAIN NORMAL TRACKING GAIN UP TRACKING GAIN UP FILTER SELECT 1 TRACKING GAIN UP FILTER SELECT 2 0 0 0 1TRACKING CONTROL1 Table 5-17. *: Don't care TR K D R V FW D JM P R EV JM P Servo O N R F Trace M IR R TE 0 TZC Edge TR KC N C L 0TR K D R V (SFBK O FF) SEN S TZC out Inner track O uter track 0TR K D R V (SFBK O N ) TR K D R V R EV JM P FW D JM P Servo O N R F Trace M IR R TE 0 TZC Edge TR KC N C L 0TR K D R V (SFBK O FF) SEN S TZC out O uter track Inner track 0TR K D R V (SFBK O N )

– 95 – CXD2585Q § 5-13. COUT Signal The COUT signal is output to count the number of tracks during traverse, etc. It is basically generated by loading the MIRR signal at both edges of the TZC signal. The used TZC signal can be selected from among three different phases according to the COUT signal application.

• HPTZC: For 1-track jumps Fast phase COUT signal generation with a fast phase TZC signal. (The TZC phase is advanced by a cutoff 1kHz digital HPF; when MCK = 128Fs.)
• STZC: For COUT generation when MIRR is externally input and for applications other than COUT generation. This is generated by sampling the TE signal at 700kHz. (when MCK = 128Fs)
• DTZC: For high-speed traverse Reliable COUT signal generation with a delayed phase STZC signal. Since it takes some time to generate the MIRR signal, it is necessary to delay the TZC signal in accordance with the MIRR signal delay during high-speed traverse. The COUT signal output method is switched with D15 and D14 of $3C. When D15 = 1: STZC When D15 = 0 and D14 = 0: HPTZC When D15 = 0 and D14 = 1: DTZC When DTZC is selected, the delay can be selected from two values with D14 of $36. § 5-14. Serial Readout Circuit The following measurement and adjustment results can be read out from the SENS pin by inputting the readout clock to the SCLK pin by $39. (See Fig. 5-18, Table 5-19 and "Description of SENS Signals".) Specified commands $390C: VC AVRG measurement result $3953: FCS AGCNTL coefficient result $3908: FE AVRG measurement result $3963: TRK AGCNTL coefficient result $3904: TE AVRG measurement result $391C: TRVSC adjustment result $391F: RF AVRG measurement result $391D: FBIAS register value Item Symbol Min. Typ. Max. Unit SCLK frequency SCLK pulse width Delay time f SCLK tSPW tDLS 31.3

µs Table 5-19. During readout, the upper 8 bits of the command register must be 39 (Hex). Fig. 5-18.

• ••
• •• tDLS tSPW 1/fSCLK MSB LSB XLAT SCLK Serial Readout Data (SENS pin)

– 96 – CXD2585Q § 5-15. Writing to Coefficient RAM The coefficient RAM can be rewritten by $34. All coefficients have default values in the built-in ROM, and transfer from the ROM to the RAM is completed approximately 40µs (when MCK = 128Fs) after the XRST pin rises. (The coefficient RAM cannot be rewritten during this period.) After that, the characteristics of each built-in filter can be finely adjusted by rewriting the data for each address of the coefficient RAM. The coefficient rewrite command is comprised of 24 bits, with D14 to D8 of $34 as the address (D15 = 0) and D7 to D0 as data. Coefficient rewriting is completed 11.3µs (when MCK = 128Fs) after the command is received. When rewriting multiple coefficients, be sure to wait 11.3µs (when MCK = 128Fs) before sending the next rewrite command. § 5-16. PWM Output FCS, TRK and SLD PWM format outputs are described below. In particular, FCS and TRK use a double oversampling noise shaper. Timing Chart 5-20 and Fig. 5-21 show examples of output waveforms and drive circuits. t MCK = ≈180ns Timing Chart 5-20. Fig. 5-21. Drive Circuit 5.6448MHz 64tM C K 64tM C K 64tM C K AtM C K AtM C KSFD R SR D R SLD 32tM C K 32tM C K 32tM C K 32tM C K32tM C K32tM C K FC S/TR K FFD R / TFD R FR D R / TR D R O utput value +A O utput value –A O utput value 0 tM C KA 2 tM C KA tM C KA 2 tM C KA M C K R R R R VEE D R V VC C R D R FD R

– 97 – CXD2585Q D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 KA6 KA5 KA4 KA3 KA2 KA1 KA0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 PGFS1 PGFS0 PFOK1 PFOK0 0 0 0 0 0 0 0 0 When D15 = 0. KA6 to KA0: Coefficient address KD7 to KD0: Coefficient data § 5-18. Description of Commands and Data Sets $34 $348 (preset: $348 000) PGFS1 High when the frame sync is of the correct timing, low when not the correct timing. High when the frame sync is of the correct timing, low when continuously not the correct timing for 2ms or longer. High when the frame sync is of the correct timing, low when continuously not the correct timing for 4ms or longer. High when the frame sync is the correct timing, low when continuously not the correct timing for 8ms or longer. PGFS0 Processing These commands set the GFS pin hold time. The hold time is inversely proportional to the playback speed. PFOK1 High when the RFDC value is higher than the FOK slice level, low when lower than the FOK slice level. High when the RFDC value is higher than the FOK slice level, low when continuously lower than the FOK slice level for 4.35ms or more. High when the RFDC value is higher than the FOK slice level, low when continuously lower than the FOK slice level for 10.16ms or more. High when the RFDC value is higher than the FOK slice level, low when continuously lower than the FOK slice level for 21.77ms or more. PFOK0 Processing These commands set the FOK hold time. See $3B for the FOK slice level. These are the values when MCK = 128Fs, and the hold time is inversely proportional to the MCK setting. § 5-17. Servo Status Changes Produced by LOCK Signal When the LOCK signal becomes low, the TRK servo switches to the gain-up mode and the SLD servo turns off in order to prevent SLD free-running. Setting D6 (LKSW) of $38 to 1 deactivates this function. In other words, neither the TRK servo nor the SLD servo change even when the LOCK signal becomes low. This enables microcomputer control.

– 98 – CXD2585Q D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 1 SFBK1 SFBK2 0 0 0 0 0 0 0 0 0 0 $34B (preset: $34B 000) The low frequency can be boosted for brake operation. See § 5-12 for brake operation. SFBK1: When 1, brake operation is performed by setting the LowBooster-1 input to 0. This is valid only when TLB1ON = 1. The preset is 0. SFBK2: When 1, brake operation is performed by setting the LowBooster-2 input to 0. This is valid only when TLB2ON = 1. The preset is 0. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 0 THB ON FHB ON TLB1 ON FLB1 ON TLB2 ON 0 HBST1 HBST0 LB1S1 LB1S0 LB2S1 LB2S0 $34C (preset: $34C 000) These commands turn on the boost function. (See § 5-20. Filter Composition.) There are five boosters (three for the TRK filter and two for the FCS filter) which can be turned on and off independently. THBON: When 1, the high frequency is boosted for the TRK filter. Preset when 0. FHBON: When 1, the high frequency is boosted for the FCS filter. Preset when 0. TLB1ON: When 1, the low frequency is boosted for the TRK filter. Preset when 0. FLB1ON: When 1, the low frequency is boosted for the FCS filter. Preset when 0. TLB2ON: When 1, the low frequency is boosted for the TRK filter. Preset when 0. The difference between TLB1ON and TLB2ON is the position where the low frequency is boosted. For TLB1ON, the low frequency is boosted before the TRK jump, and for TLB2ON, after the TRK jump. The following commands set the boosters. (See § 5-20. Filter Composition.) HBST1, HBST0: TRK and FCS HighBooster setting. HighBooster has the configuration shown in Fig. 5-24a, and can select three different combinations of coefficients BK1, BK2 and BK3. (See Table 5-25a.) An example of characteristics is shown in Fig. 5-26a. These characteristics are the same for both the TRK and FCS filters. The sampling frequency is 88.2kHz (when MCK = 128Fs). LB1S1, LB1S0: TRK and FCS LowBooster-1 setting. LowBooster-1 has the configuration shown in Fig. 5-24b, and can select three different combinations of coefficients BK4, BK5 and BK6. (See Table 5-25b.) An example of characteristics is shown in Fig. 5-26b. These characteristics are the same for both the TRK and FCS filters. The sampling frequency is 88.2kHz (when MCK = 128Fs). LB2S1, LB2S0: TRK LowBooster-2 setting. LowBooster-2 has the configuration shown in Fig. 5-24c, and can select three different combinations of coefficients BK7, BK8 and BK9. (See Table 5-25c.) An example of characteristics is shown in Fig. 5-26c. This booster is used exclusively for the TRK filter. The sampling frequency is 88.2kHz (when MCK = 128Fs). Note) Fs = 44.1kHz

– 99 – CXD2585Q HBST1 HBST0 HighBooster setting –120/128 –124/128 –126/128 BK1 BK2 BK3 Table 5-25a.Fig. 5-24a. Fig. 5-24b. Fig. 5-24c. LB1S1 LB1S0 LowBooster-1 setting –255/256 –511/512 –1023/1024 BK4 BK5 BK6 Table 5-25b. LB2S1 LB2S0 LowBooster-2 setting –255/256 –511/512 –1023/1024 BK7 BK8 BK9 Table 5-25c. BK2 Z–1 Z–1 BK1 BK3 BK5 Z–1 Z–1 BK4 BK6 BK8 Z–1 Z–1 BK7 BK9

– 100 – CXD2585Q –15 Gain [dB] –12 100101 Frequency [H z] 1k 10k 23 1 –90 +90 Phase [degree] –72 –36 +36 +72 100101 Frequency [H z] 1k 10k 23 1 Fig. 5-26a. Servo HighBooster Characteristics [FCS, TRK] (MCK = 128Fs) HBST1 = 0 HBST1 = 1, HBST0 = 0 HBST1 = 1, HBST0 = 11 2 3

– 101 – CXD2585Q –15 Gain [dB] –12 100101 Frequency [H z] 1k 10k –90 +90 Phase [degree] –72 –36 +36 +72 100101 Frequency [H z] 1k 10k 23 1 Fig. 5-26b. Servo LowBooster1 Characteristics [FCS, TRK] (MCK = 128Fs) LB1S1 = 0 LB1S1 = 1, LB1S0 = 0 LB1S1 = 1, LB1S0 = 11 2 3

– 102 – CXD2585Q –15 Gain [dB] –12 100101 Frequency [H z] 1k 10k –90 +90 Phase [degree] –72 –36 +36 +72 100101 Frequency [H z] 1k 10k 2 13 23 1 Fig. 5-26c. Servo LowBooster2 Characteristics [FCS, TRK] (MCK = 128Fs) LB2S1 = 0 LB2S1 = 1, LB2S0 = 0 LB2S1 = 1, LB2S0 = 11 2 3

– 103 – CXD2585Q D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 0 1 FB9 FB8 FB7 FB6 FB5 FB4 FB3 FB2 FB1 — When D15 = D14 = D13 = D12 = 1 ($34F) D11 = 0, D10 = 1 FBIAS register write FB9 to FB1: Data; two's complement data, FB9 = MSB. For FE input conversion, FB9 to FB1 = 011111111 corresponds to 255/256 · V DD /5 and FB9 to FB1 = 100000000 to –256/256 · VDD /5 respectively. (VDD : supply voltage) 1 1 1 1 1 0 FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1 — When D15 = D14 = D13 = D12 = D11 = 1 ($34F) D10 = 0 FBIAS LIMIT register write FBL9 to FBL1: Data;data compared with FB9 to FB1, FBL9 = MSB. When using the FBIAS register in counter mode, counter operation stops when the value of FB9 to FB1 matches with FBL9 to FBL1. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 0 0 TV9 TV8 TV7 TV6 TV5 TV4 TV3 TV2 TV1 TV0 When D15 = D14 = D13 = D12 = 1 ($34F) D11 = 0, D10 = 0 TRVSC register write TV9 to TV0: Data;two's complement data, TV9 = MSB. For TE input conversion, TV9 to TV0 = 0011111111 corresponds to 255/256 · VDD /5 and TV9 to TV0 = 1100000000 to –256/256 · VDD /5 respectively. (VDD : supply voltage) Note) • When the TRVSC register is read out, the data length is 9 bits. At this time, data corresponding to each bit TV8 to TV0 during external write are read out.

• When reading out internally measured values and then writing these values externally, set TV9 the same as TV8. $34F

– 104 – CXD2585Q $35 (preset: $35 58 2D) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FT1 FT0 FS5 FS4 FS3 FS2 FS1 FS0 FTZ FG6 FG5 FG4 FG3 FG2 FG1 FG0 FT1, FT0, FTZ:Focus search-up speed Default value: 010 (0.673 · VDD V/s) Focus drive output conversion FT1 1.35 · V DD 0.673 · VDD 0.449 · VDD 0.336 · VDD 1.79 · VDD 1.08 · VDD 0.897 · VDD 0.769 · VDD FT0 FTZ Focus search speed [V/s] FS5 to FS0: Focus search limit voltage Default value:011000 (±24/64 · VDD , VDD : PWM driver supply voltage) Focus drive output conversion FG6 to FG0: AGF convergence gain setting value Default value: 0101101 $36 (preset: $36 0E 2E) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TDZC DTZC TJ5 TJ4 TJ3 TJ2 TJ1 TJ0 SFJP TG6 TG5 TG4 TG3 TG2 TG1 TG0 TDZC: Selects the TZC signal for generating the TRKCNCL signal during brake circuit operation. TDZC = 0: The edge of the HPTZC or STZC signal, whichever has the faster phase, is used. TDZC = 1: The edge of the HPTZC or STZC signal or the tracking drive signal zero-cross, whichever has the fastest phase, is used. (See § 5-12.) DTZC: DTZC delay (8.5/4.25µs, when MCK = 128Fs) Default value: 0 (4.25µs) TJ5 to TJ0: Track jump voltage Default value: 001110 (≈ ±14/64 · V DD , VDD : PWM driver supply voltage) Tracking drive output conversion SFJP: Surf jump mode on/off The tracking PWM output is generated by adding the tracking filter output and TJReg (TJ5 to 0), by setting D7 to 1 (on) TG6 to TG0: AGT convergence gain setting value Default value: 0101110 *: preset, VDD : PWM driver supply voltage

– 105 – CXD2585Q $37 (preset: $37 50 BA) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT FZSH, FZSL: FZC (Focus Zero Cross) slice level Default value: 01 (1/8 · VDD · 0.4, VDD : supply voltage); FE input conversion FZSH 1/4 · V DD · 0.4 1/8 · VDD · 0.4 1/16 · VDD · 0.4 1/32 · VDD · 0.4 FZSL Slice level SM5 to SM0: Sled move voltage Default value: 010000 (≈ –16/64 · VDD , VDD : PWM driver supply voltage) Sled drive output conversion AGS: AGCNTL self-stop on/off Default value: 1 (on) AGJ: AGCNTL convergence completion judgment time during low sensitivity adjustment (31/63ms, when MCK = 128Fs) Default value: 0 (63ms) AGGF: Focus AGCNTL internally generated sine wave amplitude (small/large) Default value: 1 (large) AGGT: Tracking AGCNTL internally generated sine wave amplitude (small/large) Default value: 1 (large) AGGF 0 (small) 1 (large)* 1/32 · VDD · 0.4 1/16 · VDD · 0.4 1/16 · VDD · 0.4 1/8 · VDD · 0.4AGGT 0 (small) 1 (large)* FE/TE input conversion AGV1: AGCNTL convergence sensitivity during high sensitivity adjustment; high/low Default value: 1 (high) AGV2: AGCNTL convergence sensitivity during low sensitivity adjustment; high/low Default value: 0 (low) AGHS: AGCNTL high sensitivity adjustment on/off Default value: 1 (on) AGHT: AGCNTL high sensitivity adjustment time (128/256ms, when MCK = 128Fs) Default value: 0 (256ms) *: preset *: preset

– 106 – CXD2585Q $38 (preset: $38 00 00) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0 *VCLM: VC level measurement (on/off) VCLC: VC level compensation for FCS In register (on/off) *FLM: Focus zero level measurement (on/off) FLC0: Focus zero level compensation for FZC register (on/off) *RFLM: RF zero level measurement (on/off) RFLC: RF zero level compensation (on/off) AGF: Focus auto gain adjustment (on/off) AGT: Tracking auto gain adjustment (on/off) DFSW: Defect disable switch (on/off) Setting this switch to 1 (on) disables the defect countermeasure circuit. LKSW: Lock switch (on/off) Setting this switch to 1 (on) disables the sled free-running prevention circuit. TBLM: Traverse center measurement (on/off) *TCLM: Tracking zero level measurement (on/off) FLC1: Focus zero level compensation for FCS In register (on/off) TLC2: Traverse center compensation (on/off) TLC1: Tracking zero level compensation (on/off) TLC0: VC level compensation for TRK/SLD In register (on/off) Note)Commands marked with * are accepted every 2.9ms. (when MCK = 128Fs) All commands are on when 1.

– 107 – CXD2585Q SD6 Data RAM data for address = SD4 to SD0 Coefficient RAM data for address = SD5 to SD0 SD4 SD3 to SD0 1 1 1 1 1 1 1 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 1 1 * * 1 0 * * 0 1 * * 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 RF AVRG register RFDC input signal FBIAS register TRVSC register RFDC envelope (bottom) RFDC envelope (peak) RFDC envelope (peak) – (bottom) VC AVRG register FE AVRG register TE AVRG register FE input signal TE input signal SE input signal VC input signal 8 bits 8 bits 9 bits 9 bits 8 bits 8 bits 8 bits 9 bits 9 bits 9 bits 8 bits 8 bits 8 bits 8 bits $399F $399E $399D $399C $3993 $3992 $3991 $398C $3988 $3984 $3983 $3982 $3981 $3980 8 bits 16 bits SD5 Readout data Readout data length *: Don't care Note) Coefficients K40 to K4F cannot be read out. See the Description for Data Readout concerning readout methods for the above data. D15 D14 D13 D12 D11 D10 D9 D8 DAC SD6 SD5 SD4 SD3 SD2 SD1 SD0 DAC: Serial data readout DAC mode (on/off) SD6 to SD0: Serial readout data select $39

– 108 – CXD2585Q $3A (preset: $3A 00 00) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 FBON FBSS FBUP FBV1 FBV0 0 TJD0 FPS1 FPS0 TPS1 TPS0 0 SJHD INBK MTI0

FBON: FBIAS (focus bias) register addition (on/off) The FBIAS register value is added to the signal loaded into the FCS In register by setting FBON = 1 (on). FBSS: FBIAS (focus bias) register/counter switching FBSS = 0: register, FBSS = 1: counter. FBUP: FBIAS (focus bias) counter up/down operation switching This performs counter up/down control when FBSS = 1. FBUP = 0: down counter, FBUP = 1: up counter. FBV1, FBV0: FBIAS (focus bias) counter voltage switching The number of FCS BIAS count-up/-down steps per cycle is decided by these bits. TJD0: This sets the tracking servo filter data RAM to 0 when switched from track jump to servo on only when SFJP = 1 (during surf jump operation). FPS1, FPS0: Gain setting when transferring data from the focus filter to the PWM block. TPS1, TPS0: Gain setting when transferring data from the tracking filter to the PWM block. These are effective for increasing the overall gain in order to widen the servo band. Operation when FPS1, FPS0 (TPS1, TPS0) = 00 is the same as usual (7-bit shift). However, 6dB, 12dB and 18dB can be selected independently for focus and tracking by setting the relative gain to 0dB when FPS1, FPS0 (TPS1, TPS0) = 00. SJHD: This holds the tracking filter output at the value when surf jump starts during surf jump. INBK: When INBK = 0 (off), the brake circuit masks the tracking drive signal with TRKCNCL which is generated by fetching the MIRR signal at the TZC edge. When INBK = 1 (on), the tracking filter input is masked instead of the drive output. MTI0: The tracking filter input is masked when the MIRR signal is high by setting MTI0 = 1 (on). The counter changes once for each sampling cycle of the focus servo filter. When MCK is 128Fs, the sampling frequency is 88.2kHz. When converted to FE input, 1 step is approximately 1/2 9 · VDD · 0.4, VDD = supply voltage. FBV1 FBV0 Number of steps per cycle FPS1 FPS0 0dB +6dB +12dB +18dB Relative gain TPS1 TPS0 0dB +6dB +12dB +18dB Relative gain *: preset *: preset

– 109 – CXD2585Q $3B (preset: $3B E0 50) SFOX, SFO2, SFO1: FOK slice level Default value: 011 (28/256 · VDD · 0.57, VDD = supply voltage) RFDC input conversion SFOX 16/256 · V DD · 0.57 20/256 · VDD · 0.57 24/256 · VDD · 0.57 28/256 · VDD · 0.57 32/256 · VDD · 0.57 40/256 · VDD · 0.57 48/256 · VDD · 0.57 56/256 · VDD · 0.57 SFO2 SFO1 Slice level D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT 0 0 0 *: preset SDF2, SDF1: DFCT slice level Default value: 10 (0.0313 · VDD · 1.14V) RFDC input conversion SDF2 0.0156 · V DD · 1.14 0.0234 · VDD · 1.14 0.0313 · VDD · 1.14 0.0391 · VDD · 1.14 SDF1 Slice level MAX2, MAX1: DFCT maximum time (MCK = 128Fs) Default value: 00 (no timer limit) MAX2 No timer limit 2.00ms 2.36 2.72 MAX1 DFCT maximum time BTF: Bottom hold double-speed count-up mode for MIRR signal generation On/off (default: off) On when set to 1. *: preset, V DD : supply voltage *: preset

– 110 – CXD2585Q D2V2, D2V1: Peak hold 2 for DFCT signal generation Count-down speed setting Default value:01 (0.086 · V DD · 1.14V/ms, 44.1kHz) [V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the operating frequency of the internal counter. D1V2, D1V1: Peak hold 1 for DFCT signal generation Count-down speed setting Default value:01 (0.688

• VDD · 1.14V/ms, 352.8kHz) [V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the operating frequency of the internal counter. RINT: This initializes the initial-state registers of the circuits which generate MIRR, DFCT and FOK. D2V2 22.05 44.1 88.2 176.4 0.0431 · V DD · 1.14 0.0861 · VDD · 1.14 0.172 · VDD · 1.14 0.344 · VDD · 1.14 D2V1 Count-down speed [V/ms] [kHz] *: preset, VDD : supply voltage *: preset, VDD : supply voltage D1V2 176.4 352.8 705.6 1411.2 0.344 · V DD · 1.14 0.688 · VDD · 1.14 1.38 · VDD · 1.14 2.75 · VDD · 1.14 D2V1 Count-down speed [V/ms] [kHz]

– 111 – CXD2585Q $3C (preset: $3C 00 80) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 COSS COTS CETZ CETF COT2 COT1 MOT2 0 BTS1 BTS0 MRC1 MRC0 0 0 0 0 COSS, COTS: This selects the TZC signal used when generating the COUT signal. Preset = HPTZC. STZC is the TZC generated by sampling the TE signal at 700kHz. (when MCK = 128Fs) DTZC is the delayed phase STZC. (The delay time can be selected by D14 of $36.) HPTZC is the fast phase TZC passed through a HPF with a cut-off frequency of 1kHz. See § 5-13. CETZ: The input from the TE pin normally enters the TRK filter and is used to generate the TZC signal. However, the input from the CE pin can also be used. This function is for the center error servo. When 0, the TZC signal is generated by using the signal input to the TE pin. When 1, the TZC signal is generated by using the signal input to the CE pin. CETF: When 0, the signal input to the TE pin is input to the TRK servo filter. When 1, the signal input to the CE pin is input to the TRK servo filter. These commands output the TZC signal. COT2, COT1: This outputs the TZC signal from the COUT pin. COSS STZC HPTZC DTZC COTS TZC *: preset, —: don't care BTS1 BTS0 Number of count-up steps per cycle MRC1 5.669* 11.338 22.675 45.351 MRC0 Setting time [µs] *: preset (when MCK = 128Fs) MOT2: The STZC signal is output from the MIRR pin by setting MOT2 to 1. These commands set the MIRR signal generation circuit. BTS1, BTS0: This sets the count-up speed for the bottom hold value of the MIRR generation circuit. The time per step is approximately 708ns (when MCK = 128Fs). The preset value is BTS1 = 1, BTS0 = 0 like the CXD2586R. This is valid only when BTF of $3B is 0. MRC1, MRC0: This sets the minimum pulse width for masking the MIRR signal of the MIRR generation circuit. As noted in § 5-9, the MIRR signal is generated by comparing the waveform obtained by subtracting the bottom hold value from the peak hold value with the MIRR comparator level. Strictly speaking, however, for MIRR to become high, these levels must be compared continuously for a certain time. This sets that time. The preset value is MRC1 = 0, MRC0 = 0 like the CXD2586R. COT2 STZC HPTZC COUT COT1 COUT pin output *: preset, —: don't care

– 112 – CXD2585Q $3D (preset: $3D 00 00) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SFID SFSK THID THSK 0 TLD2 TLD1 TLD0 0 0 0 0 0 0 0 0 SFID: SLED servo filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK filter second-stage output. When the low frequency component of the tracking error signal obtained from the RF amplifier is attenuated, the low frequency can be amplified and input to the SLD servo filter. SFSK: Only during TRK servo gain up2 operation, coefficient K30 is used instead of K00. Normally, the DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain up2, creating a difference in the DC level at M0D. In this case, the DC level of the signal transmitted to M00 can be kept uniform by adjusting the K30 value even during the above switching. THID: TRK hold filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK filter second-stage output. When signals other than the tracking error signal from the RF amplifier are input to the SE input pin, the signal transmitted from the TE pin can be obtained as the TRK hold filter input. THSK: Only during TRK servo gain up2 operation, coefficient K46 is used instead of K40. Normally, the DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain up2, creating a difference in the DC level at M0D. In this case, the DC level of the signal transmitted to M18 can be kept uniform by adjusting the K46 value even during the above switching. * See § 5-21. Filter Composition regarding the SFID, SFSK, THID and THSK commands. TLD0 to 2: This turns on and off SLD filter correction independently of the TRK filter. See $38 (TLC0 to 2) and Fig. 5-3. TLC0 OFF ON OFF OFF ON ON TLD0 VC level correction TRK filter SLD filter *: preset, —: don't care TLC1 OFF ON OFF OFF ON ON TLD1 Tracking zero level correction TRK filter SLD filter TLC2 OFF ON OFF OFF ON ON TLD2 Traverse center correction TRK filter SLD filter

– 113 – CXD2585Q

• Input coefficient sign inversion when SFID = 1 and THID = 1 The preset coefficients for the TRK filter are negative for input and positive for output. With this, the CXD2585Q outputs the servo drives which have the reversed phase to the error inputs.. When SFID = 1, the TRK filter negative input coefficient is applied to the SLD filter, so invert the SLD input coefficient (K00) sign. (For example, inverting the sign for coefficient K00: E0Hex results in 60Hex.) For the same reason, when THID = 1, invert the TRK hold input coefficient (K40) sign. * for TRK servo gain normal See § 5-21. Filter Composition. K19 TR K Filter K22 N egative input coefficient Positive output coefficient TE K00 SLD Filter K05 N egative input coefficient Positive output coefficient SE K40 TR K H old Filter K45 Positive input coefficient Positive output coefficient TR K H old K19 TR K Filter K22 N egative input coefficient Positive output coefficient TE K00 SLD Filter K05 Positive input coefficient Positive output coefficient SE K40 TR K H old Filter K45 N egative input coefficient Positive output coefficient TR K H old M O D

– 114 – CXD2585Q $3E (preset: $3E 00 00) F1NM, F1DM: Quasi double accuracy setting for FCS servo filter first-stage On when 1; default when 0. F1NM: Gain normal F1DM: Gain down T1NM, T1UM: Quasi double accuracy setting for TRK servo filter first-stage On when 1; default when 0. T1NM: Gain normal T1UM: Gain up F3NM, F3DM: Quasi double accuracy setting for FCS servo filter third-stage On when 1; default when 0. Generally, the advance amount of the phase becomes large by partially setting the FCS servo third-stage filter which is used as the phase compensation filter to double accuracy. F3NM: Gain normal F3DM: Gain down T3NM, T3UM: Quasi double accuracy setting for TRK servo filter third-stage On when 1; default when 0. Generally, the advance amount of the phase becomes large by partially setting the TRK servo third-stage filter which is used as the phase compensation filter to double accuracy. T3NM: Gain normal T3UM: Gain up Note)Filter first- and third-stage quasi double accuracy settings can be set individually. See § 5-20 Filter Composition at the end of this specification concerning quasi double accuracy. DFIS: FCS hold filter input extraction node selection 0: M05 (Data RAM address 05); default 1: M04 (Data RAM address 04) TLCD: This command masks the TLC2 command set by D2 of $38 only when FOK is low. On when 1; default when 0 LKIN: When 0, the internally generated LOCK signal is output to the LOCK pin. (default) When 1, the LOCK signal can be input from an external source to the LOCK pin. COIN: When 0, the internally generated COUT signal is output to the COUT pin. (default) When 1, the COUT signal can be input from an external source to the COUT pin. The MIRR, DFCT and FOK signals can also be input from an external source. MDFI: When 0, the MIRR, DFCT and FOK signals are generated internally. (default) When 1, the MIRR, DFCT and FOK signals can be input from an external source through the MIRR, DFCT and FOK pins. MIRI: When 0, the MIRR signal is generated internally. (default) When 1, the MIRR signal can be input from an external source through the MIRR pin. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD 0 LKIN COIN MDFI MIRI XT1D XT1D: When XT1D = 1, the input to the servo master clock can be used without dividing its frequency. This command takes precedence over the XTSL pin, XT2D and XT4D. See the description of $3F for XT2D and XT4D. MDFI MIRR, DFCT and FOK are all generated internally. MIRR only is input from an external source. MIRR, DFCT and FOK are all input from an external source. MIRI *: preset, —: don't care

– 115 – CXD2585Q $3F (preset: $3F 00 00) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 AGG4 XT4D XT2D 0 DRR2 DRR1 DRR0 0 ASFG FTQ LPAS 0 0 AGHF 0

XT4D, XT2D: MCK (digital servo master clock) frequency division setting This command forcibly sets the frequency division ratio to 1/4, 1/2 or 1/1 when MCK is generated. See the description of $3E for XT1D. Also, see the decription of §5-2. Digital Servo Block Master Clock (MCK). AGG4: This varies the amplitude of the internally generated sine wave using the AGGF and AGGT commands during AGC. When AGG4 = 0, the default is used. When AGG4 = 1, the setting is as shown in the table below. AGG4 AGGF AGGT FE input conversion 1/36 · V DD · 0.4 1/16 · VDD · 0.4 TE input conversion 1/16 · V DD · 0.4 1/8 · VDD · 0.4* DRR2 to DRR0 : Partially clears the Data RAM values (0 write). The following values are cleared when 1 (on) respectively; default = 0 DRR2: M08, M09, M0A DRR1: M00, M01, M02 DRR0: M00, M01, M02 only when LOCK = low Note)Set DRR1 and DRR0 on for 50µs or more. ASFG: When vibration detection is performed during anti-shock circuit operation, the FCS servo filter is forcibly set to gain normal status. On when 1; default when 0 LPAS: Built-in analog buffer low-current consumption mode This mode reduces the total analog buffer current consumption for the VC, TE, SE and FE input analog buffers by using a single operational amplifier. On when 1; default when 0 Note) When using this mode, first check whether each error signal is properly A/D converted using the data readout and the like. AGHF: This halves the frequency of the internally generated sine wave during AGC. FTQ: The slope of the output during focus search is 1/4 of the conventional output slope. On when 1; default when 0 . ASOT: The anti-shock signal, which is internally detected, is output from the ATSK pin. Output when set to 1; default = 0 Vibration detection when a high signal is output for the anti-shock signal output. See $37 for AGGF and AGGT. The presets are AGG4 = 0, AGGF = 1 and AGGT = 1. *: preset, —: don't care *: preset, —: don't care XT1D XT2D XT4D According to XTSL Frequency division ratio Sine wave amplitude 1/64 · VDD · 0.4 1/32 · VDD · 0.4 1/16 · VDD · 0.4 1/8 · VDD · 0.4

– 116 – CXD2585Q Description of Data Readout SO C K (5.6448M H z) XO LT (88.2kH z) SO U T M SB LSB··· M SB LSB··· 16-bit register for serial/parallel conversion SO U T SO C K XO LT C LK C LK M SB LSB To the 7-segm ent LED To the 7-segm ent LED D ata is connected to the 7-segm ent LED by 4bits at a tim e. This enables H ex display using four 7-segm ent LED s. M SB LSB 16-bit register for latch SO U T SO C K XO LT Serial data input C lock input Latch enable input Analog output D /A To an oscilloscope, etc. O ffset adjustm ent, gain adjustm ent W aveform s can be m onitored w ith an oscilloscope using a serial input-type D /A converter as show n above.

– 117 – CXD2585Q § 5-19. List of Servo Filter Coefficients <Coefficient Preset Value Table (1)> ADDRESS K00 K01 K02 K03 K04 K05 K06 K07 K08 K09 K0A K0B K0C K0D K0E K0F SLED INPUT GAIN SLED LOW BOOST FILTER A-H SLED LOW BOOST FILTER A-L SLED LOW BOOST FILTER B-H SLED LOW BOOST FILTER B-L SLED OUTPUT GAIN FOCUS INPUT GAIN SLED AUTO GAIN FOCUS HIGH CUT FILTER A FOCUS HIGH CUT FILTER B FOCUS LOW BOOST FILTER A-H FOCUS LOW BOOST FILTER A-L FOCUS LOW BOOST FILTER B-H FOCUS LOW BOOST FILTER B-L FOCUS PHASE COMPENSATE FILTER A FOCUS DEFECT HOLD GAIN K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K1A K1B K1C K1D K1E K1F K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K2A K2B K2C K2D K2E K2F FOCUS PHASE COMPENSATE FILTER B FOCUS OUTPUT GAIN ANTI SHOCK INPUT GAIN FOCUS AUTO GAIN HPTZC / Auto Gain HIGH PASS FILTER A HPTZC / Auto Gain HIGH PASS FILTER B ANTI SHOCK HIGH PASS FILTER A HPTZC / Auto Gain LOW PASS FILTER B Fix* TRACKING INPUT GAIN TRACKING HIGH CUT FILTER A TRACKING HIGH CUT FILTER B TRACKING LOW BOOST FILTER A-H TRACKING LOW BOOST FILTER A-L TRACKING LOW BOOST FILTER B-H TRACKING LOW BOOST FILTER B-L TRACKING PHASE COMPENSATE FILTER A TRACKING PHASE COMPENSATE FILTER B TRACKING OUTPUT GAIN TRACKING AUTO GAIN FOCUS GAIN DOWN HIGH CUT FILTER A FOCUS GAIN DOWN HIGH CUT FILTER B FOCUS GAIN DOWN LOW BOOST FILTER A-H FOCUS GAIN DOWN LOW BOOST FILTER A-L FOCUS GAIN DOWN LOW BOOST FILTER B-H FOCUS GAIN DOWN LOW BOOST FILTER B-L FOCUS GAIN DOWN PHASE COMPENSATE FILTER A FOCUS GAIN DOWN DEFECT HOLD GAIN FOCUS GAIN DOWN PHASE COMPENSATE FILTER B FOCUS GAIN DOWN OUTPUT GAIN NOT USED NOT USED DATA CONTENTS * Fix indicates that normal preset values should be used.

– 118 – CXD2585Q <Coefficient Preset Value Table (2)> ADDRESS K30 K31 K32 K33 K34 K35 K36 K37 K38 K39 K3A K3B K3C K3D K3E K3F SLED INPUT GAIN (Only when TRK Gain Up2 is accessed with SFSK = 1.) ANTI SHOCK LOW PASS FILTER B NOT USED ANTI SHOCK HIGH PASS FILTER B-H ANTI SHOCK HIGH PASS FILTER B-L ANTI SHOCK FILTER COMPARATE GAIN TRACKING GAIN UP2 HIGH CUT FILTER A TRACKING GAIN UP2 HIGH CUT FILTER B TRACKING GAIN UP2 LOW BOOST FILTER A-H TRACKING GAIN UP2 LOW BOOST FILTER A-L TRACKING GAIN UP2 LOW BOOST FILTER B-H TRACKING GAIN UP2 LOW BOOST FILTER B-L TRACKING GAIN UP PHASE COMPENSATE FILTER A TRACKING GAIN UP PHASE COMPENSATE FILTER B TRACKING GAIN UP OUTPUT GAIN NOT USED K40 K41 K42 K43 K44 K45 K46 K47 K48 K49 K4A K4B K4C K4D K4E K4F TRACKING HOLD FILTER INPUT GAIN TRACKING HOLD FILTER A-H TRACKING HOLD FILTER A-L TRACKING HOLD FILTER B-H TRACKING HOLD FILTER B-L TRACKING HOLD FILTER OUTPUT GAIN TRACKING HOLD FILTER INPUT GAIN (Only when TRK Gain Up2 is accessed with THSK = 1.) NOT USED FOCUS HOLD FILTER INPUT GAIN FOCUS HOLD FILTER A-H FOCUS HOLD FILTER A-L FOCUS HOLD FILTER B-H FOCUS HOLD FILTER B-L FOCUS HOLD FILTER OUTPUT GAIN NOT USED NOT USED DATA CONTENTS

– 119 – CXD2585Q § 5-20. Filter Composition The internal filter composition is shown below. K and M indicate coefficient RAM and Data RAM address values respectively. K0D K0C K0E K10 Z–1 K0B Z–1 K09 K0A M 04M 03 2–7 M 06 Z–1 K11 K13 FC S AU TO G ain M 072–1 K06 AG FO N K06 D FC TFC S H old R eg2 FC S In R eg Sin R O M K08 Z–1 M 05 K0F FC S H old R eg 1 K29 K28 K2A K2C Z–1 K27 Z–1 K25 K26 M 04M 03 2–7 2–7 M 06 Z–1 K2D K13 FSC AU TO G ain M 072–1 K06 D FC TFC S H old R eg2 FC S In R eg K24 Z–1 M 05 K28 FC S H old R eg 1 2–7 FC S Servo G ain D ow n fs = 88.2kH z N ote) Set the M SB bit of the K0B and K0D coefficients to 0. N ote) Set the M SB bit of the K27 and K29 coefficients to 0. FC S Servo G ain N orm al fs = 88.2kH z PW M BK2 Z–1 Z–1 FC S SR C H BK1 BK5 Z–1 Z–1 BK4 FPS1, 0 BK3 BK6

– 120 – CXD2585Q K1F K1E K20 K21 Z–1 K1D Z–1 K1B K1C M 0CM 0B 2–7 M 0E Z–1 K22 K23 TR K AU TO G ain M 0F2–1 K19 AG TO N K19 D FC TTR K H old R eg TR K In R eg Sin R O M K1A Z–1 M 0D SLD Servo TR K H old K3D Z–1Z–1 K1B K3C M 0CM 0B K3E K23 TR K AU TO G ain M 0F2–1 K19 D FC T TR K H old R eg TR K In R eg K1A Z–1 M 0E 2–7 TR K Servo G ain U p 1 fs = 88.2kH z N ote) Set the M SB bit of the K1D and K1F coefficients to 0. K3B K3A K3C K3D Z–1 K39 Z–1 K37 K38 M 0CM 0B 2–7 M 0E Z–1 K3E K23 TR K AU TO G ain M 0F2–1 K19 D FC T TR K H old R eg TR K In R eg K36 Z–1 M 0D 2–7 TR K Servo G ain U p 2 fs = 88.2kH z N ote) Set the M SB bit of the K39 and K3B coefficients to 0. TR K Servo G ain N orm al fs = 88.2kH z BK2 Z–1 Z–1 TR K JM P BK1 BK5 Z–1 Z–1 BK4 BK8 Z–1 Z–1 BK7 TPS1, 0 BK9 BK3 BK6 PW M

– 121 – CXD2585Q K0D K0C 80H K10 Z–1 K0B Z–1 7FH K0A M 04M 03 2–7 M 06 Z–1 K11 K13 FC S AU TO G ain M 072–1 K06 AG FO N K06 D FC TFC S H old R eg 2 FC S In R eg Sin R O M 81H Z–1 M 05 K0F FC S H old R eg 1 2–1 K06 D FC TFC S H old R eg 2 FC S In R eg 2–7 N ote) Set the M SB bit of the K0B and K0D coefficients during norm al operation, and of the K0B, K09 and K0E coefficients during quasi double accuracy to 0. FC S Servo G ain N orm al fs = 88.2kH z, during quasi double accuracy (Ex.: $3EA XX0) K0E 2–7 K09 2–7 K08 2–7 K29 K28 80H K2C Z–1 K27 Z–1 7FH K26 M 04M 03 2–7 M 06 Z–1 K2D K13 FC S AU TO G ain M 07 81H Z–1 M 05 K2B FC S H old R eg 1 2–7 K2A 2–7 K25 2–7 K24 2–7 FC S Servo G ain N orm al fs = 88.2kH z, during quasi double accuracy (Ex.: $3E5XX0) ∗ ∗ ∗ ∗ ∗ BK2 Z–1 Z–1 FC S SR C H BK1 BK5 Z–1 Z–1 BK4 FPS1, 0 PW M BK3 BK6 ∗ 81H , 7FH and 80H are each H ex display 8-bit fixed values w hen set to quasi double accuracy. N ote) Set the M SB bit of the K27 and K29 coefficients during norm al operation, and of the K24, K25 and K2A coefficients during quasi double accuracy to 0.

– 122 – CXD2585Q 2–1 K19 AG TO N K19 D FC TTR K H old R eg TR K In R eg Sin R O M 2–1 K19 D FC TTR K H old R eg TR K In R eg 2–1 K19 D FC TTR K H old R eg TR K In R eg K1F K1E 80H K21 Z–1 K1D Z–1 7FH K1C M 0CM 0B 2–7 M 0E Z–1 K22 K23 TR K AU TO G ain M 0F 81H Z–1 M 0D 2–7 K20 2–7 K1B 2–7 K1A 2–7 K3D Z–1 K3C Z–1 7FH 80H M 0CM 0B K3E K23 TR K AU TO G ain M 0F 81H Z–1 2–7 K1B 2–7 K1A 2–7 K3B K3A 80H K3D Z–1 K39 Z–1 7FH K38 M 0CM 0B 2–7 M 0E Z–1 K3E K23 TR K AU TO G ain M 0F 81H Z–1 M 0D 2–7 K3C 2–7 K37 2–7 K36 2–7 N ote) Set the M SB bit of the K1D and K1F coefficients during norm al operation, and of the K1A, K1B and K20 coefficients during quasi double accuracy to 0. N ote) Set the M SB bit of the K1A, K1B and K3C coefficients during quasi double accuracy to 0. N ote) Set the M SB bit of the K39 and K3B coefficients during norm al operation, and of the K36, K37 and K3C coefficients during quasi double accuracy to 0. TR K Servo G ain N orm al fs = 88.2kH z, during quasi double accuracy (Ex.: $3EXA X0) TR K Servo G ain up1 fs = 88.2kH z, during quasi double accuracy (Ex.: $3EX5X0) TR K Servo G ain up2 fs = 88.2kH z, during quasi double accuracy (Ex.: $3EX5X0) ∗ ∗ ∗ M 0E ∗ ∗ ∗ ∗ ∗ ∗ BK2 Z–1 Z–1 PW M TR K JM P BK1 BK5 Z–1 Z–1 BK4 TPS1, 0 BK8 Z–1 Z–1 BK7 BK3 BK6 BK9 ∗ 81H , 7FH and 80H are each H ex display 8-bit fixed values w hen set to quasi double accuracy.

– 123 – CXD2585Q SLD Servo fs = 345Hz Note)Set the MSB bit of the K02 and K04 coefficients to 0. HPTZC/Auto Gain fs = 88.2kHz K04 K03 Z–1 K02 Z–1 K01 K00 M 00 2–7 2–7 M 01 K05 K07 TR K AU TO G ain PW M 2–7 SLD M O V M 02 SLD In R eg 2–1 K30 SFSK (only w hen TG U P2 is used.) SFIDM 0D TR K SER VO FILTER Second-stage output K15 K17 Z–1 K14 M 08 M 09 M 0A Z–1 AU TO G ain R eg 2–1 AG TO N AG FO N AG FO N FC S In R eg TR K In R eg Sin R O M Z–1 Slice TZC R egSlice2–1

– 124 – CXD2585Q Anti Shock fs = 88.2kHz Note) Set the MSB bit of the K34 coefficient to 0. The comparator level is 1/16 the maximum amplitude of the comparator input. AVRG fs = 88.2kHz TRK Hold fs = 345Hz Note)Set the MSB bit of the K42 and K44 coefficients to 0. FCS Hold fs = 345Hz Note)Set the MSB bit of the K4A and K4C coefficients to 0. K34 K33 Z–1Z–1 K31 K16 Z–1 M 09M 08 2–7 M 0A K35 C om pK12 Anti Shock R eg 2–1 TR K In R eg M 08 AVR G R eg 2–1 VC , TE, FE, R FD C Z–1 2–7 K44 K43 Z–1 K42 Z–1 K41 K40 M 18 2–7 2–7 M 19 K45 TR K H old R egSLD In R eg 2–1 K46 TH SK (only w hen TG U P2 is used.) TH IDM 0D TR K SER VO FILTER Second-stage output K4C K4B Z–1 K4A Z–1 K49 K48 M 10 2–7 2–7 M 11 K4DFC S H old R eg 1 FC S H old R eg 2

– 125 – CXD2585Q § 5-21. TRACKING and FOCUS Frequency Response When using the preset coefficients with the boost function off. When using the preset coefficients with the boost function off. f – Frequency [H z] 20k1k100102.1 –10 G – Gain [dB] –180° φ – Phase [degree] 180° 90° –90° FO C U S frequency response N O R M AL G AIN D O W N φ G f – Frequency [H z] 20k1k100102.1–10 G – Gain [dB] –180° φ – Phase [degree] 180° 90° –90° TR A C K IN G frequency response φ G N O R M AL G AIN U P

– 126 – CXD2585Q [6] Application Circuit Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 4142434445464748495051525354555657585960 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 201 D VD D 2 ASYE M D 2 D O U T LR C K PC M D BC K EM PH XTSL D Vss2 XTAI XTAO SO U T SO C K XO LT SQ SO SQ C K SC SY SBSO EXC K SE FE VC TES1 TEST D Vss1 FR D R FFD R D FC T TR D R TFD R SR D R SFD R D VD D 1 FSTO SSTP M D P FO K VPCO V16M VCTL PCO FILO CLTV TE ASYO AVDD0 IGEN AVss0 ADIO RFDC BIAS AVDD1 RFAC ASYI FILI AVss1 CE XRST CLOK SCLK XLAT MUTE DATA SENS WFCK DVDD0 ATSK MIRR XUGF XPCK GFS C2PO SCOR C4M WDCK DVss0 COUT LO C K PW M I XRST SQCK MUTE XLAT DATA CLOK SENS SCLK GFS SCOR PWMI VDD GND SQSO LDON C2PO C4M WDCK COUT D O U T LR C K PC M D BC K V16M LO C K D FC T D river C ircuit TG TD FD Vcc LD O N G N D R FO FZC FE TE C E FG VC SLED SSTP SPD L G N D +5V FSTO SCCY FOK MIRR WFCK XUGF XPCK EM PH SO U T SO C K XO LT SBSO

– 127 – CXD2585Q Package Outline Unit: mm SO N Y C O D E EIAJ C O D E JED EC C O D E PAC KAG E STR U C TU R E PAC KAG E M ATER IAL LEAD TR EATM EN T LEAD M ATER IAL PAC KAG E M ASS EPO XY R ESIN SO LD ER PLATIN G 42/C O PPER ALLO Y Q FP-80P-L03 LQ FP080-P-1414 0.6g 80PIN Q FP (PLASTIC ) 16.0 ± 0.4 14.0 – 0.1 + 0.4 0.3 – 0.1 + 0.15 0.1 – 0.1 + 0.15 (15.0) 0.127 – 0.05 + 0.1 1.5 – 0.15 + 0.35 201 4160 M ± 0.12 0.1 0.65