CXD2564AM

CXD2564AM SONY | Alldatasheet

Document overview

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Technical content

Features

5121s master clock Applications Sony's original new type of 3rd-order noise shaper DATs, Mini Disc players, Digital AV amplifiers, etc. * PLM type of pulse conversion output " . . bret gigtidlage Absolute Maximum Ratings © 18 or 16 bits selectable as input word length : me ee yee on Vong y Pin Configuration (Top View) * Allowable power Pe aed ©) 500 mw © Storage temperature Q)init bvo02@8) Tstg -55 to 150 Ke syst é orn naan Recommended Operating Conditions 2 . Supply voltage Voo 4.75 to 5.25 v @snier Lar) ® Operating temperature S)LATCH Avs L@4) Ta ~10 to 60 Pel S256 15 xvas) © Oscillation frequency @rest xn@ Fx (812fs) 16.31024.6 © MHz @pvss xourg)) ()rest2 xv000) (ack aves AG) @oara n2i+168) @urcx aveo 89) Goren R11+166) (mutes pvoe 1@5) ‘Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or olher right. Application circuits shown. if any, are typical examples illustrating the operation of the devices. Sony cannot assume rasponsibilily for any problems arising out of the use of these circuits. £92210 - ST

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[ Pin No. | Symbol | vo | Description INIT 1 | Resynchronized at the rising edge of this signal. | 2 |sysm | 1 _| Systemmute input. Serial control data input. [4 {SHiet | 1 | Shiftctock input | 5 | taTCH | 1 Latch clock input. [6 | 256s | © | 256tsclock output. toi Test pin; normally fixed low. [8 |DVvss | —— | Digital GND. [9 |test2 | 1 | Test pin: normally fixed low, |_| BCK input. [a1 [bata [1 _| Datainput. [32 [trek [1 [trexinpat [13 [muTe. | o | Left channel mute flag output. Right channel mute flag output. Digital power supply. Right channel PLM output 1 (positive phase). . | 17 [AVooR | — | Right channel! analog power supply. | 18 'R2(+) | O | Right channel PLM output 2 (positive phase). | 19 | AvssR_ | — | Right channel analog GND. | [20 |XVoo | — | Master clock power supply. 21 [xout | o | Crystal oscillator output (512fs). Se | Crystal oscittator input (512fs). 23 (| XVss —— | Master clock GND. 24 AVssL | —— | Left channel analog GND. 25 Lett channel PLM output 2 (positive phase). ~ —— | Leftchanne! analog power supply. 27 Lift) 6} 68 } Lett channel PLM output 1 (positive phase). 28 DVov2 —— | Digital power supply. —3-

Electrical Characteristics

(DVop=XVoo=AVopR=AVpoL=5.0V+5%, DVss=XVss=AVssL=AVssR=0V, Ta=-10 to 60°C) Item Symbol | Conditions [ Min. [Typ | Max. [Unit] ee [asoves ||| Low input [| 0.10Vo0 ee Tn [sof 50a] AC characteristics (DVoo=XVop=AVopR=AVpoL=5.0V+5%, DVss=XVss=AVssL=AVssR=0V, Ta=-10 to 60°C ) Symbol | —Condtons [Wan [Typ _| Max [Unt [pexpumewan [wesc [if ver [DaTAnogtine | W(OATA es LRCK setup time tsu (LACK) Co ee XIN duty duty (XIN) | Voo/2at2emHz | | —50|| |S | a a [Atrastptme [wus | a] LATCH setup time [tsu(@ar) | [=| ie [aToHtaisime | waar [100 [re -4-

{tw (BCK) ftw (BCK) | a Voo/2 } i Vo0/2 | } (DATA) | (OATA) | H DATA Ftw (SH) ftw (SH) | Voo/2 j b vo072 | SHIFT i i t bru | thay | ; : eu tw oth} KLAT) (LAT) (LAT t H Hi ; LATCH oe Analog characteristics (DVo0=XVpp=AVooR=AVooL=5.0V, DVss=XVss=AVssL=AVssR=0V, Ta=25 °C ) tem | Symbo! Conditions [ Min. [| Typ, | Max. | Unit Total harmonic Input data 1kHz, 0d8 Input data 1kHz, 0/- 00 0dB —5-

1) Mute function (1) Zero data detection : Detection is performed after attenuation processing. © The zero detection flag is output when the upper 14 bits of the input data are ail “0” or all "1", and the remaining lower bits are continually in the DC state. © The detection time can be selected as either 60ms or 300ms by serial control. © Even if the zero detection flag is being output, the digital filter operates normally. (2) Digital filter mute (O/F MUTE) @ MUTE is active when it is high in serial control ATT mode. © Output from the D/F section is set to ["0"+DC offset}. © The internal operations of the digital filter are performed normally. (3) Noise shaper mute (NS MUTE) NS mute is active when it is high in serial control system mode and any of the following conditions are met: © The zero detection flag has been set. © Ahigh signal is input to the input pin SYSM (=mute). ® The D/F MUTE flag has been set. © The noise shaper output is switched to output with a DC offset component added on by the D/F section. © The internal operations of the noise shaper are performed normally, and after muting is turned off, the output immediately switches to that from the noise shaper. (4) INIT low mute © The D/F section input data is set to “0”. © Clears the internal RAM. © The D/F section output is set to ["0"+DC offset]. (After the internal RAM is cleared, and before the internal INIT.) © After the internal INIT goes low, the noise shaper section registers are cleared including the pre-value hold section, and the output is set to duty 50% PWM (equivalent to “0”). 2) Mute flag output (MUTEL, MUTER pins) * When any of the following conditions are met, the mute active flag is output from the MUTEL and MUTER pins. {The polarity of the flag can be selected by the serial control.) © The zero detection flag has been set. @ Ahigh signal (=mute) is input to the input pin SYSM. © The D/F MUTE flag has been set. © The external INIT is active. —6- M™ $3823463 0016188 77?

SONY cx0258<am 3) Serial control © The mode is set by transferring mode data to the ATT, SHIFT, and LATCH pins. © The transfer format is shown below, arr YoeyasXreXrsX eX XroX 9X0 X7XsXsX aX 3X 2X1} SHIFT LATCH a © Bit 1 data is always “0”. © When bit 2 data is "0", attenuate mode is set. When bit 2 data is “1", system mode is set. © The setting is made after the external INIT is released. (The mode setting table is shown on the following page.) * SYNC function @ When SYNC |s set high in the serial control system mode, resynchronization is performed only once at the rising edge. @ A minimum period of 4fs and a maximum period of 5fs are required until internal synchronization is achieved. -7- M@ =4342383 0016189 433

« Attenuate mode Function { High H Low _ [4 [MoDe1 [MODE switching ! Test mode {Normal mode [2 | woDea | WODE sutcing | Systemmode _Aenuate mode _| 3 | EMP De-emphasis LON i OFF MUTE *0"+ DC offset output LON | OFF 5 | ATT Aitenuate data (MSB) : H [ 6 |ATI2 _| Attenuate data H i Attenuate dala i i | 8 [ata | Attenuate data A i [9 [ans | Attenuate data H i [10 [arte | Attenuate data i j [a1 [at | Attenuate data H H [12 [ATT8 —_| Attenuate data } : ATT Attenuate data : Hi 15; ATTN Attenuate data i H [16 [atri2 | Attenuate data (LSB) i Hl * When INIT is set low, MODE1, MODE2, EMP and MUTE are reset low and ATT is set to 400H. —g— @™ 8382383 0016190 355

SONY CxD2E6¢AM e System mode [ Bit | Modeflag | Function H High : Low | 31 | MODE1 MODE switching + Test mode } Normal mode | 2 | MODE2 MODE switching i System mode } Attenuate mode | 3 |IFORM | Input data format {LSB first | MSB first IT Input data word length 18.bits ! 16 bits | 5 | H don't care all i don't care Test mode setting : Normally fixed low Test mode setting 1 Normally fixed low [ 10 [NS __| Noise shaping { don't care [12 [m2 | Zero mute flag polarity } Mute when high } Mute when low [ 14 |Fs48 _| De-emphasis {s selection j * Refer to the table below WO synchronization TON POFF [16 | NSMUTE | NS mute function 1 ON | OFF * When INIT is set low, all are reset low, * De-emphasis fs selection _ = Reta [ ee —9~ M® $4342383 0016191 29]

4) INIT function © After the rising edge of the external INIT signal, once resynchronization has been performed, the D/F and NS sections are immediately and simultaneously released from the reset state. © The external LRCK is not changed by the external INIT signal, so that after the rising edge of the external INIT signal the phase of the internal LRCK is synchronized with the initial external LRCK at the master clock level. © A minimum period of 4fs and a maximum period of 5fs are required until internai synchronization is achieved. © The internal INIT is delayed by approximately 2 to 2.5ms after the falling edge of the external INIT signal. 5) Double-speed operation © Synchronization is maintained for signals input at double speed, while internal operations are performed at normal speed. 6) Attenuator © ATT data is transferred using the 12 bits from bit 5 (MSB) to bit 16 (LSB). The size is GOOH (0.0) to 400H (1.0). When the INIT is low, the ATT data is set to 400H, ATT data {output amplitude) © i . Lo ‘ CCH transfer 400H transfer The soft muting is performed by transferring OOOH as the ATT data. To release this function, the ATT data prior to soft muting (400H in the above illustration) is transferred. ATT dats 1.0 A (ATT) 8 (aTT3) CC *& atta) ° a In this way, ATT data is always sent through the soft muting operation. In the above illustration, assume ATT data where ATT1>ATT3>ATT2, and that first ATT1 is transferred, followed by ATT2. if ATT2 was transferred before the ATT1 value was attained (state “A” in the illustration), ATT1 is ignored and the value approaches ATT2. Next, ATT2 is transferred, and if ATTS is transferred before the ATT2 value is attained ("B” or °C” in the illustration), ATT2 is ignored and the value approaches ATT3. —190- WM 3382383 0016192 123 a

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