CXD2500BQ

CXD2500BQ SONY | Alldatasheet

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Technical content

Datasheet sections

Features

• All digital signals for regeneration are processed using one chip.
• The built-in RAM enables high-integration mounting. Structure Silicon-gate CMOS IC CD Digital Signal Processor 80 pin QFP (Plastic) CXD2500BQ

—2— CXD2500BQ Absolute Maximum Ratings(Ta=25 °C)

• Supply voltage V CC –0.3 to +7.0 V
• Input voltage V I –0.3 to +7.0 V
• Output voltage V O –0.3 to +7.0 V
• Operating temperature Topr –20 to +75 °C
• Storage temperature Tstg –40 to +125 °C
• Supply voltage differences VSS –AV SS –0.3 to +0.3 V VDD –AV DD –0.3 to +0.3 V Recommended Operating Conditions
• Supply voltage V DD 4.75*1 to 5.25*3 (5.0 V typ.) V
• Operating temperature Topr –20 to +75 °C
• Input voltage V IN VSS –0.3 to + VDD + 0.3 V *1 VDD value of 4.75 V (min.) is for the double-speed playback mode at vari-pitch control reset. For the low power consumption special playback mode, VDD value is 3.6 V (min.). *2 In the normal-speed playback mode VDD value is 4.5 V (min.) *2 Low power consumption, special playback mode Set the internal operation of LSI at the double-speed mode, and half the crystal oscillation frequency. This will result in the normal-speed playback mode. 3 VDD value of 5.25 V (max.) is for the double-speed playback mode at vari-pitch control reset. For normal- speed playback and the low power consumption special playback mode, the VDD value is 5.5 V (max.). I/O Capacity
• Input pins CI 12 pF max.
• Output pins CO 12 pF max. at high impedance Note: Test Conditions VDD =V I=0 V fM =1 MHz

—3— CXD2500BQ C4M C16M PDO VCO1 VCO0 PCO FIL1 FIL0 CLTV RF ASY1 ASY0 ASYE WFCK SCOR EXCK SBSO EMPH SQCK SQSO MON FSW MDP MDS TEST NC FSTTXTAIXTAOXTSL VCKIVPCO Timing Generator Subcode P-W Processor Subcode Q Processor Noise shaper CLV processor Timing Generator 2 Peak detector Digital out D/A data processor Address generator Register 535456 53 17 19 Clock generator Digital PLL vari-pitch double speed ∗ MUX Sync Protector EFM demodulator 18-times over samplling filter XRST LOCK APTRAPTLLRCKWDCK SEINSENSMIRRCNINFOX Error corrector 32K RAM Priority encoder CPU interface Servo auto sequencer Serial/Parallel processor 70 6 313250 51 16975 76 80 AV DD AV SS VDD VDD VSS VSS PSSL DAO 1 to 6 MUTE DOUT MD 2 DATA CLOK XLAT DATO CLKO XLTO 5 ∗Asymmetry correction. Block Diagram

—4— CXD2500BQ D2500B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 21 22 23 2419 EXCK SQSO SQCK MUTE SENS XRST DATA XLAT VDD CLOK SEIN CNIN DATO XLTO CLKO MIRR 414243444546474849505152535455565759 586061626364 SBSOSCORWFCKEMPHDOUTMD2 C16MC4M FSTTXTSLXTAQXTAIV SS APLLAPTRDA01DA02DA03DA04DA05DA06DA07DA08DA09 DA10 DA11 DA12 DA13 DA14 DA15 DA16 V DD LRCK WDCK PSSL ASYE ASYO ASYI BIAS NC FOK FSW MON MDP MDS LOCK VCOOVCOITESTPDO V SS VPCOVCKIFILOFILIPCO AV SS CLTVAV DD RFNCNCNCNC Pin Configuration

—5— CXD2500BQ FOK FSW MON MDP MDS LOCK NC VCOO VCOI TEST PDO V SS NC NC NC VPCO VCKI FILO FILI PCO AV SS CLTV AV DD RF BIAS ASYI ASYO ASYE NC PSSL WDCK LRCK V DD DA16 DA15 DA14 DA13 DA12 DA11 DA10 I O Z, 0 O 1, 0 O 1, Z, 0 O 1, Z, 0 O 1, 0 O 1, 0 I I O 1, Z, 0 O 1, Z, 0 I O Analog I O 1, Z, 0 I I I I O 1, 0 I I O 1, 0 O 1, 0 O 1, 0 O 1, 0 O 1, 0 O 1, 0 O 1, 0 O 1, 0 O 1, 0 Focus OK input. Used for SENS output and servo auto sequencer. Output used to switch the spindle motor output filter. Output for spindle motor ON/OFF control Output for spindle motor servo control Output for spindle motor servo control Output is “H” when the GFS signal sampled at 460 Hz is “H”. Output is “L” when the GFS signal is “L” 8 or more times in succession. Output of oscillation circuit for analog EFM PLL Input to oscillation circuit for analog EFM PLL f LOCK =8.6436 MHz Test. Normally at 0 V (GND). Output of charge pump for analog EFM PLL GND Output of charge pump for vari-pitch PLL Clock input from external VCO for vari-pitch control. fc center=16.9344 MHz. Output of filter for master PLL (Slave=Digital PLL) Input to filter for master PLL Output of charge pump for master PLL Analog GND VCO control voltage input for master PLL Analog power supply (+5 V) EFM signal input Asymmetry circuit constant current input Asymmetry comparator circuit voltage input EFM full-swing output Asymmetry circuit OFF at “L”. Asymmetry circuit ON at “H”. Input used to switch the audio data output mode. “L” for serial output, “H” for parallel output. D/A interface for 48-bit slot. Word clock f=2Fs D/A interface for 48-bit slot. LR clock f=Fs Power supply (+5 V) Outputs DA16 (MSB) when PSSL=1, or serial data from the 48-bit slot (2’s complements, MSB first) when PSSL=0. Outputs DA15 when PSSL=1, or bit clock from the 48-bit slot when PSSL=0. Outputs DA14 when PSSL=1, or serial data from the 64-bit slot (2’s complements, LSB first) when PSSL=0. Outputs DA13 when PSSL=1, or bit clock from the 64-bit slot when PSSL=0. Outputs DA12 when PSSL=1, or LR clock from the 64-bit slot when PSSL=0. Outputs DA11 when PSSL=1, or GTOP when PSSL=0. Outputs DA10 when PSSL=1, or XUGF when PSSL=0. Pin Description Pin Symbol I/O DescriptionNo.

—6— CXD2500BQ DA09 DA08 DA07 DA06 DA05 DA04 DA03 DA02 DA01 APTR APTL VSS XTAI XTAO XTSL FSTT C4M C16M MD2 DOUT EMPH WFCK SCOR SBSO EXCK SQSO SQCK MUTE SENS XRST DATA XLAT V DD CLOCK SEIN CNIN DATO XLTO CLKO MIRR O 1, 0 O 1, 0 O 1, 0 O 1, 0 O 1, 0 O 1, 0 O 1, 0 O 1, 0 O 1, 0 O 1, 0 O 1, 0 I O 1, 0 I O 1, 0 O 1, 0 O 1, 0 I O 1, 0 O 1, 0 O 1, 0 O 1, 0 O 1, 0 I O 1, 0 I I — 1, Z, 0 I I I I I I O 1, 0 O 1, 0 O 1, 0 I Outputs DA9 when PSSL=1, or XPLCK when PSSL=0. Outputs DA8 when PSSL=1, or GFS when PSSL=0. Outputs DA7 when PSSL=1, or RFCK when PSSL=0. Outputs DA6 when PSSL=1, or C2PO when PSSL=0. Outputs DA5 when PSSL=1, or XRAOF when PSSL=0. Outputs DA4 when PSSL=1, or MNT3 when PSSL=0. Outputs DA3 when PSSL=1, or MNT2 when PSSL=0. Outputs DA2 when PSSL=1, or MNT1 when PSSL=0. Outputs DA1 when PSSL=1, or MNT0 when PSSL=0. Control output for aperture correction. “H” for R-ch. Control output for aperture correction. “H” for L-ch. GND Input for 16.9344 MHz and 33.8688 MHz X'tal oscillation circuit. Output for 16.9344 MHz X'tal oscillation circuit. X'tal selection input. “L” for 16.9344 MHz X'tal, “H” for 33.8688 MHz X'tal. 2/3 frequency demultiplication output for Pins 53 and 54. Unaffected by vari-pitch control. 4.2336 MHz output. Subject to vari-pitch control. 16.9344 MHz output. Subject to vari-pitch control. Digital-Out ON/OFF control. “H” for ON, “L” for OFF. Digital-Out output. “H” for playback disc provided with emphasis, “L” for without emphasis. WFCK (Write Frame Clock) output. “H” when subcode Sync S0 or S1 is detected. Serial output of Sub P to W Clock input for reading SBSO Outputs 80-bit Sub Q and 16-bit PCM peak-level data. Clock input for reading SQSO “H” for muting, “L” for release. SENS output to CPU System reset. “L” for resetting. Inputs serial data from CPU. Latches serial data input from CPU at falling edge. Power supply (+5 V) Inputs serial data transfer clock from CPU. Inputs SENSE from SSP. Inputs track jump count signal. Outputs serial data to SSP. Latches serial data output to SSP at falling edge. Outputs serial data transfer clock to SSP. Inputs mirror signal to be used by auto sequencer when jumping 16 or more tracks. Pin Symbol I/O Description No.

—7— CXD2500BQ Note:

• The data at the 64-bit slot is output in 2’s complements on an LSB-first basis. The data at the 48-bit slot is output in 2’s complements on an MSB-first basis.
• GTOP monitors the state of Frame Sync protection. (“H”: Sync protection window released)
• XUFG is a negative Frame Sync pulse obtained from the EFM signal before Frame Sync protection is effected..
• XPLCK is an inversion of the EFM PLL clock. The PLL is designed so that the falling edge of XPLCK coincides with a change point of the EFM signal.
• The GFS signal turns “H” upon coincidence between Frame Sync and the timing of interpolation protection.
• RFCK is a signal generated at 136-µs periods using a crystal oscillator.
• C2PO is a signal to indicate data error.
• XRAOF is a signal issued when a jitter margin of ±28F is exceeded by the 32K RAM.

—8— CXD2500BQ Electrical Character DC characteristics (VDD =AV DD =5.0 V±5 %, VSS =AV SS =0 V, Topr=–20 to +75°C) Item Condition Min. Typ. Max. Unit Related pins Input voltage. “H” level Input voltage “L” level. Input voltage “H” level Input voltage “L” level Input voltage Output voltage “H” level Output voltage “L” level Output voltage “H” level Output voltage “L” level Output voltage “L” level Output voltage “H” level Output voltage “L” level Input leak current Tristate pin output leak current V IH (1) VIL(1) VIN (2) VIN (2) VIN (3) VOH (1) VOL (1) VOH (2) VOL (2) VOL (3) VOH (4) VOL (4) ILI ILO Schmitt circuit input Analog input IOH =–1 mA IOL =1 mA IOH =–1 mA IOL =2 mA IOL =2 mA IOH =–0.28 mA IOL =0.36 mA VI=0 to 5.25 V VO =0 to 5.25 V 0.7VDD V 0.3VDD V 0.8VDD V 0.2VDD V VSS VDD V VDD –0.5 V DD V 0 0.4 V VDD –0.5 V DD V 0 0.4 V 0 0.4 V VDD –0.5 V DD V 0 0.4 V ±5 µA ±5 µA *1, *2, *3 Output Output Output Output Input Input Input voltage (4) voltage (3) voltage (2) voltage (1) voltage (3) voltage (2) voltage (1) Related pins *1 XTSL, DATA, XLAT, MD2, PSSL *2 CLOK, XRST, EXCK, SQCK, MUTE, FOK, SEIN, CNIN, MIRR, VCKI, ASYE *3 CLTV, FILI, RF *4 MDP, PDO, PCO, VPCO *5 ASYO, DOUT, FSTT, C4M, C16M, SBSO, SQSO, SCOR, EMPH, MON, LOCK, WDCK, DATO, CLKO, XLTO, SENS, MDS, DA01 to DA16, APTR, APTL, LRCK, WFCK *6 FSW *7 FILO *8 SENS, MDS, MDP, FSW, PDO, PCO, VPCO

—9— CXD2500BQ AC Characteristics (1) XTAI and VCOI pins 1) During self-oscillation (Topr=–20 to +75 °C, V DD =AV DD =5.0 V±5 %) 2) With pulses input to XTAI and VCOI pins (Topr=–20 to +75 °C, V DD =AV DD =5.0 V±5 %) 3) With sine waves input to XTAI and VCOI pins via capacitor (Topr=–20 to +75 °C, VDD =AV DD =5.0 V±5 %) Item Oscillation frequency Symbol fMAX Min. Typ. Max. Unit MHz Item Input amplitude Symbol Min. 2.0 Typ. Max. VDD +0.3 Unit Vp-p Item “H” level pulse width “L” level pulse width Pulse period Input “H” level Input “L” level Rising time Falling time Symbol t WHX tWLX tCX VIHX VILX tR , tF Min. V DD –1.0 Typ. Max. 500 500 1,000 0.8 Unit ns V ns tCX tWHX tWLX XTAI tR tF VIHX VIHX×0.9 VDD /2 VIHX×0.1 VILX

—10— CXD2500BQ (1) CLOK, DATA, XLAT, CNIN, SQCK, and EXCK pins (VDD =AV DD =5.0 V±5 %, VSS =AV SS =0 V, Topr=–20 to +75 °C Item Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width EXCK, CNIN, SQCK frequency EXCK, CNIN, SQCK pulse width Symbol f CK tWCK tSU tH tD tWL fT tWT Min. 750 300 300 300 750 300 Typ. Max. 0.65 Unit MHz ns MHz ns 1/fCK tWCK CLOK DATA XLAT tWCK tSU tH tD tWL tWT tSU tH tWT 1/fT EXCK CNIN SQCK SUBQ SQCK Description of Functions §1 CPU Interface and Commands

• CPU interface This interface is used to set various modes using DATA, CLOK, and XLAT. The interface timing chart is shown below. CLOK DATA XLAT Data Address D1 D2 D3 D0 D1 D2 D3 300ns max ValidRegisters 4 to E 750ns or more 750ns or more
• The command addresses of the CXD2500B and the data capable of being set are shown in Table 1-1.
• When XRST is set to 0, the CXD2500B is reset, causing its internal registers to be initialized to the values listed in Table 1-2.

—11— CXD2500BQ Register name A B C D E Command Auto sequence Blind (A, E), Overflow (C) Brake (B) KICK (D) Auto sequencer track jump (N) setting MODE specification Func specification Audio CTRL Traverse monitor counter setting Servo factor setting CLV CRTL CLV mode Address D3 D2 D1 D0 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 Data 1 D3 D2 D1 D0 AS3 AS2 AS1 AS0 0.18 ms 0.09 ms 0.045 ms 0.022 ms 0.36 ms 0.18 ms 0.09 ms 0.045 ms 11.6 ms 5.8 ms 2.9 ms 1.45 ms 32,768 16,384 8,192 4,096 CDROM 0 D OUT WSEL Mute-F D CLV DSPB A SEQ D PLL ON-OFF ON-OFF ON-OFF ON-OFF Vari Vari Mute ATT UP Down 32,768 16,384 8,192 4,096 Gain Gain Gain Gain MDP1 MDP0 MDS1 MDS0 DCLV TB TP CLVS PWM MD Gain CM3 CM2 CM1 CM0 Data 2 D3 D2 D1 D0 ———— ———— ———— 2,048 1,024 512 256 ———— BiliGL BiliGL FLFC — MAIN SUB PCT1 PCT2 — — 2,048 1,024 512 256 ———— ———— ———— Data 3 D3 D2 D1 D0 ———— ———— ———— 128 64 32 16 ———— ———— ———— 128 64 32 16 ———— ———— ———— Data 4 D3 D2 D1 D0 ———— ———— ———— 8421 ———— ———— ———— 8421 ———— ———— ———— Commands Table 1-1

—12— CXD2500BQ Register name A B C D E Command Auto sequence Blind (A, E), Overflow (C) Brake (B) KICK (D) Auto sequencer track jump setting MODE specification Func specification Audio CTRL Traverse monitor counter setting Servo factor setting CLV CRTL CLV mode Address D3 D2 D1 D0 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 Data 1 D3 D2 D1 D0 0000 0101 0111 0000 0000 1001 0011 0000 0110 0000 0000 Data 2 D3 D2 D1 D0 ———— ———— ———— 0001 ———— 000 — 00 — — 0001 ———— ———— ———— Data 3 D3 D2 D1 D0 ———— ———— ———— 0000 ———— ———— ———— 0000 ———— ———— ———— Data 3 D3 D2 D1 D0 ———— ———— ———— 0000 ———— ———— ———— 0000 ———— ———— ———— Reset Initialization Table 1-2

Example: D3=0 D2=D1=D0=1 (Initial Reset) D=10.15ms $7X Command Used to set the number of auto sequencer track jumps/moves. This command sets the value of “N” for 2N track jump and M track move execution using the auto sequencer. —13— CXD2500BQ §1 Meanings of Data Set at Command Addresses $4X Command Command CANCEL FOCUS-ON

1 TRACK JUMP

10 TRACK JUMP

Blind(A, E), Overflow(C) Brake(B) 0.18 ms 0.36 ms 0.09 ms 0.18 ms 0.045 ms 0.09 ms 0.022 ms 0.045 ms RXF=0 FORWARD RXF=1 REVERSE

• If a Focus-ON command ($47) is canceled during execution, $02 is issued and the auto sequence operation is discontinued.
• If a Track Jump or Track Move command ($48 to $4F) is canceled during execution, the auto sequence operation is discontinued. $5X Command Used to set timers for the auto sequencer. Timers set: A, E, C, and B Example: D2=D0=1, D3=D1=0 (Initial Reset) A=E=C=0.112 ms B=0.225 ms $6X Command Used to set a timer for the auto sequencer. Timer set: D Command KICK (D) 11.6 ms 5.8 ms 2.9 ms 1.45 ms Command Auto sequencer track jump number setting Data3 D3 D2 D1 D0 215 214 213 212 Data 2 D3 D2 D1 D0 211 210 29 28 Data 3 D3 D2 D1 D0 27 26 25 24 Data 4 D3 D2 D1 D0 23 22 21 20

—14— CXD2500BQ

• The maximum number of tracks that can be counted is 65,535. However, in the case of 2N track jumps, it is subject to mechanical restrictions due to the optical system.
• When the number of tracks to be jumped is smaller that 15, the signals input from CNIN are counted. When it is 16 or larger, the signals input from the MIRR pin are counted. This count signal selection contributes toward improving the accuracy of high-speed track jumping. $8X Command Command MODE specification CDROM D. OUT Mute-F AS0 WSEL Command CDROM=1 CDROM=0 C2PO timing 1-3 1-3 Processing CDROM mode is entered. In this mode, average value interpolation and preceding value holding are not performed. Audio mode is entered. In this mode, average value interpolation and preceding value holding are performed. Command bit D. out Mute F=1 D. out Mute F=0 Processing When Digital Out is ON (pin MD2=1), DA output is muted. Da output muting is unaffected by the setting of Digital Out. D/A Out D.out Mute with F=1 Mute-ON Mute-OFF MD2=1 (D. out-ON) – ∞ dB – ∞ dB MD2=0 (D. out-OFF) – ∞ dB 0dB Command bit WSEL=1 WSEL=0 Sync protection window width ±26 channel clock pulses* ±6 channel clock pulses Application Anti-rolling is enhanced. Sync window protection is enhanced. * In normal-speed playback, the channel clock frequency is 4.3218 MHz. $9X Command Command Func specification Data 1 D3 D2 D1 D0 DCLV DSPB A. SEQ D. PLL ON-OFF ON-OFF ON-OFF ON-OFF Data 2 D3 D2 D1 BiliGL BiliGL FLFC MAIN Sub

—16— CXD2500BQ Description of SENS signals SENS output Z SEIN XBUSY FOK GFS COMP COUT OV64 Meaning SENS is at High-Z state. SEIN signal, which was input to the CXD2500B, is output from SSP. “L” when auto sequencer is in operation; “H” when terminated. Output of the signal (normally FOK input from RF) input to the FOK pin. “H” when Focus OK is received. “H” when regenerated Frame Sync is obtained at the correct time. Used in counting the number of tracks set in register B. “H” when the count is latched to register B twice in succession. It is reset to “L” level when the count of CNIN inputs equals the originally set number for register B. Used in counting the number of tracks set in register B. “H” when the count is latched to register B, then to register C. It is toggled every time the count of CNIN inputs reaches the value set in register B. “L” when after passing through the sync detection filter, the EFM signal become longer than the 64 channel clocks. Command bit DPLL=0 DPLL=1 Meaning RFPLL enters analog mode. PDO, VCOI, and VCOO are used. RFPLL enters digital mode. PDO becomes Z. Command bit BiliGL SUB=0 BiliGL SUB=1 BiliGL MAIN=0 STEREO SUB BiliGL MAIN=1 MAIN Mute Definition of Bilingual MAIN, SUB, and STEREO MAIN; The input L-ch signal is output to both L-ch and R-ch. Sub: The input R-ch signal is output to both L-ch and R-ch. STEREO: The input L-ch and R-ch signals are output to both L-ch and R-ch respectively.

—17— CXD2500BQ $AX Command Command Audio CTRL Data 1 D3 D2 D1 D0 Vari Vari Mute ATTUP DWN Data 2 D3 D2 PCT1 PCT2 Vari UP Vari DWN Command bit Mute=0 Mute=1 Meaning Muting is off unless condition to make muting occurs. Muting is on. Peak register reset. Command bit ATT=0 ATT=1 Meaning Attenuation is off. –12dB Condition for Muting (1) Mute=1 in register A (2) Pin Mute=1 (3) D.OUT Mute F=1 in register 8 with D.Out ON (MD2=1) (4) Elapse of over 35 msec after GFS turns “Low” (5) BiliGL MAIN=Sub=1 in register 9 (6) PCT1=1 and PCT2=2 in register A In the case of (1) to (4), zero-cross muting not exceeding 1 msec is performed. Command bit PCT1 PCT2 Meaning Normal mode Level meter mode Peak meter mode Normal mode PCM Gain

• 0 dB
• 0 dB Mute
• 0 dB ECC correction capacity C1: Double, C2: Quadruple C1: Double, C2: Quadruple C1: Double, C2: Double C1: Double, C2: Double Level Meter Mode(See Timing Chart 1-4.)
• This mode makes the digital level meter function available.
• Inputting 96-bit clock pulses to SQCK will enable 96 data to be output to SQSO. Of the output data, the first 80 bits comprise Sub-Q data, which transmit the description for the data format to the Sub Code interface. The last 16 bits are ordered LSB-first, of which the first 15 bits constitute PCM data (absolute value). The final 1 bit is “High” if the prior PCM data was generated at the left channel; “Low” if generated at the right channel.
• The PCM data is reset once it is read, and the L/R flag is reversed. While this state is kept until the next read operation is started, testing for the maximum value is conducted.

—18— CXD2500BQ Peak Meter Mode(See Timing Chart 1-5.)

• In this mode, the maximum value of PCM data is detected whether the channel involved is L-ch or R-ch. To read the detected maximum value, it is necessary to input 96 clock pulses to SQCK.
• When 96 clock pulses have been input to SQCK, 96 bits of data is output to SQSO. At the same time, the data is re-set in an internal register of the LSI. That is, the PCM peak detection register is not reset when it is read.
• To reset the PCM peak register, set both PCT1 and PCT2 to 0. Or, Set $AX mute.
• In this mode, the absolute time of Subcode Q is controlled automatical.
• Namely, every time a peak value is detected, the absolute time when the CRC was passed is stored. The program time operation is performed in the normal way.
• The last bit (L/R flag) of the 96-bit data stays 0.
• In this mode, the preceding value holding and average value interpolation data are fixed to level (–∞ ). $CS Command Command Servo factor setting CLV CTRL ($DX) D3 D2 D1 D0 Gain Gain Gain Gain MDP1 MDP0 MDS1 MDS0 Gain CLVS Explanation Only DCLV=1 is effective. DCLV=1 and DCLV=0 are both effective. This command is used to externally set the spindle servo gain when DCLV=1.
• Gain setting for CLVS mode: GCLVS Gain Gain Gain GCLVS MDS1 MDS0 CLVS 0 0 0 –12dB 0 0 1 –6dB 0 1 0 –6dB 011 0 d B 100 0 d B 1 0 1 +6dB Note: When DCLV=0, the CLVS gain is determined as follows: If Gain CLVS=0, then GCLVS=–12 dB. If Gain CLVS=1, then GCLVS=0 dB
• Gain setting for CLVP mode: GMDP, GMDS Gain Gain GMDP MDP1 MDP0 0 0 –6 dB 0 1 0 dB 1 0 + 6dB Gain Gain GMDS MDS1 MDS0 0 0 –6dB 0 1 0dB 1 0 +6dB

—19— CXD2500BQ $DC Command Command CLV CTRL DCLV PWM MD TB TP CLVS Gain See “$CX Command.” Command bit DCLV PWM MD=1 DCLV PWM MD=0 Description (See Timing Chart 1-6.) Specification of PWM mode for digital CLV. Both MDS and MDP are used. Specification of PWM mode for digital CLV. Ternary MDP values are output. Command bit TB=0 TB=1 TP=0 TP=1

Description

In CLVS or CLVH mode, bottom value is held at periods of RFCK/32. In CLVS or CLVH mode, bottom value is held at periods of RFCK/16. In CLVS mode, peak value is held at periods of RFCK/4. In CLVS mode, peak value is held at periods of RFCK/2. In CLVH mode, peak holding is made at 34 kHz. $EX Command Command CLV mode D3 D2 D1 D0 CM3 CM2 CM1 CM0 CM3 CM2 CM1 CM0 Mode 0 0 0 0 STOP 1 0 0 0 KICK 1 0 1 0 BRAKE 1 1 1 0 CLVS 1 1 0 0 CLVH 1 1 1 1 CLVP 0 1 1 0 CLVA Explanation See Timing Chart 1-7. See Timing Chart 1-8. See Timing Chart 1-9. STOP: Spindle motor stop mode KICK: Spindle motor forward run mode BRAKE: Spindle motor reverse run mode CLVS: Rough servo mode for use for pulling disc run into RF-PLL capture range when the RF-PLL circuit lock has been disengaged CLVP: PLL servo mode CLVA: Automatic switching mode for CLVS and CLVS. This mode is used during normal play status.

—20— CXD2500BQ Timing Chart 1-3 LRCK WDCK CDROM=0 C2PO CDROM=1 C2PO Rch 16bit C2 Pointer Lch 16bit C2 Pointer C2 Pointer for upper 8bit C2 Pointer for Lower 8bit C2 Pointer for upper 8bit C2 Pointer for Lower 8bit Rch C2 pointer Lch C2 pointer If C2 pointer=1, data is NG 48bit Slot

—21— CXD2500BQ Timing Chart 1-4 Level Meter Timing 1 23 1 23 16 bitPeak data of this section96 bit data Hold section L/R CRCF R/L CRCF 96 clock pulses 96 clock pulses SQSO SQCK WFCK Sub-Q Data See "Sub Code interface" SQSO SQCK 15-bit peak-data Absolute value display, LSB first Peak data L/R flag L/RD14D13D6D5D4D3D2D1D0 750ns to 120µs 8180123 CRCF

—22— CXD2500BQ Timing Chart 1-5 Peak Meter Timing 123 123 CRCF Measurement 96 clock pulses CRCF Measurement 96 clock pulses Measurement CRCF WFCK SQCK

—23— CXD2500BQ Z Acceleration n·236 (nsec) n=0 to 31 Deceleration 132KHz 7.6µSec DCLV PWM MD=1 7.6µSec Acceleration n·236 (nsec) n=0~31 Deceleration Z MDS MDP MDS MDP DCLV PWM MD=0 Timing Chart 1-6 Output Waveforms with DCLV=1 Timing Chart 1-7 Z STOP DCLV=0 MDS MDP FSW MON L L L MDP MDS DCLV=1 DCLV PWM MD=0 STOP Z Z MDP MDS DCLV=1 DCLV PWM MD=1 STOP L FSW and MON are the same as for DCLV=0

—24— CXD2500BQ Z KICK DCLV=0 MDS MDP FSW MON H H MDP MDS DCLV=1 DCLV PWM MD=0 Z Z MDP MDS DCLV=1 DCLV PWM MD=1 L KICK KICK H 7.6µs H H L Timing Chart 1-8 FSW and MON are the same as for DCLV=0 FSW and MON are the same as for DCLV=0

—25— CXD2500BQ Z BRAKE DCLV=0 MDS MDP FSW MON L H MDP MDS DCLV=1 DCLV PWM MD=0 Z Z MDP MDS DCLV=1 DCLV PWM MD=1 L L BRAKE Timing Chart 1-9 FSW and MON are the same as for DCLV=0 FSW and MON are the same as for DCLV=0

—26— CXD2500BQ §2 Subcode Interface In this section, the subcode interface will be explained. The contents of the subcode interface can be externally read in two ways. The subcodes P through W totaling 8 bits can be read from SBSO by inputting EXCK to the CXD2500B. Sub-Q can be read after conducting a CRC check on the 80bits of information in the subcode frame. First, check SCOR and CRCF, then input 80 clock pulses to SQCK and read the data. §2-1 P-W Subcode Read These subcodes can be read by entering EXCK immediately after the fall of WFCK. (See Timing Chart 2-1.) §2-2 80-bit Sub-Q Read Figure 2-2 shows a block diagram of the peripheral part of the 80-bit Sub-Q register.

• The Sub Q regenerated on a bit-per-frame basis is input to the 80-bit serial/parallel register and the CRC circuit.
• When the results of CRC of the 96-bit Sub-Q are OK, CRCF is set to 1 and the 96-bit data is output to SQSO. Furthermore, it is loaded into the 80-bit, parallel/serial register. If SQSO is “H” after the output of SCOR, it can be taken that CPU has been loaded a new set of CRCOK data.
• When 80-bit data is loaded into CXD2500B, MSB and LSB are reversed within each byte of the data. Therefore, the bits are ordered LSB-first within each byte, even though the byte arrangement is kept unchanged.
• When 80 bits of data are confirmed to have been loaded, SQCK is input to read the data. Subsequently in the CXD2500B, the input of SQCK is detected and the retriggerable monostable multivibrator is reset during Low.
• The time constant of the retriggerable monostable multivibrator ranges from 270 to 400 µs. If the time of High for SQCK is less than this time constant, the monostable multivibrator will keep resetting, preventing the contents of the P/S register from being loaded into the P/S register.
• While the monostable multivibrator is resetting, data loading into the peak detection parallel/serial register and 80-bit parallel/serial register is forbidden. Therefore, while data read operation is carried out at clock periods shorter than the time constant of the monostable multivibrator, the contents of these registers are retained without being rewritten by CRCOK, etc.
• The CXD2500B permits the peak detection register to be connected to the shift-in of the 80-bit P/S register. For Ring Control 1, the input and output are short-circuited during peak meter and level meter mode. For Ring Control 2, the input and output are short-circuited during peak meter mode only. The Ring Controls are arranged in this way in order for the registers to be reset each time their contents are read in the level meter mode, while preventing destructive read in the peak meter mode. To enable this control, 96 clock pulses must be input to the peak meter mode.
• As afore mentioned, in the peak meter mode, the absolute time following the generation of a peak value is stored. These operations are shown in Time chart 2-3. Note: To perform the above operations, the duration of the clock pulse input to SQCK must be between 750ns and 120 µs for both “High” and “Low”.

—27— CXD2500BQ 750ns max WFCK SCOR EXCK SBSO WFCK SCOR EXCK SBSO Same Same S0·S1 Q R S T U V W P1S0·S1 Q R S T U V W P1 S0·S1 Q R P2 P3 Internal PLL c lock 4.3218±ΔMHz Timing Chart 2-1

(AMIN) (ASEC) (AFRAM) SIN SUB-Q A B C D E F G H A B C D E F G H SI LD LD LD LD LD LD LD 80 bit S/P Register 80 bit P/S Register OrderInversion SUBQ SHIFT SHIFT SQCK SQSO SI 16Monostablemultivibrator CRCC ABS time l oad control for peak value LOAD CONTROLE LD Ring control 1 SO 16 bit P/S register Ring control 2 CRCF Mix Peak detection —28— CXD2500BQ Block Diagram 2-2

—29— CXD2500BQ Register load forbidder When SQCK=High, 270 to 400µsec Determined by mode 80 or 96 Clock CRCF 1 OrderInversion CRCF 1 CRCF 2 WFCK SCOR SQSO SQCK Monostablemultivibrator(Internal) 750ns to 120µs CRCF ADR0 ADR1 ADR2 ADR3 CTL0 CTL1 CTL2 CTL3 300ns max SQCK SQSO Timing Chart 2-3

—30— CXD2500BQ §3 Other Functions §3-1 Channel Clock Regeneration Using Digital PLL Circuit

• Demodulation of regenerated EFM signals using an optical system requires the use of channel clock pulses. The EFM signal to be demodulated has been modulated into an integer multiple of the channel clock period T, ranging from 3T to 11T. To read the information conveyed by the EFM signal, it is essential to correctly recognize the integral value; hence, the need to use channel clock pulses. In an actual CD player, the pulse width of the EFM signal will vary, affected by fluctuations of the disc rotation. For this reason, it is necessary to use a PLL in regenerating channel clock pulses. Figure 3-1 shows a block diagram of the 3-stage PLL contained in the CXD2500B.
• The 1st-stage PLL is used for vari-pitch regeneration. To use this PLL, LPF and VCO are necessary as external parts. The minimum pitch variable possible is 0.1 %. The output of this 1st-stage PLL is used as the standard for all the clock pulses used in the LSI. When vari-pitch control is not in uses, connect the output pin of XTAO to VCKI.
• The 2nd-stage PLL generates high frequency clock pulses necessary for the 3rd-stage digital PLL.
• The 3rd-stage comprises a digital PLL used to regenerate the actual channel clock pulses. It realizes a capture range of ±150 kHz (normal conditions) or more.
• The digital PLL features a secondary loop. It is controlled through the primary loop (phase) secondary loop (frequency). When FLFC=1, the secondary loop can be turned off.
• When high frequency components such as 3T, 4T, are deviated, turning off the secondary loop will provide better play ability.
• However, the capture range will be 50 kHz.

—31— CXD2500BQ OSC X'Tal XTSL 16,9344MHz (384Fs) 1/1000+n Phase comparator VPCO LPF VCO 19. 78 to 13.26MHz Up down counter n=-217 to 168Vari-pitch 2/1 MUX Microcomputer control Vari-pitch I/M I/N Phase comparator VCKI PCO FILI FILO CLTVVCO RFPLL Digital PLL D2500B Block Diagram 3-1

—32— CXD2500BQ §3-2 Frame Sync Protection

• During CD player operation at normal speed, Frame Sync is recorded approximately once every 136 µs (at 7.35 kHz). This signal can be used to identify the data within each frame. When Frame Sync cannot be recognized, the data also cannot be identified; as a result, it is treated as an error. Therefore, correct Frame Sync recognition is very important to ensure high play ability for the CD player.
• The CXD2500B employs window protection, front protection and rear protection to realize a powerful Frame Sync protection. The CXD2500B offers two window widths, one for use when the player is subjected to rotational disturbance and the other for use without such disturbance (WSEL=0/1). The front protection counter is fixed at 13 and the rear protection counter at 3. Therefore, during normal play back, when the frame sync cannot be detected due to damages on the disc. If the number to frames with undetected Frame Sync exceeds 13, the window is released and the Frame Sync signal are re-synchronized. If no Frame Sync is correctly detected in 3 successive frames immediately after Frame Sync re- synchronization performed following a window release, the window is released at once. §3-3 Error Correction
• On CDs, each data unit (8 bits) is formatted so that it is contained in two correction codes, C1 and C2. C1 consists of 28 bytes of information and 4-byte parity, whereas C2 is made up of 24 bytes of information and 4-byte parity. Both C1 and C2 comprise a read Solomon code with a minimum distance of 5.
• C1 realizes double corrections and C2 realizes quadruple corrections, both by the refined superstrategy method.
• To prevent erroneous C2 corrections, C1 pointer based on the conditions of C1 error, EFM signal play back, and player operation during C1 operation is attached to the corrected data.
• The status of error correction can be monitored from outside the LSI. It is indicated as shown in Table 3-2.
• When C2 pointer is High, this signifies uncorrectable data error. The data are either previous data held subsitute the error, or an average value interpolation. MNT3 MNT2 MNT1 MNT0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

C1: No error detected. C1 pointer reset. C1: 1 error corrected. C1 pointer set. C1: No error detected. C1 pointer set. C1: 1 error corrected. C1 pointer set. C1: 2 errors corrected. C1 pointer set. C1: Uncorrectable error. C1 pointer set. C2: No error detected. C2 pointer reset. C2: 1 error corrected. C2 pointer reset. C2: 2 errors corrected. C2 pointer reset. C2: 3 errors corrected. C2 pointer reset. C2: 4 errors corrected. C2 pointer reset. C2: Uncorrectable error. C1 pointer copied. C2: Uncorrectable error. C2 pointer set. Table 3-2 Indication of error correction status

—33— CXD2500BQ Normal - speed PB RFCK MNT3 MNT2 MNT1 MNT0 Strobe t=Dependent on error condition C1 correction C2 correction Strobe C4M MNT0 to 3 Valid Invalid Valid 400 to 500nsec Timing Chart 3-3 §3-4 DA Interface

• The CXD2500B has two modes of DA interface. a) 48-bit slot interface This is an MSB-first interface made up of LRCK signals with 48-bit clock cycles per LRCK cycle. While the LRCK signal is High, the data going through this interface is of the left channel. b) 64-bit slot interface This is an LSB-first interface made up of LRCK signals with 64-bit clock cycles per LRCK cycle. While the LRCK signal is Low, the data going through this interface is of the left channel.

—34— CXD2500BQ Timing Chart 3-4 123456789 1 0 1 1 1 2 R ch MSBL0L ch MSB (15)R 0DA16 WDCK 12 24 DA16 R0 L ch MSB (15) L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L0 L1L2L3L4 RMSB WDCK 48 bit slot Normal-Speed Playback PSSL=L 48 bit slot Double-Speed Playback LRCK (44.1K) DA15 (2.12M) LRCK (88.2K) DA15 (4.23M)

—35— CXD2500BQ Timing Chart 3-5 L ch LSB (0) R ch LSB (0) R15

64 Bit slot Normal Speed PB PSSL=L

R ch LSB (0)

64 Bit slot Double–Speed PB

DA 12(44.4K)DA 13(2.82M) DA 14 DA 12(88.2K)DA 13(5.64M) DA 14

—36— CXD2500BQ §3-5 Digital Out There are three digital-out formats: type 1 for use at broadcasting stations, type 2, form 1 for use in general civil applications, and type 2, form 2 for use in software production. The CXD2500B supports type 2, form 1. The clock accuracy for the channel status is automatically set at Level II when the X'tal clock is used, or Level III when vari-pitch control is made. CRC checks are conducted on the Sub-Q data on the first 4 bits (bits 0-3). The data is input only after two checks are passed in succession. The X'tal clock is set to 34 MHz, and variable pitch is reset. When D out is output at DSPB=1, set MD2 to 0 and turn off D out 34. Digital Out C bit 0123456 7 89 1 0 1 1 1 2 1 3 1 4 1 5 From sub-Q 000010000000ID0 ID1 COPYEmph 0000000000000 0 / 1 00 Bits 0-3: Sub-Q control bits required to pass the CRC twice in succession. bit 29: Varipitch: 1 X'tal: 0 Table 3-6 Digital Out C bits §3-6 Servo Auto Sequencer The servo auto sequencer controls a series of operation including auto-focusing and track jumping. When an auto sequence command is received from CPU, the servo auto sequencer automatically executes auto- focusing, 1-track jumping, 2N track jumping and M track moving. During auto sequence execution (X Busy=Low), as SSP (servo signal processing LSI) is used exclusively, commands from CPU are not transferred to SSP. Instead, the commands can be sent to CXD2500B. To make this servo auto sequencer usable, connect a CPU, RF and SSP to the CXD2500B as shown in Figure 3-7 and set A.SEQ ON-OFF of Register 9 to ON. When the CLOK changes from Low to High while XBUSY is at Low, from that point on to a maximum of 100 µsec, X BUSY does not become High. Due to the monostable multivibrator which is reset when CLOK is Low (XBUSY=Low), transfer of erroneous data to SSP is prevented when XBUSY changes from Low to High.

—39— CXD2500BQ (b) Track Jump Track jump operation includes 1, 10 and 2N track jumps. Do not perform this track jump unless the focus, tracking and sled servos are on. Such steps as tracking gain up and braking are not included in this track jump. Therefore, the commands for tracking gain up and brake ON ($17) must be issued in advance.

• 1-track jump When a $48 is received from CPU (or a $49 from REV), the servo auto sequencer executes a FWD (REV) 1-track jump as shown Figure 3-9. The values of blind A and brake B must be set in Register 5.
• 10-track jump When a $4H is received from CPU (or a $4B from REV), the servo auto sequencer executes a FWD (REV) 10-track jump as shown in Figure 3-10. The principal difference between the 1-track and 10-track jumps is whether the sled is kicked or not. In the 10-track jump, the actuator after being kicked is braked when CNIN has been counted 5 tracks. When the actuator has adequately slowed down as a result of braking, the tracking and sled servos are turned on (this actuator slow-down is detected by checking whether the CNIN period has exceeded overflow C specified in Register 5).
• 2N track jump When a $4C is received from CPU (or a $4D from REV), the servo auto sequencer executes a FWD (REV) 2N track jump. The number of tracks to be jumped is determined by N, set Register 7 beforehand. The maximum permissible number is 2 16. In actual use, however, it is subject to limitation imposed by the actuator. When N is smaller than 16, the jumps are counted by means of counting CNIN signals. If N is 16 and above, MIRR signals are counted instead of CNIN signals. The 2N track jump sequence is basically the same as the 10-track jump sequence. The only difference between them is that, in the 2N track jump sequence, the sled is kept moving for time D specified in Register 6 after the tracking servo is turned on.
• M track move When a $4E is received from CPU (or a $4F from REV), the servo auto sequencer executes a FWD (REV) M-track move as shown in Figure 3-12. The maximum value that can be set from M is 2 16. The track moves are counted in the same way as for 2N track jumps. That is, when M is smaller than 16, the moves are counted by means of counting CNIN signals. If M is 16 and above, MIRR signals are counted instead of the CNIN signals. In this M track move, only the sled is moved. This method is suitable for a large track move ranging from several thousand to several tens of thousand tracks.

—40— CXD2500BQ

1 Track

(Blind A) CNIN= NO YES WAIT (Brake B) Track sled Servo ON END (REV kick is made for REV jump.) (FWD kick is made for REV jump.) Track Kick Sled servo Track REV Kick Figure 3-9 (a) Flow chart of 1-track jump Figure 3-9 (b) Timing chart for 1-track jump $48 (REV=$49) latch XLAT CNIN BUSY Blind A Brake B $28 ($2C)Commands to SSP $25$2C ($28)

—41— CXD2500BQ

10 Track

Track, Sled FWD Kick WAIT (Blind A) (5 CNINs are counted.) CNIN=5? C=Overflow? NO YES NO YES Track, REV FWD Kick Track, Sled Servo ON Checking whether the CNIN period has exceeded the value of overflow C. Figure 3-10 (a) Flow chart of 10-track jump Figure 3-10 (b) Timing chart for 10-track jump $4A (REV=$4B) latch XLAT CNIN BUSY Blind A CNIN 5count Overflow C $25Commands to SSP

—44— CXD2500BQ §3-7 Digital CLV The digital CLV is a digital spindle servo, of which its block diagram is shown in Figure 3-14. It is capable of outputting MDS or MDP error signals by the PWM method after raising the sampling frequency up to 130 kHz based on the normal speed in the CLVS, CLVP and other modes. It also permits gain setting. Digital CLV CLVS U/D MDS Error MDP Error Measure0, –6dBGain CLV P/S 2/1 MUX GP(Gain) CLV P CLV S CLV – P/S Noise Shape Modulation Mode Select DCLVMD MDP MDS KICK, BRAKE STOP Measure Gs(Gain) Over Sampling Filter-1 Mux Over Sampling Filter-2 Figure 3-14 Block diagram

—45— CXD2500BQ §3-8 Asymmetry correction Block diagram and circuit example are shown on Fig. 3-15. ASYO ASYI BIAS RF ASYE D2500B R1 2 R2 5 Figure 3-15 Asymmetry correction application circuit example

—46— CXD2500BQ 19 18 17 16 15 13 14202123 22 4440393837 434241 48474645 2536 38 37 7372717069686766 80797877767574 2633 32 31 30 29 28 2735 3440 39 Vee GND VCC C2PO MUTE WDCK DATA BCLK LRCK DEMP GND VCC CLK MUTE SCOR SQCK SUBQ GFS XLT DATA XRST SENS FOK LDON MNT0 MNT1 MNT2 MNT3 GND FOK FSW MON MOP MOS LOCK NC VCOO VCOI TEST1 PDO VSS NC NC NC VPCO VCKI FILO FILI PCO AV SS CLTV AVDD RF MIRR CLKO XLTO DATO CNIN SEIN CLOK VDD XLAT DATA XRST SENS MUTE SQCK SQSO EXCK SBSO SCOR WFCK EMPH DOUT MO2 C16M C4M FSTT XTSL XTAO XTAI VSS APTL APTR MNT0 MNT1 MNT2 MNT3 RADF C2PO RFCK GFS PLCK BIAS ASTI ASTO ASYE NC PSSL WDCK (48) VDD DATA (64) BCLK (64) DATA (64) BCLK (64) LRCK (64) GTOP XUGF LRCK (48) GND 200p GNDGND GND AV DD GND RAOV RFCK GFS PLCK UGFS STTP GNDGND GNDGND GND WFCK DOUT GND GNDGNDGNDGND TRACK-D GND FOCUS-D GND SLED-D GND SPIND-D GND SSTOP GND FE TE RF LDON VCC VCC GND GND GND GND GND GNDGNDGND GND GND GND GND GND GND GND TD FD SLD SPD C10 C23 C26 C28C27 R10 C35 R12 R11 R14R13 R4 R3 DFCT FOK C17 C15 C16 C14 C13 C11 C12 RV1 RV2 FE TE RF MIRR VC FGD FS3 FLB FEO FE- SRCH TGU TG2 AVCC TAO TA- DVCC CC2 CC1 FOK EFM ASY DFCT MIRR DGND SENS COUT XRST FDFCT FE FZC ATSC TDFCT TE TZC DVee RFO RFI CP CB SL+ SLO SL- FSET ISET SSTOP AVee DIRC LOCK CLK XLT DATA CXA1372Q CXD2500BQ Application Circuit Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party and other right due to same.

∗QFP080-P-1420-A PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 1.6g 23.9 ± 0.4 20.0 – 0.1 + 0.4 64 41 0.8 0.35 – 0.1 + 0.15 14.0 – 0.1 + 0.4 17.9 ± 0.4 16.3 0.1 – 0.05 + 0.2 2.75 – 0.15 + 0.35 0.8 ± 0.2 0.15 – 0.05 + 0.1 80PIN QFP (PLASTIC) M0.12 0.15 0° to 10° DETAIL A A SONY CODE EIAJ CODE JEDEC CODE PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING

42 ALLOY

M 80PIN QFP (PLASTIC) 20.0 – 0.1 + 0.4 24.0 ± 0.3 4164 1 24 0.8 0.35 – 0.1 + 0.15 ± 0.12 14.0 – 0.1 + 0.4 18.0 ± 0.3 0.15 – 0.05+ 0.1 16.6 0.1 – 0.05 + 0.2 0.7 ± 0.1 2.7 ± 0.1 3.1 MAX 0.15 0° to 10° 22.6 QFP-80P-L121 ∗QFP080-P-1420-AX 1.6g Package Outline Unit : mm CXD2500BQ CXD2500BQ CXD2500BQ —47—

∗QFP080-P-1420-AH 0.15 ± 0.05 1.45 0° to 10° 15° 15° 15° 15° DETAIL A 0.15 23.9 ± 0.2 ∗20.0 ± 0.2 0.35 ± 0.1 4 – 1.0 0.8 4 – 0.8 64 41 65 40 M0.15 C1.2 QFP 80PIN (PLASTIC) A + 0.20 1.6g NOTE: Dimension “∗” does not include mold protrusion. CXD2500BQ CXD2500BQ —48—