CXD2450R SONY | Alldatasheet

Document overview

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Technical content

Features

  • Base oscillation frequency 36.81MHz (2340f H )
  • Monitoring readout allowed
  • High-speed/low-speed electronic shutter function
  • Horizontal driver for CCD image sensor
  • Vertical driver for CCD image sensor
  • Signal processor IC system clock generation 1170fH , 780fH
  • Vertical/horizontal sync (SSG) timing generation

Applications

  • Digital still cameras
  • Personal computer image input Structure Silicon gate CMOS IC Pin Configuration Absolute Maximum Ratings
  • Supply voltage V DD VSS – 0.5 to +7.0 V VM VL – 0.5 to +26.0 V VH VL – 0.5 to +26.0 V VL VL – 0.5 to +26.0 V
  • Input voltage V I VSS – 0.5 to VDD + 0.5 V
  • Output voltage V O VSS – 0.5 to VDD + 0.5 V
  • Operating temperature Topr –20 to +75 °C
  • Storage temperature Tstg –55 to +150 °C Recommended Operating Conditions
  • Supply voltage VDD a, VDD b, VDD c, VDD d 3.0 to 3.6 V VM 0.0 V VH 14.5 to 15.5 V VL –5.0 to –6.0 V
  • Operating temperature Topr –20 to +75 °C Applicable CCD Image Sensors ICX098AK (Type 1/4 CCD) – 1 – E97819A9X Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. CXD2450R 48 pin LQFP (Plastic) 2 3 4 5 6 7 8 9 10 11 12 252627282930 36 35 34 313233 OSCI 3MCKV SS WEN TESTV DD XCLPOB V SS RG V DD V SS CLDFRIHRIHROFROEBCKSMSENSSKSSIV DD RST OSCO VL VSUB V2b V2a VM MCK DSGAT VDD 3 VDD 4 XSHP XSHD V SS 4 1/2MCK ID V SS XCLPDM XRS VDD 5 PBLK VH 3/2MCK * Groups of pins enclosed in the figure indicate sections for which power supply separation is possible.

– 2 – CXD2450R Block Diagram 3431 33 RG FRI HRI HRO FRO Latch Latch W EN XC LPD M XC LPO B ID PBLK Latch SSG 98 1012 13 1114 XSHP XSHD XRS 17 18 1916 20 O SC I 3M C K C LD 1/2M C K O SC O M C K 3/2M C K 23 1/2 6VD D 1 VD D 5 VD D 6 VSS1 VSS5 V D river H R I differential Pulse G enerator R egister SSI SSK SEN EBCKSM DSGAT TEST RST 2527 28 29 V2a V2b VSU B VH VM VL V SS4 V DD4 V SS2 V DD2 V SS3 V DD3

– 3 – CXD2450R Pin Description Pin No. 3MCK Vss1 WEN ID TEST V DD 1 XCLPOB V DD 2 RG Vss2 Vss3 V DD 3 XCLPDM V DD 4 XSHP XSHD XRS Vss4 PBLK 1/2MCK 3/2MCK V DD 5 RST V DD 6 SSI SSK SEN EBCKSM I O O I O O O O O O O O O O O I I I I I Internal main clock. (2340f H ) GND Memory write timing. Stop control possible using the serial interface data. Vertical direction line identification pulse output. Stop control possible using the serial interface data. IC test pin; normally fixed to GND. (With pull-down resistor) 3.3V power supply. (Power supply for common logic block) CCD optical black signal clamp pulse output. Stop control possible using the serial interface data. 3.3V power supply. (Power supply for RG) CCD reset gate pulse output. (780f H ) GND GND CCD horizontal register clock output. (780f H ) CCD horizontal register clock output. (780fH ) 3.3V power supply. (Power supply for H1/H2) CCD dummy signal clamp pulse output. 3.3V power supply. (Power supply for CDS system) CCD precharge level sample-and-hold pulse output. (780f H ) CCD data level sample-and-hold pulse output. (780fH ) Sample-and-hold pulse output for analog/digital conversion phase alignment. (780fH) GND Pulse output for horizontal and vertical blanking interval pulse cleaning. Horizontal direction pixel identification pulse output. Stop control possible using the serial interface data. System clock output for signal processing IC. (1170f H ) Stop control possible using the serial interface data. 3.3V power supply. (Power supply for common logic block) Internal system reset input. High: Normal status, Low: Reset status Always input one reset pulse after power-on. 3.3V power supply. (Power supply for common logic block) Serial interface data input for internal mode settings. Serial interface clock input for internal mode settings. Serial interface strobe input for internal mode settings. CHKSUM enable. (With pull-down resistor) High: Sum check invalid, Low: Sum check valid Symbol I/O Description

– 4 – CXD2450R FRO HRO HRI FRI CLD V SS 5 DSGAT MCK VM V2a VH V2b VSUB VL OSCO OSCI O O I I O I O O O O O O O I Vertical sync signal output. Stop control possible using the serial interface data. Horizontal sync signal output. Stop control possible using the serial interface data. Horizontal sync signal input. Vertical sync signal input. Clock output for analog/digital conversion IC. (780f H ) Phase adjustment in 60°units possible using the serial interface data. GND Control input used to stop drive pulse generation for CCD image sensor, sample-and-hold IC and analog/digital conversion IC. High:Normal status,Low:Stop status Controlled pulse can be changed using the serial interface data. System clock output for signal processor IC. (780fH ) GND (GND for vertical driver) CCD vertical register clock output. (Binary output) CCD vertical register clock output. (Binary output) CCD vertical register clock output. (Ternary output) 15.0V system power supply. (Power supply for vertical driver) CCD vertical register clock output. (Ternary output) CCD electronic shutter pulse output. –5.5V system power supply. (Power supply for vertical driver) Inverter output for oscillation. Inverter input for oscillation. Pin No. Symbol I/O Description

– 5 – CXD2450R

Electrical Characteristics

DC Characteristics (Within the recommended operating conditions) Item Supply voltage 1 Supply voltage 2 Supply voltage 3 Supply voltage 4 Supply voltage 5 Supply voltage 6 Supply voltage 7 Input voltage 1* *1 , *2 Input voltage 2 Input voltage 3*2 Output voltage 1 Output voltage 2 Output voltage 3 Output voltage 4 Output voltage 5 Output voltage 6 Output voltage 7 Output voltage 8 Output voltage 9 Output voltage VDD 2 VDD 3 VDD 4 VDD 1, VDD 5, VDD 6 VH VM VL RST, DSGAT, SSI, SSK, SEN, FRI, HRI EBCKSM TEST RG H1, H2 XSHP, XSHD, XRS, PBLK, XCLPDM 3/2MCK, MCK, CLD 1/2MCK XCLPOB, ID, WEN FRO, HRO VSUB V1, V3 V2a, V2b V DD a VDD b VDD c VDD d VH VM VL V IH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 VOH5 VOL5 VOH6 VOL6 VOH7 VOL7 VOH8 VOL8 VOM9 VOL9 VOH10 VOM101 VOM102 VOL10 3.0 3.0 3.0 3.0 14.5 –6.0 0.8V DD d 0.8VDD d 0.7VDD d VDD a – 0.8 VDD b – 0.8 VDD c – 0.8 VDD d – 0.8 VDD d – 0.8 VDD d – 0.8 VDD d – 0.8 VH – 0.25 VM – 0.25 VH – 0.25 VM – 0.25 3.3 3.3 3.3 3.3 15.0 0.0 –5.5 3.6 3.6 3.6 3.6 15.5 –5.0 0.2V DD d 0.2VDD d 0.3VDD d 0.4 0.4 0.4 0.4 0.4 0.4 0.4 VL + 0.25 VL + 0.25 VM + 0.25 VL + 0.25 V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V Feed current where IOH = –3.3mA Pull-in current where IOL = 2.4mA Feed current where IOH = –10.4mA Pull-in current where IOL = 7.2mA Feed current where IOH = –3.3mA Pull-in current where IOL = 2.4mA Feed current where IOH = –10.4mA Pull-in current where IOL = 7.2mA Feed current where IOH = –3.3mA Pull-in current where IOL = 2.4mA Feed current where IOH = –2.4mA Pull-in current where IOL = 4.8mA Feed current where IOH = –3.6mA Pull-in current where IOL = 7.2mA Feed current where IOH = –4.0mA Pull-in current where IOL = 5.4mA Feed current where IOM = –5.0mA Pull-in current where IOL = 10.0mA Feed current where IOH = –7.2mA Pull-in current where IOM = 5.0mA Feed current where IOM = –5.0mA Pull-in current where IOL = 10.0mA Pins Symbol Conditions Min. Typ. Max. Unit *1 These input pins do not have protective diodes on the internal power supply side. *2 These input pins have internal pull-down resistors. *3 The above table indicates the condition for 3.3V drive of low voltage drive blocks.

– 6 – CXD2450R Inverter I/O Characteristics for Oscillation (Within the recommended operating conditions) Item Logical Vth Input voltage Output voltage Feedback resistor Oscillation frequency OSCI OSCI OSCO OSCI, OSCO OSCI, OSCO LVth VIH VIL VOH VOL RFB f 0.7VDD d VDD d/2 500k VDD d/2 0.3VDD d VDD d/2 V V V V V Ω MHz Feed current where I OH = –6.0mA Pull-in current where IOL = 6.0mA VIN = VDD d or Vss Pins Symbol Conditions Min. Typ. Max. Unit Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment (Within the recommended operating conditions) Item Logical Vth Input voltage Input amplification 3MCK LVth V IH VIL VIN 0.7VDD d 0.3 VDD d/2 0.3VDD d V V V Vp-pfmax 50MHz sine wave Pins Symbol Conditions Min. Typ. Max. Unit 1 Input voltage is the input voltage characteristics for direct input from an external source. Input amplification is the input amplification characteristics in the case of input through capacitor. Switching Characteristics (VH = 15.0V, VM = GND, VL = –5.5V) Item TTLM TTMH TTLH TTML TTHM TTHL VCLH VCLL VCMH VCML 150 150 100 150 300 300 100 200 300 100 1.0 1.0 1.0 1.0 ns ns ns ns ns ns V V V V VL to VM VM to VH VL to VH VM to VL VH to VM VH to VL Symbol Conditions Min. Typ. Max. Unit 1 The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for measures to prevent electrostatic discharge. *2 For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1µF or more) between each power supply pin (VH, VL) and GND. Rise time Fall time Output noise voltage

– 7 – CXD2450R Switching Waveforms 10% 10% 90% 90% TTLH TTH L 90% TTLM 90% 10%10% TTM L TTLM TTM L 90% 90% 10%10% TTM H TTH M 90% 10% 90% 10% VSU B V1 (V3) V2a (V2b) VH VM VL VM VL VH VL Waveform Noise VH VL VC M LVC M H VC LLVC LH

– 8 – CXD2450R Measurement Circuit Serial interface data C 6 C 6 C 6 C 4 C 5 C 3R 2 R 1 R 1 R 1 R 1 C 1 C 1 C 1 C 2 C 2 C 2 +3.3V –5.5V +15.0V 3M C K R 1: 68W C 1: 450pF C 4: 30pF R 2: 15W C 2: 2200pF C 5: 100pF C 3: 500pF C 6: 10pF C 5 C 2 C 1 36 25 1 12

– 9 – CXD2450R AC Characteristics 1) AC characteristics between the serial interface clocks 0.8VD D d 0.8VD D d 0.2VD D d 0.2VD D d 0.2VD D d 0.8VD D d th1ts1 th2ts2 ts3 SSI SSK SEN SEN (Within the recommended operating conditions) Symbol ts1 th1 ts2 th2 ts3 SSI setup time, activated by the rising edge of SSK SSI hold time, activated by the rising edge of SSK SSK setup time, activated by the rising edge of SEN SSK hold time, activated by the rising edge of SEN SEN setup time, activated by the rising edge of SSK ns ns ns ns ns Definition Min. Typ. Max. Unit 2) Serial interface clock internal loading characteristics FR I H R I Exam ple: D uring recording drive m ode 0.2VD D dH R I V2a 0.8VD D d th4ts4 SEN 0.2VD D d V2a Enlarged view Note) Be sure to maintain a constantly high SEN logic level near the falling edge of HRI immediately before the readout period. Symbol ts4 th4 SEN setup time, activated by the falling edge of HRI SEN hold time, activated by the falling edge of HRI ns ns Definition Min. Typ. Max. Unit (Within the recommended operating conditions)

– 10 – CXD2450R (Within the recommended operating conditions) Symbol tpdPULSE Output signal delay, activated by the rising edge of SEN5 100 ns Definition Min. Typ. Max. Unit 5) Phase discrimination characteristics using FRI and HRI input 0.2VD D dFR I H R I tpd1 The field is discrim inated as an O D D field . 0.2VD D dFR I H R I tpd1 W hen the H R I logic level is low tpd1 after the falling edge of FR I The field is discrim inated as an EVEN field . W hen the H R I logic level is high tpd1 after the falling edge of FR I (Within the recommended operating conditions) Symbol tpd1 Field discrimination clock phase, activated by the falling edge of FRI1100 1300 ns Definition Min. Typ. Max. Unit 4) RST loading characteristics 0.8VD D d tw 1 0.2VD D dR ST (Within the recommended operating conditions) Symbol tw1 RST pulse width 35 ns Definition Min. Typ. Max. Unit 3) Serial interface clock output variation characteristics Normally, the serial interface data is loaded to the CXD2450R at the timing shown in 2) above. However, one exception to this is when the data such as SSGSEL and STB is loaded to the CXD2450R and controlled at the rising edge of SEN. For STB, see control data D62 to D63 STB in "Description of Operation". 0.8VD D d tpdPU LSE SEN O utput signal

– 11 – CXD2450R 7) Output timing characteristics using DSGAT tpD SG AT 0.2VD D d 0.2VD D dD SG AT H 1, H 2, R G , XSH P, XSH D , XR S, PBLK, XC LPD M , XC LPO B, C LD However, V2a, V2b and VSUB are fixed to the voltage level applied to the VH pin, and V1 and V3 are fixed to the voltage level applied to the VM pin. H1 and H2 load capacitance = 100pF, RG load capacitance = 20pF, XSHP, XSHD, XRS, PBLK, XCLPDM, XCLPOB and CLD load capacitance = 10pF (Within the recommended operating conditions) 6) FRI and HRI loading characteristics FR I, H R I M C K 0.2VD D d 0.8VD D d 0.2VD D d th5ts5 MCK load capacitance = 10pF (Within the recommended operating conditions) Symbol ts5 th5 FRI and HRI setup time, activated by the rising edge of MCK FRI and HRI hold time, activated by the rising edge of MCK ns ns Definition Miin. Typ. Min. Unit Symbol tpDSGAT Time until the above outputs go low after the fall of DSGAT 100 ns Definition Miin. Typ. Min. Unit 8) Output variation characteristics M C K W EN , ID 0.8VD D d tpd2 Symbol tpd2 Time until the above outputs change after the rise of MCK20 40 ns Definition Miin. Typ. Min. Unit WEN and ID load capacitance = 10pF (Within the recommended operating conditions)

– 12 – CXD2450R 9) H1 and RG waveform characteristics 0.9VD D b 0.1VD D b 0.9VD D b 0.1VD D b tfH 1trH 1 0.9VD D a 0.1VD D a trR G 0.9VD D a 0.1VD D a tfR G R G H 1 VDD b = 3.3V, Topr = 25°C, H1 and H2 load capacitance = 100pF, RG load capacitance = 20pF (Within the recommended operating conditions) Symbol trH1 tfH1 trRG tfRG H1 rise time H1 fall time RG rise time RG fall time ns ns ns ns Definition Min. Typ. Max. Unit 10) I/O pin capacitance Symbol C IN C OUT C I/O Input pin capacitance Output pin capacitance I/O pin capacitance pF pF pF Definition Min. Typ. Max. Unit (Within the recommended operating conditions)

– 13 – CXD2450R The CXD2450R basically loads and reflects the serial interface data sent in the above format in the readout portion at the falling edge of HRI. Here, readout portion specifies the horizontal interval during which V2a and V2b take the ternary level. There are two types of serial interface data: drive control data and phase adjustment data. Hereafter, these data are distinguished by referring to the former as control data and the latter as adjustment data. An example of the initialization data for the CXD2450R control data is shown below. This data is based on the Application Circuit Block Diagram, so care should be taken as there are some differences from the RST pin initialization data. Concretely, the internal SSG operates, the XCLPOB and ID pulses are generated, and the 3/2MCK pulse is stopped. This data shows the values when the EBCKSM pin is low and D64 to D71 CHKSUM is valid. Description of Operation Pulses output from the CXD2450R are controlled by the RST and DSGAT pins and by the serial interface data shown below. The details of control by the serial interface data and a description of operation are as follows. 00 01 02 03 04 05 06 07 08 09 10 11 58 59 60 61 62 63 64 65 66 67 68 69 70 71SSI SSK SEN MSB LSB D71 D70 D69 D68 D67 D66 D65 D64 D63 D62 D61 D60 D59 D58 D57 D56 MSB LSB D55 D54 D53 D52 D51 D50 D49 D48 D47 D46 D45 D44 D43 D42 D41 D40 MSB LSB D39 D38 D37 D36 D35 D34 D33 D32 D31 D30 D29 D28 D27 D26 D25 D24 MSB LSB D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D09 D08 MSB LSB D07 D06 D05 D04 D03 D02 D01 D00 1 0 1 0 1 1 0 1 0 0 0 0 0 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 The adjustment data does not normally need to be set. However, when adjustment is difficult due to the system configuration or for other reasons, the data considered most appropriate at that time should be set as the initialization data.

– 14 – CXD2450R Data D00 to D07 D08 to D15 D16 to D17 D18 to D25 D26 to D35 D36 to D47 D48 D49 to D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 to D61 D62 to D63 D64 to D71 CHIP CTGRY SMD Shut.FRM Shut.HD EXPOSE PSMT SSGSEL WENSEL CLPSEL IDSEL HMCKSEL TMCKSEL HMCKREV TMCKREV DSG STB CHKSUM Chip switching Category switching Electronic shutter mode setting Electronic shutter vertical interval setting Electronic shutter horizontal interval setting Recording exposure setting switching Drive mode switching Internal SSG operation switching WEN pulse operation switching XCLPOB pulse operation switching ID pulse operation switching 1/2MCK pulse operation switching 3/2MCK pulse operation switching 1/2MCK pulse reset polarity switching 3/2MCK pulse reset polarity switching Pulse generation control IC pin status control Check sum bit See D00 to D07 CHIP. See D08 to D15 CTGRY. See D16 to D35 Electronic shutter mode. See D16 to D35 Electronic shutter mode. See D16 to D35 Electronic shutter mode. All 0 All 0 All 0 All 0 All 0 All 0 All 0 All 0 All 0 All 0 Symbol Function Data = 0 Data = 1 When a reset OFF Monitoring OFF ON OFF OFF OFF ON Positive polarity Negative polarity ON Recording ON OFF ON ON ON OFF Negative polarity Positive polarity See D60 to D61 DSG table. See D62 to D63 STB table. See D64 to D71 CHKSUM. Control Data

– 15 – CXD2450R Detailed Description of Each Data D00 to D07 CHIP The serial interface data is loaded to the CXD2450R when D00 and D07 are 1. However, this assumes that either the EBCKSM pin is low and D64 to D71 CHKSUM is satisfied or the EBCKSM pin is high. D08 to D15 CTGRY Of the data provided to the CXD2450R by the serial interface, the CXD2450R loads D16 and subsequent data to the control data register side when D08 is 0, and to the adjustment data register side when D08 is 1. However, this assumes that the CXD2450R is selected by CHIP and that either the EBCKSM pin is low and D64 to D71 CHKSUM is satisfied or the EBCKSM pin is high. MSB LSB D07 D06 D05 D04 D03 D02 D01 D00 1 0 0 0 0 0 0 1 Function Loading to the CXD2450R MSB LSB D15 D14 D13 D12 D11 D10 D09 D08 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Function Loading to the control data register side Loading to the adjustment data register side D16 to D35 Electronic shutter mode The CXD2450R's electronic shutter mode can be switched as follows by SMD D16 to D17 . Handling of the data from D18 to D35 differs according to the mode, and is explained in detail below. D17 D16 Description of operation VSUB stopped mode High-speed/low-speed shutter mode HTSG control mode X The electronic shutter data is expressed as shown in the table below using Shut.HD as an example. MSB LSB D35 D34 D33 D32 D31 D30 D29 D28 D27 D26 0 1 1 1 0 0 0 0 1 1 fl fl fl 1 C 3 Shut.HD is expressed as 1C3h . Note that when SEN is shared with other ICs and identification is performed using CHIP-ID, the CXD2450R data must be positioned immediately before the load timing, that is to say at the very end. Note that the CXD2450R cannot apply both categories simultaneously during the same vertical interval. Also, care should be taken as the data is overwritten even if the same category is applied. [VSUB stopped mode] During this mode, the data from D18 to D35 is invalid. The shutter speed is 1/60 s during monitoring drive mode, and 1/30 s during recording drive mode.

– 16 – CXD2450R The CXD2450R does not distinguish between the high-speed shutter and low-speed shutter modes. The interval during which Shut.FRM and Shut.HD are specified together is the shutter speed. At this time, Shut.FRM controls the ternary level output at V2a and V2b, and Shut.HD controls the VSUB output. Concretely, when specifying high-speed shutter, Shut.FRM is set to 00h. (See the figure.) During low-speed shutter, or in other words when Shut.FRM is set to 01h or higher, the serial interface data is not loaded until this interval is finished. However, care should be taken as the vertical interval indicated here is set in 1/60s units when the drive mode is monitoring drive mode and 1/30s units during recording mode. For monitoring drive mode, care should be taken as the Shut.HD value has an offset. This is so that the CXD2450R can obtain basically the same exposure time for the same Shut.HD value during high-speed shutter independent of the drive mode. Formula for calculating the electronic shutter speed: [Shut.FRM/Shut.HD] (unit: µs) Monitoring drive mode: T = Shut.FRM*1.66834*10 4 + {(20Ch – Shut.HD)*780 + 447} *81.5*10–3 (000h ≤ Shut.HD ≤ 20Ch) Shut.FR M 01 01 01 Shut.H D -106h 00h 01h 00h 1A6h /LiteDiagLines /LiteDiagLines 1D D h 1A6hShut. H D W EN SM D Shut. FR M VSU B FR I V2a During monitoring drive mode/low-speed shutter mode Recording drive mode: 01h 00h 1A6h /LiteDiagLines /LiteDiagLines 1D D hShut. H D W EN SM D Shut. FR M VSU B FR I Shut.FR MShut.H D V2a During recording drive mode/low-speed shutter mode Symbol Data Description Shutter speed data (number of vertical intervals) specification Shutter speed data (number of horizontal intervals) specification D18 to D25 D26 to D35 Shut.FRM Shut.HD [High-speed/low-speed shutter mode] During this mode, the data has the following meanings.

– 17 – CXD2450R Shut.FRM 00h 00h 00h 00h 00h 00h 00h 00h 00h 20Ch 20Bh 209h 205h 1FDh 1EDh 1CEh 18Fh 16Fh 00h 01h 01h 02h 07h 09h 00h 00h 00h 107h* 20Ch 1D8h 20Ch 18Bh 109h 0D2h 083h 000h 1/60* 1/50*2 1/30*2 1/8*2 1/6*2 1/50*3 1/40*3 1/30*3 Shut.HD Calculation results (s)Shutter speed (s) Shut.FRM Calculation results (s)Shutter speed (s)Shut.HD Electronic shutter speed table [Shut.FRM/Shut.HD] *1 One VSUB pulse is generated for odd fields and two for even fields. *2 These are the settings during monitoring drive mode. *3 These are the settings during recording drive mode. Note) Input prohibited data: Monitoring drive mode 000h to 106h Recording drive mode and monitoring drive mode20Dh to 3FFh [HTSG control mode] During this mode, the data from D18 to D35 is invalid. The ternary level outputs at V2a and V2b are controlled, and the shutter speed is the value obtained by adding the shutter speed specified in the preceding vertical interval to the vertical period during which V2a and V2b are stopped as shown in the figure. VSU B FR I W EN 01 11 01SM D Vck V2a During HTSG control mode

– 18 – CXD2450R D51 PSMT 0: Driving is controlled in accordance with monitoring drive mode under the assumption that the vertical/ horizontal sync signals are input. 1: Driving is controlled in accordance with recording drive mode under the assumption that the vertical/ horizontal sync signals are input. See the timing charts for the vertical/horizontal sync signals in accordance with each mode. Note that when switching from monitoring drive to recording drive mode, the pixels decimated thus far must be cleaned. Concretely, this operation is supported by generating VSUB, but the CXD2450R facilitates this control by using D48 EXPOSE. (See the figure.) M onitoring FR I V2a W EN 00 00SM D VSU B 0000 0 0EXPO SE 10 1 0PSM T 00 R ecording M onitoringM onitoring Exposure tim e M ode Image of switching from monitoring drive mode to recording drive mode D48 EXPOSE 0: No operation 1: VSUB for recording exposure is generated. This control specification is such that one VSUB pulse is always generated during the horizontal interval immediately following the readout portion even if the electronic shutter speed is set to 1/60s (SMD = 00). This mode is closely related to D51 PSMT, so see D51 regarding the control. D52 SSGSEL 0: Internal SSG functions are stopped. 1: Internal SSG functions operate, and FRO and HRO are generated. When generation is stopped, these pulses are fixed low. D53 WENSEL 0: WEN is generated. 1: WEN generation is stopped. When generation is stopped, operation is the same as for D52 SSGSEL.

– 19 – CXD2450R No control performed CCD pulse stop control Sample-and-hold and analog/digital conversion IC pulse stop control CCD pulse and sample-and-hold and analog/digital conversion IC pulse stop control D60 to D61 DSG The CXD2450R can apply stop control to the CCD pulses and pulses for the sample-and-hold and analog/digital conversion ICs by setting the DSGAT pin low. Conversely, when the DSGAT pin is set high, the controlled pulses can be switched as follows using the serial interface data. D61 D60 Operating mode Here, CCD pulses refer to the H1, H2, RG, V1, V2a, V2b, V3 and VSUB pulses. Sample-and-hold and analog/digital conversion IC pulses refer to the XSHP, XSHD, XRS, PBLK, XCLPOB, XCLPDM and CLD pulses. See 7) Output timing characteristics using DSGAT of "AC Characteristics" for the stop control status of each pulse. D54 CLPSEL 0: XCPOB generation is stopped. 1: XCPOB is generated. When generation is stopped, operation is the same as for D52 SSGSEL. D55 IDSEL 0: ID generation is stopped. 1: ID is generated. When generation is stopped, operation is the same as for D52 SSGSEL. D56 HMCKSEL 0: 1/2MCK generation is stopped. 1: 1/2MCK is generated. When generation is stopped, operation is the same as for D52 SSGSEL. D57 TMCKSEL 0: 3/2MCK is generated. 1: 3/2MCK generation is stopped. When generation is stopped, operation is the same as for D52 SSGSEL. D58 HMCKREV 0: 1/2MCK reset when positive polarity. 1: 1/2MCK reset when negative polarity. D59 HMCKREV 0: 3/2MCK reset when negative polarity. 1: 3/2MCK reset when positive polarity.

– 20 – CXD2450R D62 to D63 STB This switches the operating mode as shown below. However, the IC pin status control bit is loaded to the CXD2450R and controlled immediately at the rise of the SEN input. Normal operating mode Sleep mode*1 Standby mode D63 D62 Symbol X CAMERA SLEEP STNBY Operating mode 1 Mode for the status which does not require CCD drive when playing back recorded data within the system. The pin status during each mode is shown in the table below. Pin 3MCK Vss1 WEN ID TEST V DD 1 XCLPOB V DD 2 RG Vss2 Vss3 V DD 3 XCLPDM V DD 4 XSHP XSHD XRS Vss4 PBLK 1/2MCK 3/2MCK V DD 5 ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT L L L L L L L L L L L L ACT ACT L L L L L L L L L L L L L Symbol CAMERA SLEEP STNB Y Note) ACT means that the circuit is operating. L indicates a low output level in the controlled status. Also, VH and VM indicate the voltage levels applied to VH (Pin 43) and VM (Pin 39), respectively, in the control status. Pin Symbol CAMERA SLEEP STNB Y RST V DD 6 SSI SSK SEN EBCKSM FRO HRO HRI FRI CLD Vss5 DSGAT MCK VM V2a VH V2b VSUB VL OSCO OSCI ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT L ACT ACT VM VM VH VH VH ACT ACT ACT ACT ACT ACT ACT L L ACT ACT L ACT L VM VM VH VH VH ACT ACT

– 21 – CXD2450R D64 to D71 CHKSUM This is the check sum bit. Apply the data shown below. MSB LSB D07 D06 D05 D04 D03 D02 D01 D00 D15 D14 D13 D12 D11 D10 D09 D08 D23 D22 D21 D20 D19 D18 D17 D16 D31 D30 D29 D28 D27 D26 D25 D24 D39 D38 D37 D36 D35 D34 D33 D32 D47 D46 D45 D44 D43 D42 D41 D40 D55 D54 D53 D52 D51 D50 D49 D48 D63 D62 D61 D60 D59 D58 D57 D56 +) D71 D70 D69 D68 D67 D66 D65 D64 fi CHKSUM 0 0 0 0 0 0 0 0 fi Reflected when the total is 0.

– 22 – CXD2450R FR I H R I VSU B 525 1 525 1 V2a V2b C C D O U T 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 490491492493494 1 2 1 2 3 4 5 6 7 8 1 PBLK XC LPO B XC LPD M W EN ID ∗ The num ber of VSU B pulses is determ ined by the serial interface data. This chart show s the case w here Shut.H D = 20C h and VSU B pulses are generated over the entire horizontal interval. ∗ In addition to the phase relationship betw een FR I and H R I show n above, the phases m ay also be offset by 1/2 horizontal interval. In any case, the readout interval is the 9th H R I fall counted from the fall of FR I. ∗ N ote that R and B of C C D O U T indicate lines containing these com ponents, and do not m ean the lead pixel com ponent of that line. R B R B R B R B B R B R B R Chart-1 Vertical Direction Timing Chart MODE (Base oscillation frequency: 2340fH ) Recording drive mode Applicable CCD image sensor: ICX098AK

– 23 – CXD2450R FR I H R I VSU B V2a 525 1 262 V2b C C D O U T 1 2 5 6 1 2 5 6 9 10 13 14 17 18 21 22 25 26 29 466469470473474 1 2 5 6 1 2 5 6 9 10 13 14 PBLK XC LPO B XC LPD M W EN ID 482485486489490493494 481482485486489477478 494490493 B R B R B R B R B RR B BB R R B R B R B R BR B R B R B R B R B R B R B RB R B R B R B ∗ The num ber of VSU B pulses is determ ined by the serial interface data. This chart show s the case w here Shut.H D = 20C h and VSU B pulses are generated over the entire horizontal interval. ∗ N ote that R and B of C C D O U T indicate lines containing these com ponents, and do not m ean the lead pixel com ponent of that line. Chart-2 Vertical Direction Timing Chart MODE (Base oscillation frequency: 2340fH ) Monitoring drive mode Applicable CCD image sensor: ICX098AK

– 24 – CXD2450R H 1 V2a V2b 44 80 56 92 68 104 0 50 100 550 H R I M C K 43 116 VSU B 10481 PBLK XC LPO B XC LPD M ID W EN 129 129118 21 40 ∗ The H R I of this chart is equivalent to H R I' of C hart-7. This H R I indicates the actual C XD 2450R load tim ing. ∗ The num bers at the output pulse transition points indicate the count at the M C K (780fH ) rise from the fall of H R I. ∗ VSU B is output at the tim ing show n above w hen specified by the serial interface data. ∗ The ID transition tim ing is synchronized w ith the rise of V3. ∗ W EN is output during the horizontal interval show n in C hart-1. The transition tim ing is the sam e as that for ID . ∗ R , G and B of H 1 indicate the output pixel color. In addition to the lines starting from R and G show n above, there are also lines starting from G and B. 56 92 GGG G GGG G G BBBBBBBBB RRR R RRR R R GGGGGGGGG RR GG R RRR R RRR R R GGGGGGGGG RRR R RRR R R GGGGGGGGG RRR R RRR R R GGGGGGGGG RRR R R GGGGGG R Chart-3 Horizontal Direction Timing Chart MODE (Base oscillation frequency: 2340fH ) Recording drive mode Applicable CCD image sensor: ICX098AK

– 25 – CXD2450R 0 50 100 550 H R I M C K H 1 V2a 44 80 VSU B 10481 43 116 PBLK XC LPO B XC LPD M ID W EN 129118 21 40 ∗ The H R I of this chart is equivalent to H R I' of C hart-7. This H R I indicates the actual C XD 2450R load tim ing. ∗ The num bers at the output pulse transition points indicate the count at the M C K (780fH ) rise from the fall of H R I. ∗ VSU B is output at the tim ing show n above w hen specified by the serial interface data. ∗ The ID transition tim ing is synchronized w ith the rise of V3. ID is reset low at this tim ing during the readout horizontal interval. ∗ W EN is output during the horizontal interval show n in C hart-1. The transition tim ing is the sam e as that for ID . 116 521 56 92 520 551 56 92 520 551 68 104 V2b Chart-4 Horizontal Direction Timing Chart MODE (Base oscillation frequency: 2340fH ) Recording drive mode (readout portion) Applicable CCD image sensor: ICX098AK

– 26 – CXD2450R PBLK XC LPO B XC LPD M ID W EN 129 129118 21 40 H 1 44 80 0 50 100 550 H R I M C K 43 116 VSU B 10481 62 98 V2a 50 68 86 104 GGG G GGG G G BBBBBBBBB RRR RRR R R GGGGGGG RR GG R RRR R RRR R R GGGGGGGG RRR R RRR R R GGGGGGG RRR R RRR R R GGGGGGG RRR R R GGGGG V2b 50 68 58 110 86 104 74 92 R G R G G G G G G G ∗ The H R I of this chart is equivalent to H R I' of C hart-7. This H R I indicates the actual C XD 2450R load tim ing. ∗ The num bers at the output pulse transition points indicate the count at the M C K (780fH ) rise from the fall of H R I. ∗ VSU B is output at the tim ing show n above w hen specified by the serial interface data. ∗ The ID transition tim ing is synchronized w ith the rise of V3. ∗ W EN is output during the horizontal interval show n in C hart-2. The transition tim ing is the sam e as that for ID . ∗ R , G and B of H 1 indicate the output pixel color. In addition to the lines starting from R and G show n above, there are also lines starting from G and B. Chart-5 Horizontal Direction Timing Chart MODE (Base oscillation frequency: 2340fH ) Monitoring drive mode Applicable CCD image sensor: ICX098AK

– 27 – CXD2450R 0 50 100 550 H R I M C K H 1 44 80 43 116 62 98 116 521 V2a 50 68 86 104 V2b VSU B 10481 PBLK XC LPO B XC LPD M ID W EN 129118 21 40 58 11074 92 50 68 86 104 520 551 ∗ The H R I of this chart is equivalent to H R I' of C hart-7. This H R I indicates the actual C XD 2450R load tim ing. ∗ The num bers at the output pulse transition points indicate the count at the M C K (780fH ) rise from the fall of H R I. ∗ VSU B is output at the tim ing show n above w hen specified by the serial interface data. ∗ The ID transition tim ing is synchronized w ith the rise of V3. ID is reset low at this tim ing during the readout horizontal interval. ∗ W EN is output during the horizontal interval show n in C hart-2. The transition tim ing is the sam e as that for ID . Chart-6 Horizontal Direction Timing Chart MODE (Base oscillation frequency: 2340fH ) Monitoring drive mode (readout portion) Applicable CCD image sensor: ICX098AK

– 28 – CXD2450R H R I H R I' ∗ H R I' indicates the H R I w hich is the actual C XD 2450R load tim ing. ∗ The 3/2M C K and 1/2M C K polarities can be inverted by the serial interface data. This chart indicates the status in w hich 3/2M C K is negative polarity and 1/2M C K is positive polarity. 3M C K 3/2M C K 1/2M C K C LD M C K H 1 H 2 R G XSH P XSH D XR S 43 116 Chart-7 High-speed Phase Timing Chart MODE (Base oscillation frequency: 2340fH ) Applicable CCD image sensor: ICX098AK

– 29 – CXD2450R Application Circuit Block Diagram 17 18 19 21 15 35 29282730372548471 CLD Signal Processor Block ID 1/2M C K W EN M C K FR I H R I H R O FR O XSHP XCLPOB XCLPDM PBLK XRS XSHD V2b VSU B H 1 H 2 R G C C D IC X098AK C C D O U T D R V O U T VR T VR B A/D C XD 2310AR D 0 to 9 10 TG C XD 2450R SSG EBCKSM TEST DSGAT RST OSCI OSCO CK C ontroller SEN SSK SSI V2a 3/2M C K S/H C XA2006Q V-D r Notes for Power-on supplies in the following order to prevent the VSUB pin of the CCD image sensor from going to negative potential. 20% 20% t2 ≥ t1 –5.5V 15.0V Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 30 – CXD2450R Package Outline Unit: mm SO N Y C O D E EIAJ C O D E JED EC C O D E PAC KAG E M ATER IAL LEAD TR EATM EN T LEAD M ATER IAL PAC KAG E W EIG H T EPO XY / PH EN O L R ESIN PLATIN G 42/C O PPER ALLO Y PAC KAG E STR U C TU R E 48PIN LQ FP (PLASTIC ) 9.0 ± 0.2 ∗ 7.0 ± 0.1 1 12 2536 48 (0.22) 0.18 – 0.03 + 0.08 0.5 ± 0.08 (8.0) 0.5 ± 0.2 0.127 – 0.02 + 0.05 0.1 ± 0.1 0.5 ± 0.2 A 1.5 – 0.1 + 0.2 0° to 10° D ETAIL A 0.2g LQ FP-48P-L01 Q FP048-P-0707 0.1 SO LD ER /PALLAD IU M N O TE: “∗” D im ensions do not include m old protrusion.