CXD2312

CXD2312R SONY | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 16

Technical content

Features

• Resolution: 9-bit ±0.5 LSB (D.L.E.)
• Maximum sampling frequency: 20MSPS
• Low power consumption: 130mW (at 20MSPS typ.) (Not including reference current)
• TTL compatible input
• Tri-state TTL compatible output (DV DD = 3.3V)
• Low input capacitance
• Reference impedance: 300Ω (typ.) Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage V DD 7V
• Reference voltage VRT, VRB V DD + 0.5 to VSS – 0.5 V
• Input voltage (analog) VIN VDD + 0.5 to VSS – 0.5 V
• Input voltage (digital) VIH, VIL VDD + 0.5 to VSS – 0.5 V
• Output voltage (digital) VOH , VOL VDD + 0.5 to VSS – 0.5 V
• Storage temperature Tstg –55 to +150 °C Recommended Operating Conditions
• Supply voltage AV DD , AVSS 5.0 ± 0.25 V DV DD , DVSS 3.0 to 5.25 V | DVSS – AVSS | 0 to 100 mV
• Reference input voltage VRB More than 1.8 V VRT to AV DD – 0.4 V
• Analog input V IN More than 1.8Vp-p
• Clock pulse width T PW 1 25 (min.) ns TPW 0 25 (min.) ns
• Operating ambient temperature Topr –20 to + 75 °C Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. 48 pin LQFP (Plastic)

– 2 – CXD2312R Block Diagram /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines + + DAC Coarse Comparate Encode Calibration Unit Fine Comparate Encode Fine Latch Coarse Correction Latch Timing Gen D0 (LSB) MINV LINV TESTMODE CAL SEL RESET VIN VRT VRT VRB VRB CLK CE OE 2627 28 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Sense Amp Sense Amp AV SS AV DD Auto Calibration Pulse Generator Pin Configuration CE OE CLK MINV LINV TESTMODE AV DD SEL DV SS RESET TIN TO TSTR AT VIN NC CAL TS AV SS AV SS DV DD NC NC DV SS AV SS VRBVRB NC NC NC VRT VRT AV SS AV SS AV DD AV DD D1 D2 D3 D4DV SS DV DD D5 D6 D7 D8D0 2 3 4 5 6 7 8 9 10 11 12 252627282930 36 35 34 313233 NC

– 3 – CXD2312R Pin Description DV DD DV SS Pin No Symbol Equivalent circuit Description 2 to 5 8 to 12 D0 to D8 7, 45 6, 16, 48 27, 28, 36, 43, 44 TO DV DD DV SS AV SS

17 SEL

22 CLK

15 RESET

D0 (LSB) to D8 (MSB) output. Test pin. TS = High: High impedance state Digital VDD . Digital VSS . Analog VSS . Calibration input pulse select after completion of the startup calibration. High : Internal pulse generation Low : External input Clock pin. Calibration pulse input. Calibration circuit reset and startup calibration restart. AV DD AV SS AV DD AV SS AV DD AV SS AV DD AV SS

– 4 – CXD2312R AV DD AV SS Pin No. Symbol Equivalent circuit Description

14 TIN

34, 35 VRB 23 OE CE24 Test signal input. Normally fixed to AVDD or AV SS . Reference top. Reference bottom. Test signal output. TS = High: High impedance state D0 to D8 output enable. Low : Output state High : High impedance state Chip enable. Low : Active state High : Standby state 29, 30 VRT 38 AT 42 TS

37 TSTR

Test signal input. Normally fixed to AV DD . Test signal input. Normally fixed to AVSS . AV DD AV SS AV DD AV SS

– 5 – CXD2312R Pin No. Symbol Equivalent circuit Description

20 LINV

39 V IN

Test mode. High : Output state Low : Output fixed Output inversion. High : D0 to D7 are inverted and output. Output inversion. High : D8 is inverted and output. Analog input.

19 TESTMODE

21 MINV

18, 25, 26 AV DD AV DD AV SS Analog VDD . AV DD AV SS AV DD AV SS AV DD AV SS

– 6 – CXD2312R Input signal voltage Digital output code MSB LSBStep VRT VRB 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 255 256 511 TESTMODE LINV MINV D0 D1 D2 D3 D4 D5 D6 D7 D8 P N P N P N P N P N P N P N P N P N P N P N P N P N P N P N P N P P N N Digital Output The following table shows the correlation between the analog input voltage and the digital output code (TESTMODE = 1, LINV, MINV = 0) The following table shows the output state for the combination of TESTMODE, LINV, and MINV states. P: Forward-phase output N: Inverted output Timing Chart 1 tDL tPW 1t PW 0 Clock Analog input Data output N – 3 N – 2 N N – 1 1.65V 1.65V (DVDD = 3.3V) 2.5V (DVDD = 5.0V) HOLD N HOLD N + 1 HOLD N + 2 HOLD N + 3 tSLtSH Timing Chart 2 High Impedance tPEZ tPZE Active Active 1.65V1.65V Output enable (OE) Data output 1.65V (DVDD = 3.3V) 2.5V (DVDD = 5.0V)

– 7 – CXD2312R Electrical Characteristics (Fc = 20MSPS, AVDD = 5V, DVDD = 3.3V, VRB = 2.0V, VRT = 4.0V, Ta = 25°C) Fc max Fc min IA DD IDDD IAST IDST IRT IRB BW C IN R REF EOT EOB VCAL 1 VCAL 2 VIH VIL AIH AIL IIH IIL IOH IOL IOZH IOZL tPEZ tPZE EL ED DG DP tDL tSH tSL Max. conversion rate Min. conversion rate Analog Digital Analog Digital Analog input band Analog input capacitance Reference resistance value (VRT – VRB) Tri-state output disable time Tri-state output enable time Integral non-linearity error Differential non-linearity error Differential gain error Differential phase error Output data delay Sampling delay 1.6 5.0 3.0 210 –30 –30 2.3 –10 4.0 3.5 1.7 7.5 5.5 300 8.0 2.5 1.0 ±0.5 ±0.3 1.0 0.3 0.5 1.8 1.0 1.0 10.0 8.0 390 0.8 ±1.0 ±0.5 Item Symbol Conditions Min. Typ. Max. Unit Supply current MSPS mA µA mA MHz pF W mV V V µA µA µA ns ns deg ns ns LSB mA Standby current Reference pin current Offset voltage Analog input current Startup calibration start voltage Digital input voltage Digital input current Digital output current Digital output current FIN = 1.0kHz triangular wave input FIN = 1.0kHz triangular wave input CE = High EOT = theoretical value-actual measured value EOB = actual measured value- theoretical value –1dB VOH = DVDD – 0.5V VOH = 0.4V VOH = DVDD VOL = 0V DV DD = max OE = AVSS DV DD = min Clock not synchronized for active fi high impedance Clock not synchronized for high impedance fi active NTSC 40 IRE mod ramp, Fc = 14.3MSPS AV DD = 4.75V to 5.25V C L = 20pF VIL= 0V VIH = DVDD VIN = 4V VIN = 2V OE = AVDD DV DD = max AV DD –A VSS VRT – VRB

– 8 – CXD2312R Application Circuit 1. Startup calibration + internal auto calibration Digital output 2.0V AV SS 4.0V 2.0V AV DD AV SSDV DD DV SS 4.0V AV DD AV SS AV DD AV SS DV SS Clock input CE OE CLK MINV LINV TESTMODE AV DD SEL DV SS RESET TIN TO TSTR AT VIN NC CAL TS AV SS AV SS DV DD NC NC DV SS AV SS VRBVRB NC NC NC VRT VRT AV SS AV SS AV DD AV DD D1 D2 D3 D4DV SS DV DD D5 D6 D7 D8D0 is all 0.1µF Sample & Hold 1 2 3 4 5 6 7 8 9 10 11 12 252627282930313233343536 AV DD NC SNR SFDR SNR SFDR Item Symbol Conditions Min. Typ. Max. Unit dB dB F IN = 100kHz FIN = 500kHz FIN = 1MHz FIN = 3MHz FIN = 7MHz FIN = 10MHz FIN = 100kHz FIN = 500kHz FIN = 1MHz FIN = 3MHz FIN = 7MHz FIN = 10MHz Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 9 – CXD2312R Application Circuit 2. Startup calibration + external sync calibration 2.0V AV SS Calibration pulse 4.0V 2.0V AV DD AV SSDV DD DV SS 4.0V AV DD AV SS AV DD AV SS DV SS Clock input CE OE CLK MINV LINV TESTMODE AV DD SEL DV SS RESET TIN TO TSTR AT VIN NC CAL TS AV SS AV SS DV DD NC NC DV SS AV SS VRBVRB NC NC NC VRT VRT AV SS AV SS AV DD AV DD is all 0.1µF Sample & Hold 252627282930313233343536 AV DD Digital output D1 D2 D3 D4DV SS DV DD D5 D6 D7 D8D0 1 2 3 4 5 6 7 8 9 10 11 12 NC Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 10 – CXD2312R Application Circuit 3. Only startup calibration (Less than supply voltage fluctuation range of AVDD = ±100mV and reference voltage fluctuation range of |VRT – VRB| = 200mV) 2.0V AV SS 4.0V 2.0V AV DD AV SSDV DD DV SS 4.0V AV DD AV SS AV DD AV SS DV SS Clock input CE OE CLK MINV LINV TESTMODE AV DD SEL DV SS RESET TIN TO TSTR AT VIN NC CAL TS AV SS AV SS DV DD NC NC DV SS AV SS VRBVRB NC NC NC VRT VRT AV SS AV SS AV DD AV DD is all 0.1µF Sample & Hold 252627282930313233343536 AV DD Digital output D1 D2 D3 D4DV SS DV DD D5 D6 D7 D8D0 1 2 3 4 5 6 7 8 9 10 11 12 NC Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 11 – CXD2312R 1. Calibration Function In order to achieve superior linearity, the CXD2312R has a built-in calibration circuit and a calibration pulse auto generation circuit which is used to execute a calibration circuit. Fig. 1 shows a block diagram of the calibration pulse generation circuit. AV DD OUT14 bit Counter 24 bit Counter CLR CLR CO CO CLR SEL CAL D Q 1CLK AV DD AV SS VRT VRB RESET CE Sence Amp 1 Sence Amp 2 Fig. 1. Calibration Pulse Generation Circuit (1) Startup Calibration Function Over 600 calibration pulses are needed to complete the initial calibration process when the power is first supplied to the IC. The startup calibration function automatically generates these pulses internally and completes the initial calibration process. The following five conditions must be satisfied to initiate the startup calibration function. a) The voltage between AV DD and AVSS is approximately 2.5V or more. b) The voltage between VRT and VRB is approximately 1V or more. c) The RESET pin (Pin 15) must is high. d) The CE pin (Pin 24) must is low. e) Condition b is met after condition a. Once all five of these conditions have been met, the calibration pulses are generated. The pulses are generated by counting 16 main clock cycles on a 14-bit counter and closing the gate when the carry-out occurs. Therefore, the time required for startup calibration after the above five conditions have been met is determined by the following formula: Startup calibration time = main clock cycle · 16 · 16,384 For example, if the main clock frequency is 14.3MHz, the time required for startup calibration is 18ms. When RESET = High and CE = Low AV DD VRT VRB [V] 2.5 0 [ t ] Sence Amp 1 Sence Amp 2 CLR

– 12 – CXD2312R (2) Auto Calibration Pulse Generation Function After startup calibration is completed, this function periodically generates calibration pulses so that calibration can be performed constantly without any need for input of calibration pulses from an external source. This function counts 16 main clock cycles on a 24-bit counter and uses the carry-out as the calibration pulse. The cycle of the calibration pulse generated in this fashion is as follows: Internal calibration pulse generation cycle = main clock cycle · 16 · 16,777,216 Therefore, if the main clock frequency is 14.3MHz, the calibration pulse cycle is approximately 19 seconds; since calibration is performed once every seven pulses, the calibration cycle is approximately 130 seconds. In order to use this function, the SEL pin (Pin 17) must be high. Note that this function cannot be used if fixing the lower bits in the calibration operation as described below will cause problems because this function is executed asynchronously without regard to the input signals. (3) External Calibration Pulse Input Function If the auto calibration function cannot be used, calibration can be performed in synchronization with the input signals when a calibration pulse is input from the CAL pin (Pin 41) by setting the SEL pin (Pin 17) low. 7clock 1clock or more CLK CAL D4 to D8 D0 to D3 10ns or more N – 3 N – 2 N – 1 N N + 1 N + 2 N + 3 N + 4 N + 5 N – 3 N – 2 N – 1 N N + 5 Fig. 2. Calibration Timing Chart Calibration starts when the falling edge of the pulse input to the CAL pin (Pin 41) is detected. Because the lower comparator is occupied for four clock cycles at this point, the previous lower data is held for four clock cycles after seven clock cycles since the rising edge of the clock cycle in which the falling edge of CAL was detected. Calibration can be performed outside of video intervals by using the sync signal, etc., to input the CAL signal. An example of this is shown below. (1) Inputting CAL every H-sync Input CLK CAL

– 13 – CXD2312R (2) Inputting CAL every V-sync Input CLK RESET CAL It is also possible to use only the startup calibration function by leaving the SEL pin (Pin 17) low and fixing the CAL pin (Pin 41) either high or low. Note that this method requires restriction of the fluctuation range of the supply voltage and the reference voltage. (4) Re-initiating the Startup Calibration Function The startup calibration function can be re-initiated after the power and reference voltage are supplied by using the CE pin (Pin 24) and the RESET pin (Pin 15). Particularly in cases where the riseup characteristics of the power supply and the reference voltage are unstable, it is possible to initiate startup calibration properly by connecting a CR and delaying startup until after power supply riseup. RESET AV DD AV SS R C [V] [ t ] RESET AV DD VRT VRB Fig. 3. Initiation of the Startup Calibration Function Using the RESET pin

– 14 – CXD2312R 2. Power supply To prevent the influence of noise, connect the power supply to a 0.1µF by-pass capacitor as near the device as possible. 3. DV DD supply generates a decreased amount of radiation noise but offers a decreased drive capacity. These two power supplies do not virtually differ in static and dynamic characteristics. Further, the High output level rises up to DV DD . 4. Reference input The voltage to be supplied to the reference pins must be driven by a buffer having a 10mA or more drive capacity. For supplied voltage stabilization, connect the buffer to a 0.1µF by-pass capacitor as near the pins as possible. 5. Latch-up Ensure that the AV DD and DVDD pins share the same power supply on a board to prevent latch-up which may be caused by power ON time-lag. 6. Board To obtain full-expected performance from this IC, be sure that the mounting board has a large ground pattern for lower impedance. It is recommended that the IC be mounted on a board without using a socket to evaluate its characteristics adequately.

– 15 – CXD2312R –20 0 25 50 75 –20 0 25 50 75 AV DD = 5.0V DV DD = 3.3V Fc = 1MHz CL = 20pF 100k 1M 10M AV DD = 5.0V DV DD = 3.3V Fc = 20MHz V IN = 2Vp-p Ta = 25°C 100k 1M 10M AV DD = 5.0V DV DD = 3.3V Fc = 20MHz V IN = 2Vp-p Ta = 25°C 100k 1M 10M AV DD = 5.0V DV DD = 3.3V Fc = 20MHz V IN = 2Vp-p Ta = 25°C –20 0 25 50 75 AV DD = 5.0V DV DD = 3.3V Fc = 1MHz –20 0 25 50 75 100k 1M 10M AV DD = 5.0V DV DD = 3.3V Fc = 20MHz V IN = 2Vp-p Ta = 25°C TSL TSH Supply current vs. Ambient temperature Fc = 20MHz fin = 1kHz triangular wave AV DD = 5.0V DV DD = 3.3V Output data delay vs Ambient temperature Input frequency vs. SNR Input frequency vs. Effective bits Input frequency vs. SFDR Sampling delay vs. Ambient temperature Maximum operating frequency vs. Ambient temperature fin = 1kHz triangular wave AV DD = 5.0V DV DD = 3.3V Input band Ambient temperature [°C] Ambient temperature [°C] Supply current [mA] Maximum operating frequency [MHz] Ambient temperature [°C] Ambient temperature [°C] Output data delay [ns] Sampling delay [ns] Input frequency [Hz] Input frequency [Hz] SNR [dB] SFDR [dB] Input frequency [Hz] Input frequency [Hz] Effective bits [bit] Output level [dB] Example of Representative Characteristics

– 16 – CXD2312R Package Outline Unit: mm SONY CODE EIAJ CODE JEDEC CODE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN PLATING 42/COPPER ALLOY PACKAGE STRUCTURE 48PIN LQFP (PLASTIC) 9.0 ± 0.2 ∗ 7.0 ± 0.1 1 12 2536 48 (0.22) 0.18 – 0.03 + 0.08 0.2g LQFP-48P-L01 LQFP048-P-0707 (8.0) 0.5 ± 0.2 0.127 – 0.02 + 0.05 A 1.5 – 0.1 + 0.2 0.1 SOLDER/PALLADIUM NOTE: Dimension “∗” does not include mold protrusion. 0.1 ± 0.1 0.5 ± 0.20° to 10° DETAIL A 0.13 M 0.5