CXD2301Q

CXD2301Q SONY | Alldatasheet

Document overview

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• PDF pages: 23

Technical content

Features

• Resolution: 8 bits ±1/2LSB (DL)
• Maximum sampling frequency: 30MSPS
• Low power consumption: 120mW (at 30MSPS typ.) (Including reference current)
• Standby function: 0.5mW power consumption in standby
• Amplifier functions: Built-in 3x amplifier (15MHz band), 2-input selector function provided
• Synchronous clamp function
• Clamp ON/OFF function
• Reference voltage self-bias circuit
• TTL compatible output
• 3V digital interface capability
• Single 5V or dual 4.75/3.3V power supplies
• Low input capacitance: 8pF
• Reference impedance: 330Ω (typ.)

Applications

Wide range of application fields where high-speed A/D conversion is required such as in the digital systems of TVs, VCRs, etc. Structure Silicon gate CMOS IC Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage V DD 7V
• Reference voltage V RT , VRB VDD +0.5 to VSS –0.5 V
• Input voltage (analog) VIN VDD +0.5 to VSS –0.5 V
• Input voltage (digital) VIH, VIL VDD +0.5 to VSS –0.5 V
• Output voltage (digital) VOH , VOL VDD +0.5 to VSS –0.5 V
• Storage temperature Tstg –55 to +150 °C Recommended Operating Conditions
• Supply voltage IDV SS –AV SS I 0 to 100 mV Single power supply AVDD , DVDD 5.0 ± 0.25 V Dual power supply AV DD 4.75 ± 0.25 V DV DD 3.3 ± 0.3 V
• Reference input voltage VRB 0 to V VRT to 2.2 V
• Analog input ADIN More than 1.2Vp-p
• Clock pulse width T PWI 16 (min) ns TPWO 16 (min) ns
• Operating ambient temperature Topr –20 to +75 °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. 32 pin QFP (Plastic)

– 2 – CXD2301Q Block Diagram Lower data latchUpper data latch TEST (DV SS ) SEL CE D0(LSB) D7(MSB) CLK DV DD DV SS VREF CLE CLP CCP AV SS AV SS AV SS AV SS AV SS AV DDADVADVOPOVIN2 VIN1 Clock generator Upper encoder (4 bit) Upper sampling comparator (4 bit) Lower encoder (4 bit) Lower sampling comparator (4 bit) Lower encoder (4 bit) Lower sampling comparator (4 bit) ADIN Reference supply VRB VRT R TS VBI R R ADV A/D Converter Block 27 25 30 21 22 26 3220624

– 3 – CXD2301Q Pin Description Reference voltage (bottom) Connect to AVSS for normal use. When another external voltage is input, connect an external 0.1µF capacitor and retain a 1.5V differential compared to the top reference voltage. Reference voltage (top) By setting V RB to AVSS , outputs approximately 1.5V. Connect only a 0.1µF external by-pass capacitor for normal use. When another external voltage is input, it must be 2.2V or lower. 23 1 RrefR TS AVSS AVDD Pin No. Symbol 1V RB

23 V RT

2, 3, 7, 28, 31 AV SS

4 SEL

19 TEST

6 CLE

18 CLK

20 CLP

17 DV DD

Equivalent circuit Description Analog GND. Switches the input of the 3x amplifier. When SEL is at Low level, VIN1 is selected. When SEL is at High level, VIN2 is selected. Standby function ON/OFF selector. In standby state when High. Fix to VSS for normal use. When CLE = Low: Clamp functiion is enabled. When CLE = High: Clamp function is disabled, and only the normal A/D converter function is enabled. Clock input Inputs the clamp pulse to Pin 20 (CLP). Clamps the High interval signal voltage. Digital GND. D 7 (MSB) to D0 (LSB) output Outputs Low level in standby. In operation, the phase of D 7 to D0 output is inverted against the phase of ADIN. 5V or 3.3V AVSS DV SS AVDD AVSS AVDD CE Di

– 4 – CXD2301Q Short Pins 21 and 22, and connect 0.1µF external capacitor. AVSS AVDD CE AVSS AVDD AVDD AVSS AVSS AVDD 200 R R11 R12

21 ADV

22 ADV

Clamp reference voltage input. Clamps so that the reference voltage and the clamp interval ADIN input signal are equal. The reference voltage is more than 0.5V. 24 V REF Amplifier input pin. Biased internally at 1.9V (when AV DD = 5V) or at 1.8V (when AVDD = 4.75V). When in standby as well. When SEL is at Low level, V IN1 is selected for input; When SEL is at High level, V IN2 is selected for input. VIN1 VIN2 5V or 4.75V26 AV DD Pin No. Symbol Equivalent circuit Description

– 5 – CXD2301Q A/D converter block analog input. AVDD AVSS

29 ADIN

Amplifier output. The phase of this output is inverted against the phase of V IN1, 2. In standby mode, it becomes high-impedance output condition. AVSS AVDD

3030 OPO

Integrates the clamp control voltage. The relationship between the CCP voltage variation and the ADIN voltage is positive phase. AVDD AVSS 3232 TEST CE SEL D1 D2 D3 D4 D5 D6 D7 D8 L L H H H L H L H H X X X L H D1 D2 D3 D4 D5 D6 D7 D8 LLLLLLLL TEST mode HLHLHLHL LHLHLHLH CCP

• The following table shows the status of the digital output pins when the TEST pin is used with the CE and SEL pins. Pin No. Symbol Equivalent circuit Description

– 6 – CXD2301Q Digital Output The following table shows the correlation between the ADIN input voltage and the digital output code. Take notice that the phase of ADIN input signal voltage is inverted against the phase of the digital output. ADIN Input signal voltageStep Digital output code MSB LSB VRT V RB 127 128 255 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 : Indicates point at which input signal is sampled Td TPW 1 TPW 0 Clock 2V ADIN input Data output N N+1 N+2 N+3 N+4 N–3 N–2 N+1 N N–1 Fig. 1. Timing Chart

– 7 – CXD2301Q

Electrical Characteristics

(1) When using a single power supply(Fc = 30MSPS, AVDD = DVDD = +5V, VRB = 0V, VRT = 1.5V, Ta = 25°C) Item Symbol Conditions Min. Typ. Max. Unit Supply current Standby supply current Max. conversion rate Min. conversion rate ADIN input band (at –1dB) ADIN input capacitance Reference resistance (VRT to VRB ) Self bias Offset voltage Digital input voltage Digital input current Digital output current Output data delay Integral nonlinearity error Differential nonlinearity error Differential gain error Differential phase error Aperture jitter Sampling delay Clamp offset voltage Clamp pulse delay Amplifier gain V IN1 and VIN2 bias voltage VIN1 and VIN2 input resistance VIN1 and VIN2 input capacitance IAD + IDD ISTB Fc max Fc min BW C ADIN R REF VRT EOT EOB VIH VIL IIH IIL IOH IOL TDL EL ED DG DP taj tsd Eoc tcpd V BI1, 2 R I1, 2 C I1, 2 Fc = 35MSPS NTSC ramp wave input CE = DVDD VIN = 0 to 1.5V fIN = 1kHz ramp VIN = 0.75V + 0.07Vrms VRB = AVSS VIH = VDD VIL= 0V VOH = VDD –0.5V VOL = 0.4V With TTL 1gate and 10pF load Fc = 30MSPS V IN = 0 to 1.5V Fc = 30MSPS VIN = 0 to 1.5V NTSC 40IRE mod ramp, Fc = 14.3MSPS VREF = 0.5V VREF = 1.5V DC to 15MHz When open 230 1.38 –40 +25 3.5 –1.1 3.7 –40 8.5 130 330 1.52 –20 +45 –2.5 6.5 +0.5 ±0.3 0.5 +20 –20 9.5 1.9 200 0.5 440 1.66 +65 0.5 +1.3 ±0.5 +40 10.5 mA µA MSPS MHz pF Ω V mV V µA mA ns LSB LSB deg ps ns mV ns dB V kΩ pF DV DD = max. DV DD = min. VADIN = DC, PWS = 3µsec

– 8 – CXD2301Q Item Symbol Conditions Min. Typ. Max. Unit Analog supply current Digital supply current Standby supply current Max. conversion rate Min. conversion rate ADIN input band (at –1dB) ADIN input capacitance Reference resistance (VRT to VRB ) Self bias Offset voltage Digital input voltage Digital input current Digital output current Output data delay Integral nonlinearity error Differential nonlinearity error Differential gain error Differential phase error Aperture jitter Sampling delay Clamp offset voltage Clamp pulse delay 3x amplifier gain V IN1 and VIN2 bias voltage VIN1 and VIN2 input resistance VIN1 and VIN2 input capacitance IAD IDD ISTB Fc max Fc min BW C ADIN R REF VRT EOT EOB VIH VIL IIH IIL IOH IOL TDL EL ED DG DP taj tsd Eoc tcpd V BI1, 2 R I1, 2 C I1, 2 Fc = 30MSPS NTSC ramp wave input Fc = 30MSPS NTSC ramp wave input CE = DVDD VIN = 0 to 1.5V fIN = 1kHz ramp VIN = 0.75V + 0.07Vrms VRB = AVSS VIH = DVDD VIL= 0V VOH = VDD –0.5V VOL = 0.4V With TTL 1gate and 10pF load Fc = 30MSPS V IN = 0 to 1.5V Fc = 30MSPS VIN = 0 to 1.5V NTSC 40IRE mod ramp, Fc = 14.3MSPS VREF = 0.5V VREF = 1.5V DC to 15MHz When open 230 1.44 –40 +25 2.5 –1.1 3.7 –40 8.5 130 330 1.52 –20 +45 –2.5 6.5 +0.5 ±0.3 0.5 +20 –20 9.5 1.8 200 0.5 440 1.6 +65 0.5 +1.3 ±0.5 +40 10.5 mA mA µA MSPS MHz pF Ω V mV V µA mA ns LSB LSB deg ps ns mV ns dB V kΩ pF DV DD = max. DV DD = min. VIN = DC, PWS = 3µsec (2) When using a dual power supply(Fc = 30MSPS, AVDD = 4.75V, DVDD = 3.3V, VRB = 0V, VRT = 1.5V, Ta = 25°C)

– 9 – CXD2301Q Application Circuit (1) When using the internal amplifier a) Clamp usage example (using self bias) 1718192021222324 2 3 4 5 6 7 81 GND (digital)GND (analog) 0.01µ 0.1µ 10p 0.1µ 0.1µ VIDEO IN VREF 20k +4.75V 0.1µ 0.1µCLAMP PULSE IN CLOCK IN +3.3V 0.1µ ACO4 LATCH * CK Q * Although the ADC sampling clock latches the clamp pulse, it is not needed for basic clamp operation. However, depending on the relationship between the sampling frequency and the clamp pulse frequency, a small beat might be generated as V sag. The latch circuit is valid at this time.

– 10 – CXD2301Q b) Digital clamp usage example (using self bias) 2 3 4 5 6 7 81 GND (digital)GND (analog) 0.1µ VIDEO IN2 +4.75V 0.1µ CLOCK IN +3.3V 0.1µ ACO4 Subtracter, Comparator, etc. Clamp Level Setting data DAC, PWM, etc. High impedance for all information outside the clamp interval 0.1µ 0.1µ 0.1µ VIDEO IN1 1718192021222324 * The relationship between the CCP voltage (Pin 32) variation and the ADIN voltage variation is positive phase. * ∆ADIN/∆VCCP = 3.0 (fs = 30MSPS)

– 11 – CXD2301Q c) When not using the clamp GND (digital) GND (analog) 0.1µ 10p 0.1µ 0.1µ VIDEO IN +4.75V 0.1µ CLOCK IN +3.3V (digital) 0.1µ ACO4 0.1µ 1718192021222324 2 3 4 5 6 7 81 +3.3V (digital) 0.1µ

– 12 – CXD2301Q (2) When not using the internal amplifier a) Clamp usage example GND (digital)GND (analog) 10p 0.1µ VIDEO IN # +4.75V (analog) 0.1µ CLAMP PULSE IN CLOCK IN +3.3V (digital) 0.1µ ACO4 LATCH * CK Q 0.01µ 10µ 0.1µ 17181920212223 2 3 4 5 6 7 81 +4.75V 20k * Although the ADC sampling clock latches the clamp pulse, it is not needed for basic clamp operation. However, depending on the relationship between the sampling frequency and the clamp pulse frequency, a small beat might be generated as V sag. The latch circuit is valid at this time. # Take care that the phase of ADIN input is inverted against the phase of the digital output, because the use of the built-in inverting amplifier is standard. (Refer to “Digital Output” on page 6.)

– 13 – CXD2301Q b) Digital clamp usage example Subtracter, Comparator, etc. Clamp Level Setting data DAC, PWM, etc. High impedance for all information outside the clamp interval GND (digital)GND (analog) 10p 0.1µ VIDEO IN # +4.75V (analog) 0.01µ 10µ 0.1µ CLOCK IN {3.3V (digital) 0.1µ ACO4 0.1µ 1718192021222324 2 3 4 5 6 7 81 * The relationship between the CCP voltage (Pin 32) variation and the ADIN voltage variation is positive phase. * ∆VADIN /∆VCCP = 3.0 (fs = 20MSPS) c) When not using the clamp GND (digital) GND (analog) 10p VIDEO IN # +4.75V (analog) 0.1µ CLOCK IN +3.3V (digital) 0.1µ ACO4 0.1µ +3.3V (digital) 0.1µ 1718192021222324 2 3 4 5 6 7 81 # Take care that the phase of ADIN input is inverted against the phase of the digital output, because the use of the built-in inverting amplifier is standard. (Refer to “Digital Output” on page 6.)

– 14 – CXD2301Q Example of Representative Characteristics Input frequency of VIN2 vs. Crosstalk VIN2→ VIN1 VDD =4.75V VIN=150mVrms VIN1=GND –10 –80 –20 –30 –40 –50 –60 –70 Crosstalk [dB] fIN–Input frequency [MHz] 1 5 10 50 Sampling frequency vs. Current consumption fIN=NTSC ramp wave VIN=150mVrms fs–Sampling frequency [MHz] 0.1 0.5 1 51 0 Current consumption [mA] Input frequency vs. Current consumption VDD =5V, Input waveform is ramp wave V IN=150mVrms Current consumption [mA] fIN–Input frequency [MHz] 0.1 0.5 1 50 51 0

– 15 – CXD2301Q ANALOG CIRCUIT MOUNT PORTION ANALOG INPUT INTERFACE ANALOG CIRCUIT MOUNT PORTION V REF DAC SOCKET DATA LATCH CLOCK BUFFER OSC DIGITAL CIRCUIT MOUNT PORTION 8V IN V OUT SW CLOCK OE SEL SYNC CLE BLK Unnecessary at self bias use –5V+5VGND DACSOCKET 8bit ADC and DAC Evaluation Board Evaluation boards are available for the high speed, low power consumption CMOS converters, CXD2301Q (8-bit 30MHz A/D) and CXD1171M (8-bit 40MHz D/A). The evaluation board is composed of a main board common to either type, to which is added sub board D2301Q or sub board D1171M. The junction is made through a socket. To the main board are mounted an input interface, clock buffer and latch. To each of the sub boards is mounted CXD2301Q and CXD1171M respectively. Those IC's are mounted according to recommended print patterns designed to provide maximum performance to the A/D and D/A converters. Block Diagram Characteristics

• Resolution 8bit
• Maximum conversion rate 30MHz
• Digital input level CMOS level
• Supply voltage ±5.0V (Single +5V power supply possible at self bias use) Supply Voltage Item Min. Typ. Max. Unit +5V –5V 165 20 mA Clock Input CMOS compatible Pulse width T CW1 16ns (min) TCW0 16ns (min)

– 16 – CXD2301Q Analog Output(CXD1171M) (RL > 10k Ω ) Item Min. Typ. Max. Unit Analog output 1.8 2.0 2.1 V Item Symbol Min. Typ. Unit Clock High time Clock Low time Clock Delay Data delay AD Data delay (latch) Settling time Hold time Data delay DA T PW1 TPW0 Tdc tPD (AD) tDD tS th tPD (DA) Max. ns ns ns ns ns ns ns ns Output Format (CXD2301Q) The table shows the output format of AD Converter Analog input voltage Step Digital output code MSB LSB VRT V RB 127 128 255 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Timing Chart tPD (DA) tS th tDD tPD(AD) Tdc TPW1 TPW0 Analog input External clock AD clock AD output Latch output DA input DA clock DA output

– 17 – CXD2301Q CMOS ADC/DAC Peripheral Circuit Board (Main Board) 3.3k VR4 20k AVDD (16R)0.1 200 (R) V OUT OUTPUT GAIN ADJUST Q2VR2 510R6 510 510 Q1VR1 VRB ADJUST VRT ADJUST AVSS 0.01 SW2 0.01 SW3VR3 20k CLAMP VOLTAGE ADJUST AVDD AVSS 75C2 10µ C1 470µ 100k VIDEO INPUT 47µ CLK DV SS DV DD CLEAR CLK DV SS DV DD CLEAR DV SS DV DD 0.01µ 0.01µ 0.01µ SW1 CLE SEL OE BLK SYNC EXTERNAL CLOCK INPUT OSC SWITCH EXT/INT VR5 20k R10 47µ SYNC INT OSC OUT DV SS DV DD (R IN=75µ) GND +5V –5V DVDD AVDD 0.01 DV DD DV SS DV DD DV SS 1213 24 1 NC NC AVSS AVSS IREF VREF AVDD AVDD IO IO NC DV DD NC DV SS CLK BLK 1415 28 1 PW NC NC V RT VRTS AVDD AVDD VIN AVSS AVSS VRBS VRB VREF CLE SYNC SEL CLK DV DD DV SS OE 74S04 OR 74HC04 (INV BUFFER) 74S174 (LATCH) 74S174 (LATCH)

– 18 – CXD2301Q CMOS ADC/DAC Peripheral Circuit Board (Sub Board) 0.1µ NC NC DV DD CLK CLP NC NC NC NC AV DD AVDD VIN AVSS AVSS NC NC 1000p 0.1µ 0.1µ 0.01µ 1718192021222324 2 3 4 5 6 7 81 CXD2301Q NC DV SS CLE VREF CXD1171M NC DV SS BLK CLK NC DV DD NC AVSS IREF VREF AVDD AVDD IO IO NC AVSS

– 19 – CXD2301Q List of Parts resitance transistor R1 100k Q1 2SC2785 R2 75 Ω Q2 2SC2785 R3 75 Ω Q3 2SC2785 R4 510 Ω R5 510 Ω ic R6 510 Ω IC1 74S174 R7 R = 200 IC2 74S174 R8 18R ≈ 3.3k IC3 74S04 R9 75 Ω R10 75 Ω oscillator VR1 2k OSC VR2 2k VR3 20k others VR4 20k connector BNC071 VR5 20k SW AT1D2M3 capacitance C1 470µF/6.3V (chemical) C2 10µF/16V (chemical) C3 0.01µF C4 0.01µF C5 0.1µF C6 0.1µF C7 0.1µF C8 0.1µF C9 0.1µF C10 0.1µF C11 47µF/10V (chemical) C12 47µF/10V (chemical) C13 47µF/10V (chemical) C14 0.1µF Adjustment 1. Vref adjustment (VR1, VR2) Adjustment of A/D converter reference voltage. V RB is adjusted through VR1 and VRT through VR2. When self bias is used, there is no need for adjustment. Reference voltage is set through self bias at delivery. 2. Setting of clamp reference voltage (VR3) Clamp reference voltage is set. 3. DAC output full scale adjustment (VR4) Full scale voltage of D/A converter output is adjusted at the PCB shipment, the full scale voltage is adjusted to approx. 2V. 4. Sync (clamp) pulse interface (VR5) This adjustment enables interface with the signal generator and others at the PCB shipment, adjustment is performed to obtain a threshold of approx. 2.5V to an H sync of 0 to 5V.

– 20 – CXD2301Q 5. OE, SEL, Sync, BLK, CLE, Sync INT The following pins are set on the main board: Sync, CLE, Sync INT (CXD2301Q) and BLK (CXD1171M), OE, SEL (not used). For the pins function, refer to the specifications. The difference between Sync pin and Sync INT pin is that you input a pulse above 3.5Vp-p to Sync INT pin. The pulse threshold is set through VR5. For input through Sync pin, pulse is input at TTL or CMOS level. In this case cut off the junction line between Sync pin and Sync INT pin. At the PCB shipment the main board pins are set as follows. 6. Clamp pulse input method The clamp pulse is directly input to CXD2301Q as show in Application Circuit examples (1) and (2). Use the direct input that is set at the PCB shipment. Points on the PCB Pattern Layout 1. Set the layout not to have Digital current flow into Analog GND (Part 1). (For 1, see P.17 Component side diagram.) 2. At CXD2301Q sub board, C 2 and C3 capacitors serve the important role of bringing out CXD2301Q's full performance. These are over 0.1µF (ceramic) capacitors with good high frequency characteristics. Layout as close to the IC as possible. 3. Analog GND (AV SS ) and Digital GND (DVSS ) are on a common voltage and power source. Keeping ADC's DV SS (Part 2) as close as possible to the voltage supply source will provide better results. That is, a layout where ADC is close to the voltage supply source, is recommended. (For 2, see P.17 Component side diagram.) 4. ADC samples analog signals at the clock falling edge point. Accordingly clocks supplied to ADC should not have any jitter. 5. The PCB layout shows ADC and DAC's Analog GND independently from the voltage supply source. The layout aims at providing an independent evaluation of ADC and DAC, as much as possible. On the actual board, common use will not cause any problems.

– 21 – CXD2301Q Notes on Operation 1. Reference voltage By shorting VRT and VRTS , VRB and VRBS , CXD2301 has the self bias function that generates VRT = about 2.6V and VRB = about 0.5V. On the PCB, either self bias or the external reference voltage can be selected depending on the junction method of the jumper line. At shipment from the factory, reference voltage is provided in self bias. Also, to provide external reference voltage, adjust the dynamic range (V RT – VRB ) to above 1.8Vp-p. 2. Clock input There are 2 modes for the PCB clock input. 1) Provided from the external signal generator (External clock) 2) Using the crystal oscillator (built-in clock driver). (Internal clock) The 2 modes are selected using the switch on the PCB. 3. The 2 Latch IC's (74S174) are not absolutely necessary for the evaluation of ADC and DAC. That is, operation will still be normal if ADC output data is directly input to DAC input. However, as ADC output data is hardly ever D/A converted without executing Digital signal processing, it was mounted to indicate an example layout of Digital signal processing IC. When the ADC output data is used, use the output of the latch IC. 4. When clamp is not used Turning CLE to H will set OFF the clamp function. In this case, the DC element is cut off by means of C 2 on the main board and DC voltage on the ADC side of C2 turns to about (VRT + VRB ). To transfer DC elements of input signals, short C2. At that time, it is necessary to bias input signals, but keeping R2 open, Q3 can also be used as buffer. Use the open space for the bias circuit. 5. Clamp pulse latch On the evaluation board, the clamp pulse is latched with ADC sampling CLK and then input to the CLP pin. This is to minimize Vsag due the synchronizing of noise and clamp pulse beat elements with GND sampling clock around ADC. If there are no problems with Vsag, latch is not necessary. 6. Peripheral through hole There is a group of through holes on the Analog input, output and Logic. These are to be used when mounting additional circuits to the PCB. Use when necessary. The connector hole on DAC part is used to mount the test chassis and the mount jack.

– 22 – CXD2301Q Silk Side Component Side Soldering Side (Diagram seen from the component side)

– 23 – CXD2301Q Package Outline Unit: mm SONY CODE EIAJ CODE JEDEC CODE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING

42 ALLOY

32PIN QFP (PLASTIC) 9.0 ± 0.2 (8.0) 0.1 – 0.1 + 0.2 + 0.35+ 0.3 0.500.127 – 0.05 + 0.1 0° to 10° 0.8 0.3 – 0.1 + 0.15 1 8 932 1724 M± 0.12 0.1 0.2g QFP-32P-L01 ∗QFP032-P-0707-A