CXD1177Q

CXD1177Q SONY | Alldatasheet

Document overview

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• PDF pages: 13

Technical content

Features

• Resolution 8-bit
• Maximum conversion speed 40MSPS
• YC 2-channel input/output
• Differential linearity error ±0.3 LSB
• Low power consumption 160 mW (200 Ω load at 2 Vp-p output)
• Single 5 V power supply
• Low glitch noise
• Stand-by function Structure Silicon gate CMOS IC 8-bit 40MSPS YC 2-channel D/A Converter 32 pin QFP (Plastic) CXD1177Q

— 2— CXD1177Q Block Diagram Pin Configuration 2LSB'S C U R R EN T C ELLS 6M SB'S C U R R EN T C ELLS C LO C K G EN ER ATO R LATC H ESD EC O D ER 2LSB'S C U R R EN T C ELLS 6M SB'S C U R R EN T C ELLS C LO C K G EN ER ATO R LATC H ESD EC O D ER C U R R EN T C ELLS (FO R FU LL SC ALE) BIAS VO LTAG E G EN ER ATO R D EC O D ER D EC O D ER D VD D AVD D YO YO YC K AVSS D VSS C O C O C C K VG VR EF IR EF VB (LSB) Y0 (M SB) Y7 (LSB) C 0 C 1 C 2 C 3 C 4 C 5 C 6 (M SB) C 7 BLK C E 1718192021222324 2 3 4 5 6 7 81

25 C 7

— 3— CXD1177Q Pin Description and I/O Pins Equivalent Circuit 1 to 8 9 to 16 Y0 to Y7 C0 to C7 BLK VB YCK CCK DV SS AV SS CE I I O I I Pin No. Symbol I/O Equivalent circuit Description D VD D D VSS to D VD D D VSS D VD D D VSS D VD D D VD D D VSS D VD D D VSS Digital input Y0 (LSB) to Y7 (MSB) C0 (LSB) to C7(MSB) Blanking input. This is synchronized with the clock input signal for each channel. No signal at “H” (Output 0 V). Output condition at “L”. Connect a capacitor of about 0.1 µF. Clock input. Digital ground Analog ground Chip enable input. This is not synchronized with the clock input signal. No signal (Output 0 V) at “H” and minimizes power consumption.

— 4— CXD1177Q IREF VREF VG AV DD CO YO CO YO DV DD O I O O Pin No. Symbol I/O Equivalent circuit Description AVSS AVSS AVD D AVD D AVSS AVD D AVD D AVD D AVSS AVD D AVSS Connect a resistance 16 times “RIR” that of output resistance value “ROUT ”. Set full-scale output value. Connect a capacitor of about 0.1 µF. Analog power supply Current output. Voltage output can be obtained by connecting a resistance. Inverted current output. Normally dropped to analog ground. Digital power supply

— 5— CXD1177Q Electrical Characteristics (FCLK =40 MHz, AVDD =DV DD =5 V, ROUT =200 Ω , VREF =2.0 V, Ta=25 °C) Full-scale voltage for each channel*1 Full-scale output ratio =Full-scale voltage average value for each channels–1 · 100 (%) *2 When the external capacitors for the VG pins are 0.1 µF. Electrical Characteristics Measurement Circuit Analog Input Resistance Measurement CircuitDigital Input Current C XD 1177Q +5.25V AVD D , D VD D AVSS, D VSS V A Item Resolution Conversion speed Integral non-linearity error Differential non-linearity error Output full-scale voltage Output full-scale ratio * Output full-scale current Output offset voltage Glitch energy Crosstalk Supply current Analog input resistance Input capacitance Digital input voltage Digital input current Setup time Hold time Propagation delay time CE enable time * CE disable time *2 Symbol n FCLK EL ED VFS FSR IFS VOS GE CT I DD ISTB R IN C I VIH VIL IIH IIL ts th t PD tE tD Measurement conditions AV DD =DV DD =4.75 to 5.25 V Ta=–40 to +85 °C Endpoint When “00000000” data input R OUT =75 Ω When 1 kHz sine wave input When 14.3 MHz CE=L color bar data inputCE=H VREF AV DD =DV DD =4.75 to 5.25 V Ta=–20 to +75 °C AV DD =DV DD =4.75 to 5.25 V Ta=–20 to +75 °C R OUT =75 Ω R OUT =75 Ω CE=H fi L CE=L fi H Min. 0.5 –2.5 –0.3 1.8 2.4 Typ. 2.0 1.5 Max. 2.5 0.3 2.2 3.0 1.2 0.8 Unit bit MSPS LSB LSB V mA mV pV•s dB mA M Ω pF V µA ns ns ns ms ms

— 6— CXD1177Q YC K 8bit C O U N TER w ith LATC H C LK 40M H Z SQ U AR E W AVE C C K 0.1µ D Vss 200 AVss AVss BLK C E VB YO C O Y0 to Y7 1 to 8 C 0 to C 7 9 to 16 VG VR EF IR EF AVss 0.1µ 3.3k 200 AVD D O SC ILLO SC O PE Crosstalk Measurement Circuit YC K D IG ITAL W AVEFO R M G EN ER ATO R C LK 40M H Z SQ U AR E W AVE C C K 0.1µ D Vss 200 AVss AVss BLK C E VB YO C O Y0 to Y7 1 to 8 C 0 to C 7 9 to 16 VG VR EF IR EF AVss 0.1µ 3.3k 200 AVD D ALL “1” SPEC TR U M AN ALYZER Setup Time Hold Time Measurement Circuit Glitch Energy YC KC LK 1M H Z SQ U AR E W AVE C C K 0.1µ D Vss AVss AVss BLK C E VB YO C O Y0 to Y7 1 to 8 C 0 to C 7 9 to 16 VG VR EF IR EF AVss 0.1µ 1.2k AVD D D ELAY C O N TR O LLER 8bit C O U N TER w ith LATC H D ELAY C O N TR O LLER O SC ILLO SC O PE Maximum Conversion Velocity Measurement Circuit

— 7— CXD1177Q DC Characteristics Measurement Circuit YC KC LK 40M H Z SQ U AR E W AVE C C K 0.1µ D Vss 200 AVss AVss BLK C E VB YO C O Y0 to Y7 1 to 8 C 0 to C 7 9 to 16 VG VR EF IR EF AVss 3.3k 200 AVD D C O N TR O LLER 0.1µ D VM YC K FR EQ U EN C Y D EM U LTIPLIER C LK 10M H Z SQ U AR E W AVE C C K 0.1µ D Vss 200 AVss AVss BLK C E VB YO C O Y0 to Y7 1 to 8 C 0 to C 7 9 to 16 VG VR EF IR EF AVss 0.1µ 3.3k 200 AVD D O SC ILLO SC O PE Propagation Delay Time Measurement Circuit

— 8— CXD1177Q tPW 1 tPW 0 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines ts th ts th ts th tPD tPD tPD C LK D ATA D /A O U T 100% 50% I/O Chart(When full-scale output voltage at 2.00 V) Input code Output voltage MSB LSB 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2.0 V 1.0 V 0 V Description of Operation Timing Chart Y O U T C O U T 200 AVss 200 AVss AVss AVss AVD D 3.3k AVss D Vss 0.1µF D Vss (M SB)(LSB) (M SB) (LSB) D VD D AVD D 0.1µF 9 10 11 12 13 14 15 16 2526272829303132 C IN C LO C K Y IN Application Circuit Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

— 9— CXD1177Q Notes on Operation

• How to select the output resistance The CXD1177Q is a D/A converter of the current output type. To obtain the output voltage connect the resistance to the current output pins Y0, C0. For specifications we have; Output full scale voltageV FS = 1.8 to 2.2 [V] Output full scale currentIFS = less than 15 [mA] Calculate the output resistance value from the relation of VFS = IFS · R OUT . Also, 16 times resistance of the output resistance is connected to reference current pin IREF . In some cases, however, this turns out to be a value that does not actually exist. In such a case a value close to it can be used as a substitute. Here please note that V FS becomes VFS = VREF · 16R OUT /RIR. ROUT is the resistance connected to the current output pins YO and CO while RIR is connected to IREF . Increasing the resistance value can curb power consumption. On the other hand glitch energy and data settling time will inversely increase. Set the most suitable value according to the desired application.
• Phase relation between data and clock To obtain the expected performance as a D/A converter, it is necessary to set properly the phase relation between data and clock applied from the exterior. Be sure to satisfy the provisions of the setup time (t S) and hold time (tH ) as stipulated in the Electrical Characteristics.
• Power supply and grand To reduce noise effects separate analog and digital systems in the device periphery. For the power supply pins, both digital and analog, bypass respective grounds by using a ceramic capacitor of about 0.1 µF, as close as possible to the pin.
• Latch up AV DD and DVDD have to be common at the PCB power supply source. This is to prevent latch up due to voltage difference between AVDD and DVDD pins when power supply is turned ON.
• YO and IO pins The YO and IO pins are the inverted current output pins described in the Pin Description. The sums shown below become the constant value for any input data. a) The sum of the currents output form YO and YO b) The sum of the currents output form CO and CO However, the performances such as the linearity error of the inverted current output pin output current is not guaranteed.

— 10— CXD1177Q C AVSS D VSS AVSS D VSS AVD D D VD D C XD 1177Q D VD D D IG ITAL IC 2123 C +5V Latch Up Prevention The CXD1177Q is a CMOS IC which requires latch up precautions. Latch up is mainly generated by the lag in the voltage rising time of AV DD (Pin 31) and DVDD (Pin 32), when power supply is ON. 1. Correct usage a. When analog and digital supplies are from different sources b. When analog and digital supplies are from a common source (i) (ii) AVD D +5V AVSS D VSS AVSS D VSS AVD D D VD D C XD 1177Q D VD D D IG ITAL IC 2123 C C+5V AVSS D VSS AVSS D VSS AVD D D VD D C XD 1177Q D VD D D IG ITAL IC 2123 C C+5V

— 11— CXD1177Q 2. Example when latch up easily occurs a. When analog and digital supplies are from different sources b. When analog and digital supplies are from common source (i) (ii) AVD D +5V AVSS D VSS AVSS D VSS AVD D D VD D C XD 1177Q D VD D D IG ITAL IC 2123 C +5V C AVSS D VSS AVSS D VSS AVD D D VD D C XD 1177Q D VD D D IG ITAL IC AVD D 2123 +5V +5V AVSS D VSS AVSS D VSS AVD D D VD D C XD 1177Q D VD D D IG ITAL IC AVD D 2123

— 12— CXD1177Q Example of Representative Characteristics 1.00 1.0 2.0 R eference voltage vs. O utput full scale voltage R eference voltage VR EF [V] Output full scale voltage V FS [V] 2.0 0 25 50 75–25 Output full scale voltage V FS [V] 1.9 2.0 Am bient tem perature vs. O utput full scale voltage Am bient tem perature Ta [°C ] 100 100 O utput resistance vs. G litch energy O utput resistance R O U T [Ω ] Glitch energy GE [pV•s] 200 200 100k 1M Crosstalk CT [dB] O utput frequency vs. C rosstalk O utput frequency FO [H z] 10M AVD D =D VD D =5.0V R O U T=200Ω R IR =3.3kΩ Ta=25°C AVD D =D VD D =5.0V VR EF=2.0V R IR 16R O U T Ta=25°C AVD D =D VD D = 5.0V VR EF=2.0V R O U T=200Ω R IR =3.3kΩ AVD D =D VD D = 5.0V VR EF=2.0V R O U T=200 R IR =3.3k Ta=25°C Ω Ω

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32PIN Q FP (PLASTIC ) 9.0 ± 0.2 (8.0) 0.1 – 0.1 + 0.2 + 0.35+ 0.3 0.50 0.127 – 0.05 + 0.1 0° to 10° 0.8 0.3 – 0.1 + 0.15 1 8 932 1724 M0.24 0.2g Q FP-32P-L01 Q FP032-P-0707 0.1 Package Outline Unit : mm CXD1177Q — 13—