CXD1159AQ

CXD1159AQ SONY | Alldatasheet

Document overview

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Technical content

Features

• Adapts to NTSC or P AL through mode switching  Low power consumption  Phase comparator and built-in inverter for active filter (Power supply according to inverter for filter)  Supports external synchronization Structure Silicon gate CMOS Application Video cameras Functions Generation of various sync signals Absolute Maximum Ratings (T a = 25°C)  Supply voltage V DD VSS ∗1 – 0.5 to +7.0 V  Input voltage V I VSS ∗1 – 0.5 to VDD + 0.5 V  Output voltage V O VSS ∗1 – 0.5 to VDD + 0.5 V  Storage temperature Tstg –55 to +150 °C ∗1 VSS = 0V Recommended Operating Conditions  Supply voltage V DD 4.50 to 5.50 V  Operating temperature T opr –20 to +75 °C

– 2 – CXD1159AQ Block Diagram 28 12 18 21 29 30 31 32 1 8 11 25 26 2422 1/4FSCI FSCO CLKO VDD1 VSS1 VDD2 VSS2 HDO VDO SYNC BLKO BFO FLD LALT WNDE WND CLKI 1/5 1/227 PHASE COMPARATOR 1/7 or 6 1/65 1/525 or 625 RESET GENERATOR SUB-CARRIER CONTROL TEST GENERATOR H-DECODER V-DECODER V-CONTROL OUTPUT CONTROL VINT LR VR HR EXT TEST MODE SCOF AIN AOUT PSEL COMP SC Pin Configuration 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 16WNDE WND TEST VDD1 HDO VDO SYNC BLKO PSEL VINT MODE SCOF V SS1 LALT NC NC SC FSCO FSCI V SS2 AOUT AIN V DD2 COMP BFO HR VR LR EXT CLKI CLKO FLD

– 3 – CXD1159AQ Pin Description Pin No. Symbol I/O Description BFO HR VR LR EXT CLKI CLKO FLD NC NC LALT VSS1 SCOF MODE VINT PSEL COMP V DD2 AIN AOUT V SS2 FSCI FSCO SC WNDE WND TEST V DD1 HDO VDO SYNC BLKO O I I I I I O O O I I I I O I O I O O I O I O O O O Burst flag pulse H reset input V reset input LALT reset input Internal/External mode switching INT/EXT Clock input (NTSC: 14.31818MHz, P AL: 14.1875MHz) Clock output Field pulse Line alternate pulse GND Sub carrier suppress input L: OFF NTSC/PAL mode switching NTSC/P AL Initialize input Phase comparator polarity switch Phase comparator output Filter inverter +5V Filter inverter input Filter inverter output Filter inverter GND 4fsc clock input 4fsc clock output Sub carrier output WND output enable input (at L: Enable) Window output T est input (Normally "L") +5V Horizontal drive pulse Vertical drive pulse Composite sync pulse Composite blanking pulse

– 4 – CXD1159AQ

Electrical Characteristics

DC Characteristics (VDD = 5V ± 10%, VSS = 0V , T opr = –20 to +75°C) Item Symbol Supply current Output voltage I∗2 Output voltage II∗3 Input voltage Input leak current Input leak current∗4 High level Low level High level Low level High level Low level IDD IDDS VOH VOL VOH VOL VIH VIL ILI ILZ Conditions Static state∗1 IOH = –2mA IOL = 4mA IOH = –1.5mA IOL = 1.5mA VI = 0V to VDD Min. T yp. Max. Unit VDD – 0.8 VSS VDD /2 VSS 0.7VDD –10 –10 4.5 0.1 VDD 0.4 VDD VDD /2 0.3VDD mA mA V V V V V V µA µA ∗1 VIH = VDD , VIL = VSS ∗2 Output pins except "AOUT" ∗3 "AOUT" pin ∗4 T ri-state pin AC Characteristics Item Symbol Fall delay time Rise delay time tPDL tPDH Conditions VOL = 0.4V VOH = 2.4V Min. T yp. Max. Unit ns ns 2.5V tPDL tPDH HDO CLKI 0.4V 2.4V I/O Capacitance T est conditions: VDD = VI = 0V , fM = 1MHz Filter Amplifier Characteristics Voltage gain G V 25dB (T yp.) Test Circuit VOVI 2019 0.1µF 1µF 1M Ω Gv = 20 logVO VI 600Ω VDD 1kHz Item Symbol Input pin Output pin C IN C OUT Min. T yp. Max. Unit pF pF

– 5 – CXD1159AQ Functions 1. Generation of various sync signals (See the Timing Chart.) Various sync signals are generated from clocks.  Clock frequencies NTSC: 910f H (14.31818MHz) P AL: 908fH (14.1875MHz) 4fsc (17.734475MHz) For the system clock NTSC: 910f H /7 P AL: 908fH /7 or 6 2. PAL PLL for 4fsc T o the master clock of 908f H is matched a phase of 4fsc. The polarity of the phase comparator can be switched according to the type of external filter (passive or active). Filter PSEL Master (908fH ) 4fsc COMP Passive L Active H Fast Slow Fast Slow Delay Fast Delay Fast H L L H 3. SC (Sub-Carrier) generation In either mode unused counters are stopped. When SC is not required, by setting SCOF to L all SC counters are stopped and SC is not output. 4. Initialization and Reset In INT mode the circuit is initialized with the fall of VINT . At that time, H, V and LALT resets are not accepted. In EXT mode, VINT is not accepted, whereas H, V and LALT resets are accepted. SCINT or EXTMode 910fH /4 4fsc/4 4fsc/4 INT EXT x NTSC NTSC PA L INT: Internal mode (EXT = L) EXT: External mode (EXT = H)

– 6 – CXD1159AQ  Initialize (VINT) When EXT = L, VINT fall is detected and operation is started as the circuit is initialized at the VD fall position just before field I. (Initialization is completed within 100ns after the fall is detected). NTSC VINT Initialize point VD HD FLD PAL VINT Initialize point VD HD FLD  H reset (HR) Reset is performed with the first fall. However reset is not done anymore unless there is a deviation of more than 2 clocks (0.98µs) to the subsequent edges. The minimum reset pulse width is 0.98µs. HD is reset 2.94 to 3.43µs in advance of HR input.  V reset (VR) VD is reset 3.5H in advance of VR input. The minimum reset pulse width is 32µs.  LALT reset (LR) LALT is reset in the same phase as LR reset. The minimum reset pulse width is 32µs. HR HD more than 0.98µs 2.94 to 3.43µs LR LALT

– 7 – CXD1159AQ Timing Chart H (NTSC) Timing Chart H (PAL) 6.36 HDO BLKO BFO VD FLD WND HSYNC (SYNC) EO (SYNC) VSYNC (SYNC) 10.76 26.89 28.36 2.45 6.85 17.6 1/2H (Unit: µs) 1.47 ODD EVEN 4.89 2.451.47 6.41 HDO BLKO BFO VD FLD WND LALT HSYNC (SYNC) EO (SYNC) VSYNC (SYNC) 10.70 27.07 28.55 2.47 6.91 17.69 1/2H (Unit: µs) 1.48 ODD EVEN 4.93 2.471.48 4.89 4.93

– 8 – CXD1159AQ Timing Chart V (NTSC) Timing Chart V (PAL) FIELD O O: ODD E: EVENFIELD E HDO VDO SYNC BLKO BFO FLD WND HDO VDO SYNC BLKO BFO FLD WND FIELD E 20H 80.5H 121H 20H 80H 121H FIELD O HDO VDO SYNC BLKO BFO (III – IV) BFO (I – II) LALT (III – IV) LALT (I – II) FLD WND 7.5H 25H 97H 144H FIELD II, IVFIELD I, III HDO VDO SYNC BLKO BFO (IV – I) BFO (II – III) LALT (IV – I) LALT (II – III) FLD WND 7.5H 25H 96.5H 144H FIELD I, IIIFIELD II, IV

– 9 – CXD1159AQ Application Circuit NTSC (Internal mode) PAL (Filter configuration 2, Internal mode) 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 16WNDE WND TEST V DD1 HDO VDO SYNC BLKO PSEL VINT MODE SCOF VSS1 LALT NC NC SC FSCO FSCI VSS2 AOUT AIN VDD2 COMP BFO HR VR LR EXT CLKI CLKO FLD 910fH {14.31818MHz} 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 16WNDE WND TEST V DD1 HDO VDO SYNC BLKO PSEL VINT MODE SCOF VSS1 LALT NC NC SC FSCO FSCI 1000p100k 4fsc {17.73MHz} VSS2 AOUT AIN VDD2 COMP BFO HR VR LR EXT CLKI CLKO FLD 908fH {14.1875MHz} 100 10k 68k 0.01µ 1000p 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 16WNDE WND TEST V DD1 HDO VDO SYNC BLKO PSEL VINT MODE SCOF VSS1 LALT NC NC SC FSCO FSCI 1000p 100k 2SC945 10k 10k 0.1µ4.7k 220k 1.5µ 4fsc {17.73MHz} VSS2 AOUT AIN VDD2 COMP BFO HR VR LR EXT CLKI CLKO FLD 908fH {14.1875MHz} PAL (Filter configuration 1, Internal mode) Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 10 – CXD1159AQ Sony Corporation Package Outline Unit: mm SONY CODE EIAJ CODE JEDEC CODE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42 / COPPER ALLOY 32PIN QFP (PLASTIC) 9.0 ± 0.2 (8.0) 0.1 – 0.1 + 0.2 + 0.35+ 0.3 0.50 0˚ to 10˚0.8 b 1 8 932 1724 M0.24 0.2g QFP-32P-L01 P-QFP32-7x7-0.8 0.1 b = 0.30 – 0.10 ( 0.30) (0.127) + 0.15 DETAIL A : SOLDER A 0.127 – 0.05 + 0.10 LEAD SPECIFICATIONS ITEM LEAD MATERIAL ALLOY 42 LEAD TREATMENT Sn-Pb 10% LEAD TREATMENT THICKNESS 5-18µm SPEC.