CXA7000R

CXA7000R SONY | Alldatasheet

Document overview

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• PDF pages: 23

Technical content

Features

• Supports 10-bit input  Supports signals up to XGA  Low output deviation by on-chip output offset cancel circuit  On-chip timing generator with ECL  VCOM voltage generation circuit  Precharge pulse waveform generation circuit

Applications

LCD projectors and other video equipment Absolute Maximum Ratings (V SS = 0V)  Supply voltage V CC 16 V VDD 5.5 V  Operating temperature T opr –20 to +70 °C  Storage temperature Tstg –65 to +150 °C  Allowable power dissipation PD 1250 mW Recommended Operating Conditions  Supply voltage V CC 15.0 to 15.5 V VDD 4.75 to 5.25 V  Operating temperature T opr –20 to +70 °C LCD Driver

– 2 – CXA7000R Block Diagram D_IN9 SH_OUT6 SH_OUT5 SH_OUT4 SH_OUT3 SH_OUT2D_IN8 D_IN7 D_IN6 D_IN5 D_IN4 D_IN3 D_IN2 D_IN1 D_IN0 NC NC NC STATUS GND PV CC SL_DATDIRC F/H_CNTVREF_OVREF_IV DD PS PRG SID_LVPRG_LVSID_OUTV CC VCOM_OFSTVCOM_OUT GND GNDFRP SHST SHTEST SIG.C SIG_OFST DCFBOFF GND GND MCLK MCLKX PGND GND GNDGND NC CAL_LCAL_H SH_OUT1 PV CC NC TEST PGND GND POSCNT3POSCNT2POSCNT1POSCNT0 Vref Gen. SID_Gen. TG FRP CAL_PLS VCOM_Gen. D/A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

64 Offset Cancel Control

Line inv. Offset Cancel Line inv. Offset Cancel Line inv. Offset Cancel Line inv. Offset Cancel Line inv. Offset Cancel Line inv. Offset Cancel S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H

– 3 – CXA7000R Pin Description Pin No. Symbol I/O Standard voltage level Equivalent circuit Description LCD panel AC drive inversion timing input. High: inverted Low: non-inverted See the Timing Chart. Internal sample-and-hold timing circuit reset pulse input. This pin is also used as the offset cancel level insertion timing input. A reset is applied to the internal timing generator at the falling edge. Output phase adjustment. The output phase is adjusted in MCLK period units when SL_DA T is high, and in 1/2 MCLK period units when SL_DA T is low. Signal center voltage (inversion folded voltage) adjustment input. The SH_OUT output center voltage can be adjusted in the range from 7.0 to 8.0V . Output signal offset adjustment from signal center voltage. The SH_OUT output 100% white level (at 3FF input) voltage can be adjusted in the range from 0 to 1V from the center voltage. High: ≥2.0V Low: ≤0.8V High: ≥2.0V Low: ≤0.8V High: ≥2.0V Low: ≤0.8V 1 to 5.0V 0 to 5.0VISIG_OFST12 ISIG.C11 I POSCNT0 POSCNT1 POSCNT2 POSCNT3 ISHST2 IFRP1 VDD GND 192 50k VDD GND 192 50k VDD GND 192 50k3 VDD VCC GND 30k 20µ VDD VCC GND 30k 10µ Level output for canceling the offset between channels. Connect the CAL_L and CAL_H, between ICs when using two CXA7000R. 3.0 to 6.0V 9.0 to 12.0V I/OCAL_L CAL_H VCC GND 145 40µ 1k

– 4 – CXA7000R Pin No. Symbol I/O Standard voltage level Equivalent circuit Description Offset cancel function off. Normally connect to GND to use with the offset cancel function on. High (offset cancel function off) when open. Demultiplexed output of AC inverse driven video signals. Can be connected directly to the LCD panel. LCD panel common voltage output. Can be set in the range from the SH_OUT center potential Vsig.c to Vsig.c – 2V by VCOM_OFST . LCD panel common voltage adjustment. VCOM_OUT can be set in the range from the SH_OUT center potential Vsig.c to Vsig.c – 2V by inputting 0 to 5V . GND 1.5 to 13.5V 5.0 to 8.0V 0 to 5.0VIVCOM_OFST34 OVCOM_OUT33 O SH_OUT6 to SH_OUT1 IDCFBOFF16 Precharge waveform output. These pins cannot directly drive the LCD panel, so input to the LCD panel with an external buffer. 1.5 to 13.5VOSID_OUT36 VDD GND 145 24k24k PV CC GND 300 300 VCC GND 145100k 80µ 500 500 VDD VCC GND 100 80µ VCC GND 145 100k 100k 0.2p 0.2p

– 5 – CXA7000R Pin No. Symbol I/O Standard voltage level Equivalent circuit Description Precharge level setting. Adjusts the SID_OUT and SID_OUTX output potential. PRG_LV is reflected when the PRG input pin (Pin 60) is high, and SID_LV is reflected when PRG is low. Timing pulse input for switching the Pin 36 output levels. (See PRG_LV (Pin 37) and SID_LV (Pin 38).) Internal D/A converter reference voltage input. Normally connect directly to VREF_O. Reference voltage output. Normally connect directly to VREF_I, and connect to GND through a 0.5 to 1.0µF capacitor. SH_OUT output timing selection. High: SH_OUT1 to SH_OUT3 and SH_OUT4 to SH_OUT6 are output at different timing. Low: SH_OUT1 to SH_OUT6 are output at the same timing. 1.0 to 5.0V High: ≥2.0V Low: ≤0.8V Open: Low IF/H_CNT46 IPRG_LV SID_LV Scan direction setting. High: output as a time series in ascending order of output pin symbol (in order from SH_OUT1 to SH_OUT6) Low: output in descending order High: ≥2.0V Low: ≤0.8VIDIRC47 VDD VCC GND 50k 29µ 50k VDD VCC GND 10k 100k 50µ VDD GND 280µ 70µ 10µ 33.3k VDD GND 20µ 20k 12.4k VDD GND 192 50k 200k VDD GND 192 50k High: ≥2.0V Low: ≤0.8VIPRG39 3.2VIVREF_I44 3.2VOVREF_O45

– 6 – CXA7000R Pin No. Symbol I/O Standard voltage level Equivalent circuit Description Dot clock input. PECL differential input or TTL input. For TTL input, input to MCLK and connect MCLKX to GND through a capacitor. Power GND. Power V CC . 15V power supply. 5V power supply. PECL differential (amplitude 0.4V or more between V DD to 2V) or TTL input IMCLK MCLKX GND 15.5V 15.5V PGND PV CC VCC 15 VDD 5 24, 25 17, 32 Digital input mode switch setting. High: when using master/slave mode two CXA7000R. Low: when using normal mode one CXA7000R. High: ≥2.0V Low: ≤0.8V Open: Low ISL_DA T48 Master/slave setting when using two CXA7000R. High: master IC. Offset cancel level is output. Low: slave IC. This pin is left open (high) when using one CXA7000R. High: ≥2.0V Low: ≤0.8V IST A TUS50 Digital data input.High: ≥2.0V Low: ≤0.8VID_IN9 to D_IN0 to to VDD GND 192 50k 200k VDD GND 192 50k 200k VDD GND 192 50k 5551 to 6258 to VDD 140k 60k 60k100µ 140k8k GND VDD GND 70k 30µ180k 42 T est. Normally connect to VDD .5VIPS42

– 7 – CXA7000R Pin No. Symbol I/O Standard voltage level Equivalent circuit Description GND. NC. These pins are not connected to anything. GNDGND NC 8, 9, 15, 23, 26, 40, 41, 56, 57 10, 19, 21, 28, DAC output monitor test. Normally connect to VDD . T est. Leave open. 1.7 to 3.2V 2.5VISHTEST7 OTEST49 VDD GND 192 250k 20k 20k 250k 20k 20k 10µ10µ VDD GND 192 20µ

– 8 – CXA7000R Electrical Characteristics Measurement Circuit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 33343536373839404142434445464748 TESTVDD SL_DAT DIRC F/H_CNT VREF_O VREF_I V DD 5 PS GND GND PRG SID_LV PRG_LV SID_OUT V CC 15 VCOM_OFST VCOM_OUT PV CC SH_OUT1 NC SH_OUT2 NC SH_OUT3 GND PGND PGND GND SH_OUT4 STATUS D_IN9 D_IN8 D_IN7 D_IN6 D_IN5 GND GND D_IN4 D_IN3 D_IN2 D_IN1 D_IN0 MCLK MCLKX NC SH_OUT5 NC SH_OUT6 PV CC VCC FRP POSCNT3 SHST POSCNT0 POSCNT1 POSCNT2 SHTEST GND GND NC SIG.G SIG_OFST CAL_L CAL_H GND DCFBOFF 270p 270p 270p 270p 270p 270p A VDD A VCC A 47p 15.5V VCC VDD

– 9 – CXA7000R

Electrical Characteristics

No. Item Symbol Measurement points Measurement conditions Min. T yp. Max. Unit Digital input resolution Digital input setup time Digital input hold time MCLK input frequency range 1 MCLK input frequency range 2 VREF_I input voltage range VREF_O output voltage range SH_OUT amplitude SH_OUT minimum amplitude SH_OUT slew rate SH_OUT minimum output voltage SH_OUT maximum output voltage Output deviation between channels 1 Output deviation between channels 2 Output deviation between ICs 1 n TS TH fMCLK1 fMCLK2 VVREF_I VVREF_O VSHOUTp-p VOUTMINp-p SR OUT VMIN VMAX D OUT1 D OUT2 D IC1 VOUT1 VOUT1 VOUT1 to VOUT6 VOUT1 to VOUT6 VOUT1 to VOUT6 VOUT1 to VOUT6 VOUT1 to VOUT6 VOUT1 to VOUT6 SHST and D_IN[9:0] minimum setup time relative to MCLK input. SHST and D_IN[9:0] minimum hold time relative to MCLK input. SL_DA T: 5V; maximum frequency at which the internal timing generator and D/A converter operate normally. SL_DA T: 0V; maximum frequency at which the internal timing generator and D/A converter operate normally. VREF_I input voltage range at which the D/A converter operate normally. Measure the VREF_O (Pin 45) voltage. Measure the SH_OUT1 voltage difference at D_IN[9:0]: 000h and 3FFh. Lower the VREF_I voltage and adjust the amplitude; minimum amplitude at which SH_OUT1 can be output at D_IN[9:0]: 000h and 3FFh. Load capacitance = 270pF; measure slew rate at 10 to 90% of output waveform rise and fall when D_IN[9:0] is varied from 000h to 3FFh and from 3FFh to 000h. Minimum voltage at which sample- and-hold outputs V OUT1 to VOUT6 can be output. Maximum voltage at which sample- and-hold outputs VOUT1 to VOUT6 can be output. Value obtained by subtracting minimum V OUT1 to VOUT6 value from maximum VOUT1 to VOUT6 value at D_IN[9:0]: 200h. Value obtained by subtracting minimum VOUT1 to VOUT6 value from maximum VOUT1 to VOUT6 value at D_IN[9:0]: 000h or 3FFh. Value obtained by subtracting minimum VOUT1 to VOUT6 value from maximum VOUT1 to VOUT6 value at D_IN[9:0]: 200h. (when using two CXA7000R) 3.2 3.2 4.5 150 bit ns ns MHz MHz V V V V V/µs V V mVp-p mVp-p mVp-p 2.7 3.1 4.39 3.9 150 1.5 100 3.5 3.3 4.64 13.5

– 10 – CXA7000R Output deviation between ICs 2 SID output gain 1 SID output gain 2 SID output slew rate Signal center adjustable range SH_OUT offset adjustable range VCOM adjustable range VDD current consumption VCC current consumption Current consumption in power saving mode Differential linearity error Integral linearity error D IC2 ASID1 ASID2 SR SID VSIG VSIGOFST VCOM IDD ICC IPS D LE ILE VOUT1 to VOUT6 VSID_LV VSID VPRG_LV VSID VSID VOUT1 VOUT1 VCOM IVDD IVCC1 IVCC2 IVDD IVCC1 IVCC2 Value obtained by subtracting minimum VOUT1 to VOUT6 value from maximum VOUT1 to VOUT6 value at D_IN[9:0]: 000h or 3FFh. (when using two CXA7000R) PRG: 0V; measure VSID_LV and VSID at FRP: 0V , and VSID_LV at FRP: 5V . Calculate as ASID1 = VSID/VSID_L V. PRG: 5V; measure VPRG_LV and VSID at FRP: 0V , and VPRG_LV at FRP: 5V . Calculate as ASID2 = VSID/VPRG_LV . Load capacitance = 47pF , PRG: 0V; input a repeating high/low pulse to FRP (Pin 1), and apply DC input voltage so that V SID is 4V/10V . Measure slew rate at 10 to 90% of output waveform rise and fall. VOUT1 center voltage when SIG.C (Pin 11) is varied from 0 to 5V . D_IN[9:0]: 3FFh, FRP: 0V; value obtained by subtracting VOUT1 from VOUT1 center voltage when SIG_OFST (Pin 12) is varied from 0 to 5V . VCOM_OUT voltage when VCOM_OFST (Pin 34) is varied from 0 to 5V . IDD = IVDD ICC = IVCC1 + IVCC2 GND (Pin 42), I CC = IVDD + IVCC1 + IVCC2 VVREF _I = 3.2V VVREF _I = 3.2V mVp-p times times V/µs V V V mA mA mA LSB LSB No. Item Symbol Measurement points Measurement conditions Min. T yp. Max. Unit 1.9 1.9 Vc – 2.5 –0.5 –1.5 2.1 2.1 Vc 0.7 0.4

– 11 – CXA7000R Description of Operation The flow of internal operations is described below. The digital signals input to D_IN0 to D_IN9 are internally D/A converted into approximately 1.5V (at VREF_I: 3.2V) analog signals. After that, the signal that has been demultiplexed into 6 phases is amplified by a factor of three times, inverted at the signal center potential according to FRP , and output. The output level relative to the digital input changes according to the following settings. A: SIG_OFST voltage B: VREF_I voltage C: SIG.C voltage 1. Digital input block The CXA7000R can be set to master/slave mode, single mode and left/light inversion. This makes it possible to support various systems. In master/slave mode, the even and odd data is internally selected respectively and input to the D/A converter. 2. D/A converter block The internal D/A converter has two systems for odd-numbered and even-numbered outputs. The voltage input from VREF_I becomes the 100% white level potential of the analog converted signal, and this amplitude is a maximum 1.5Vp-p with respect to input data of 000h to 3FFh. 3. Sample-and-hold (S/H) block The D/A converter outputs are input to the sample-and-hold blocks, respectively. The signals are converted from time series signals into 6-phase cyclic parallel signals by the sample-and-hold group which is appropriately controlled by the internal timing generator. For forward scan, the signals are output in the ascending order of SH_OUT1, SH_OUT2, SH_OUT3 ... SH_OUT6. For reverse scan, this order is inverted and the signals are output in descending order. Connect the signals to the LCD panel according to the order used. The timing of each sample-and-hold pulse is shown on the following pages. These pulses are not output and are used only inside the IC. VCC GND Signal Center 1023 512 A A B B C Digital IN SH_OUT

– 12 – CXA7000R Master/slave mode D DAC S/HD_IN[9:0] MCLK/2 D_IN2 D_IN1 Selector STATUS DAC_O MCLK D 10bit D_IN[9:0] D_IN1 D_IN2 DAC_O MCLK SH1_1 SH1_2 SH1_3 SH1_4 SH1_5 SH1_6 SH2_1_3 SH2_4_6 SH3A_1_6 SH3B_4_6 SH3B_1_3 SH1_1 SH1_2 SH1_3 SH1_4 SH1_5 SH1_6 SH2_1_3 SH2_4_6 SH3A_1_6 SH3B_4_6 SH3B_1_3 DIRC: H DIRC: L F/H_CNT: L F/H_CNT: H F/H_CNT: L F/H_CNT: H D D L H 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 1 3 5 7 9 11 13 15 17 19 21 23 25 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 CH1 to CH6 simultaneous output timing CH1 to CH3 simultaneous output timing CH4 to CH6 simultaneous output timing CH1 to CH6 simultaneous output timing CH1 to CH3 simultaneous output timing CH4 to CH6 simultaneous output timing

– 13 – CXA7000R Single mode D DAC S/HD_IN[9:0] MCLK D_IN2D_IN1 DAC_O D 10bit MCLK D_IN1 DAC_O 1 2 3 40 5 6 7 8 9 10 11 12 13 14D_IN[9:0] 01 2 3–14 5 6 7 8 9 1 0 1 1 1 2D_IN2 1 2 3 4 5 6 7 8 9 10 11 12 130 SH1_1 SH1_2 SH1_3 SH1_4 SH1_5 SH1_6 SH2_1_3 SH2_4_6 SH3A_1_6 SH3B_4_6 SH3B_1_3 SH1_1 SH1_2 SH1_3 SH1_4 SH1_5 SH1_6 SH2_1_3 SH2_4_6 SH3A_1_6 SH3B_4_6 SH3B_1_3 DIRC: H DIRC: L F/H_CNT: L F/H_CNT : H F/H_CNT: L F/H_CNT: H D CH1 to CH6 simultaneous output timing CH1 to CH3 simultaneous output timing CH4 to CH6 simultaneous output timing CH1 to CH6 simultaneous output timing CH1 to CH3 simultaneous output timing CH4 to CH6 simultaneous output timing

– 14 – CXA7000R 4. Timing generator (TG) block The internal timing generator operates by one pair of differential clock inputs (MCLK, MCLKX) and a horizontal sync signal input (SHST), and generates the timing pulses needed by the demultiplexer block, dot inversion control pulse and output deviation cancel circuit. The various operating modes can be designated by the pin settings. The SHST and FRP inputs should satisfy the relationship shown in the figure below with the MCLK and MCLKX input period as 1clk. The CXA7000R can select various operating modes according to the timing generator block settings. These settings are described below.  SL_DA T (Pin 48) Operation mode selection. Master/slave mode is selected which is common with digital input of two ICs when set to high level, and single mode is selected with one IC when set to low level. In case of the former, connect 10-bit input as short as possible between two ICs and select which data of odd or even is obtained by ST A TUS (Pin 50).  DIRC (Pin 47) Scan direction settings. Output is ascending order when DIRC is set to high level, and inverted to descending order (SH_OUT1 to SH_OUT6) when set to low level. Also, the output is varied as shown below in combination with ST A TUS (Pin 50). 30clk or more 1µs or more SHST FRP 123456789 1 0 1 1 1 2 1 3 1 4 1 5D_IN[9:0] ST A TUS: L ST A TUS: H SH_OUT1: 11 SH_OUT2: 9 SH_OUT3: 7 SH_OUT4: 5 SH_OUT5: 3 SH_OUT6: 1 SH_OUT1: 12 SH_OUT2: 10 SH_OUT3: 8 SH_OUT4: 6 SH_OUT5: 4 SH_OUT6: 2 SH_OUT1: 2 SH_OUT2: 4 SH_OUT3: 6 SH_OUT4: 8 SH_OUT5: 10 SH_OUT6: 12 SH_OUT1: 1 SH_OUT2: 3 SH_OUT3: 5 SH_OUT4: 7 SH_OUT5: 9 SH_OUT6: 11 DIRC: HDIRC: L SH_OUT1: 6 SH_OUT2: 5 SH_OUT3: 4 SH_OUT4: 3 SH_OUT5: 2 SH_OUT6: 1 SH_OUT1: 1 SH_OUT2: 2 SH_OUT3: 3 SH_OUT4: 4 SH_OUT5: 5 SH_OUT6: 6 DIRC: HDIRC: L SL_DA T: L SL_DA T: H

– 15 – CXA7000R  Output phase setting The phase of each SH_OUT output can be adjusted by POSCNT[3:0] (Pins 3 to 6). The phase can be set in 16 ways by 4-bit digital input. The output phase shifts backward by the clock period units when SL_DA T is high or 1/2 clock period units when SL_DA T is low each time this setting is increased by one bit.  F/H_CNT (Pin 46) SH_OUT output timing phase setting. When set to low level, all SH_OUT outputs are output at the same timing. When set to high level, SH_OUT1 to SH_OUT3 and SH_OUT4 to SH_OUT6 are output at phases offset by 1/2 clock period from each other. GND SH_OUT1 to 3 SH_OUT4 to 6 GND SH_OUT1 to 3 SH_OUT4 to 6 F/H_CNT: L F/H_CNT: H

– 16 – CXA7000R 5. Calibration level generator block The CXA7000R has a built-in offset cancel circuit and generates the reference with a calibration level generator in order to minimize the deviation between channels at the center level. The 200h output level is generated at both the AC output high and low sides respectively when STA TUS (Pin 50) is high level, and these levels are DC output from CAL_H and CAL_L and at the same time, these are used internally. When ST A TUS (Pin 50) is low level, CAL_H and CAL_L are input pins and the external offset cancel level is input. The 200h data is forcibly inserted into the video signal while the video blanking period SHST pulse is low level, and feedback is applied so that the output levels of all SH_OUT channels conform to CAL_H and CAL_L during this period. 6. SID signal generator block This circuit generates the precharge signal waveform used by the LCD panel. The voltage input from PRG_LV (Pin 37) and SID_L V (Pin 38) is switched by the PRG pulse (Pin 39). The PRG_L V voltage is selected when PRG is high, and the SID_LV voltage is selected when PRG is low. This signal is then further amplified by a factor of two times and folded by the FRP pulse. The folded center voltage is the SH_OUT center voltage (voltage set by the SIG.C pin). SID_OUT (Pin 36) is inverted when FRP is high, and non-inverted when FRP is low. SID_OUT cannot directly drive the precharge signal input of the LCD panel, so they should be connected via a buffer having sufficient current supply capability. 7. VCOM potential generator block This block sets the DC common potential for the LCD panel. VCOM_OFST (Pin 33) sets the deviation relative to the SH_OUT center potential, which is set by SIG.C. SHST FRP SH_OUT 200h 200h 000h 000h 200ns CAL_PLS (internal pulse) Video signal replacement period Signal center Offset cancel operation Delayed by sample-and-hold

– 17 – CXA7000R Example of Representative Characteristics (VCC = 15.5V , VDD = 5.0V , T a = 25°C) 4.6 4.5 4.3 4.2 4.4 4.1 4.0 3.9 3.8 4.8 4.7 3FFh300h200h100h000h 4.03.53.02.5 8.0 8.5 7.0 6.0 5.0 5.5 7.5 3.02.01.00.0 7.0 6.0 5.5 4.5 7.5 4.5 6.5 9.0 4.0 6.5 5.0 FRP = High FRP = Low FRP = High FRP = Low 5.0 VREF_I voltage vs. SH_OUT voltage white-black amplitude SH_OUT white-black amplitude voltage [V] VREF_I voltage [V] Input data vs. SH_OUT voltage SH_OUT voltage [V] Input data (10 bits) SIG.C voltage vs. SH_OUT center voltage SH_OUT center voltage [V] SIG.C voltage [V] SIG_OFST voltage vs. SH_OUT voltage SH_OUT voltage [V] SIG_OFST voltage [V] VCOM_OFST voltage vs. VCOM_OUT voltage VCOM_OUT voltage [V] VCOM_OFST voltage [V] <Measurement conditions> SIG.C = 3.75V SIG_OFST = 3.6V <Measurement conditions> SIG_OFST = 3.6V <Measurement conditions> SIG.C = 3.75V SIG_OFST = 3.6V <Measurement conditions> SIG.C = 3.75V DATA = 200h <Measurement conditions> SIG.C = 3.75V

– 18 – CXA7000R 43210 FRP = High FRP = Low 43210 FRP = High FRP = Low PRG_LV voltage vs. SID_OUT voltage SID_OUT voltage [V] SID_LV voltage vs. SID_OUT voltage PRG_LV voltage [V]SID_LV voltage [V] SID_OUT voltage [V] <Measurement conditions> SIG.C = 3.75V <Measurement conditions> SIG.C = 3.75V

– 19 – CXA7000R Application Circuit 1 (to SVGA Panel) 47µF Buffer OPEN 1Ω10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω D_IN9 SH_OUT6 SH_OUT5 SH_OUT4 SH_OUT3 SH_OUT2D_IN8 D_IN7 D_IN6 D_IN5 D_IN4 D_IN3 D_IN2 D_IN1 D_IN0 ROUT9 PRG DSD CXD3526GG LCD Panel LCX026 RGT ROUT8 ROUT7 ROUT6 ROUT5 ROUT4 ROUT3 ROUT2 ROUT1 ROUT0 CLKOUT FRP SHST NC NC NC STATUS GND PV CC SL_DATDIRCF/H_CNTVREF_OVREF_IV DD5 PS PRGSID_LVPRG_LVSID_OUTV CC15 VCOM_OFSTVCOM_OUT GNDGNDFRPSHST SHTEST SIG.C SIG_OFST DCFBOFF GND GND MCLK MCLKX PGND GND GNDGND NC CAL_LCAL_H CXA7000R SH_OUT1 PV CC NC TEST PGND GND POSCNT3POSCNT2POSCNT1POSCNT0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PV CC VCC VDD 20kΩ 20kΩ 20kΩ 20kΩ VDD 0.1µF 0.1µF 1µF 1µF 0.1µF 47µF 0.1µF1µF 0.1µF 47µF VDD VDD VDD VDD VDD VDD Vsig6 Vsig5 Vsig4 Vsig3 Vsig2 Vsig1 COM Psig 113 10Ω 10Ω 118 119 15.5V PV CC 10Ω2 10Ω45 15.5V VCC VDD 20kΩ 0.1µF VDD 20kΩ 0.1µF VDD 10kΩ Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 20 – CXA7000R Application Circuit 2 (to XGA Panel) 47µF Buffer OPEN PV CC 0.1µF 47µF 1Ω10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω D_IN9 SH_OUT6 SH_OUT5 SH_OUT4 SH_OUT3 SH_OUT2D_IN8 D_IN7 D_IN6 D_IN5 D_IN4 D_IN3 D_IN2 D_IN1 D_IN0 ROUT9 PRG DSD CXD3526GG LCD Panel LCX029 RGT ROUT8 ROUT7 ROUT6 ROUT5 ROUT4 ROUT3 ROUT2 ROUT1 ROUT0 CLKOUT FRP SHST NC NC NC STATUS GND PV CC SL_DATDIRCF/H_CNTVREF_OVREF_IV DD5 PS PRGSID_LVPRG_LVSID_OUTV CC15 VCOM_OFSTVCOM_OUT GNDGNDFRPSHST SHTEST SIG.C SIG_OFST DCFBOFF GND GND MCLK MCLKX PGND GND GNDGND NC CAL_LCAL_H CXA7000R SH_OUT1 PV CC NC TEST PGND GND POSCNT3POSCNT2POSCNT1POSCNT0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PV CC VCC VDD 20kΩ 20kΩ 20kΩ 10kΩ 20kΩ VDD 0.1µF 0.1µF 0.47µF 0.47µF 0.47µF 0.47µF 0.1µF 47µF 0.1µF1µF 0.1µF 47µF VDD 10kΩ 0.1µF VDD VDD VDD 0.1µF 47µF VDDVDD VDD VDD VCC VDD 20kΩ 1µF VDD VDD VDD VDD D_IN9 SH_OUT6 SH_OUT5 SH_OUT4 SH_OUT3 SH_OUT2D_IN8 D_IN7 D_IN6 D_IN5 D_IN4 D_IN3 D_IN2 D_IN1 D_IN0 NC NC NC STATUS GND PV CC SL_DATDIRCF/H_CNTVREF_OVREF_IV DD5 PS PRGSID_LVPRG_LVSID_OUTV CC15 VCOM_OFSTVCOM_OUT GNDGNDFRPSHST SHTEST SIG.C SIG_OFST DCFBOFF GND GND MCLK MCLKX PGND GND GNDGND NC CAL_LCAL_H CXA7000R SH_OUT1 Vsig11 Vsig9 Vsig7 Vsig5 Vsig3 Vsig1 COM Psig Vsig12 Vsig10 Vsig8 Vsig6 Vsig4 Vsig2 PV CC NC TEST PGND GND POSCNT3POSCNT2POSCNT1POSCNT0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 0.1µF OPEN 113 10Ω 10Ω 118 119 20kΩ 15.5V0.1µF VDD PV CC 20kΩ 0.1µF VDD 10Ω2 10Ω45 15.5V VCC VDD Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 21 – CXA7000R Application Circuit 3 (to SXGA Panel) 47µF Buffer OPEN PV CC 0.1µF 47µF 1Ω10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω D_IN9 SH_OUT6 SH_OUT5 SH_OUT4 SH_OUT3 SH_OUT2D_IN8 D_IN7 D_IN6 D_IN5 D_IN4 D_IN3 D_IN2 D_IN1 D_IN0 R1OUT9 PRG DSD CXD3511Q LCD Panel LCX028 RGT R1OUT8 R1OUT7 R1OUT6 R1OUT5 R1OUT4 R1OUT3 R1OUT2 R1OUT1 R1OUT0 CLKOUT FRP SHST NC NC NC STATUS GND PV CC SL_DATDIRCF/H_CNTVREF_OVREF_IV DD5 PS PRGSID_LVPRG_LVSID_OUTV CC15 VCOM_OFSTVCOM_OUT GNDGNDFRPSHST SHTEST SIG.C SIG_OFST DCFBOFF GND GND MCLK MCLKX PGND GND GNDGND NC CAL_LCAL_H CXA7000R SH_OUT1 PV CC NC TEST PGND GND POSCNT3POSCNT2POSCNT1POSCNT0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PV CC VCC VDD 20kΩ 20kΩ 20kΩ 10kΩ 20kΩ VDD 0.1µF 0.1µF 0.47µF 0.47µF 0.47µF 0.47µF 0.1µF 47µF 0.1µF1µF 0.1µF 47µF VDD 10kΩ 0.1µF VDD VDD VDD 0.1µF 47µF VDDVDD VDD VDD VCC VDD 20kΩ 1µF VDD VDD VDD VDD D_IN9 SH_OUT6 SH_OUT5 SH_OUT4 SH_OUT3 SH_OUT2D_IN8 D_IN7 D_IN6 D_IN5 D_IN4 D_IN3 D_IN2 D_IN1 D_IN0 NC NC NC STATUS GND PV CC SL_DATDIRCF/H_CNTVREF_OVREF_IV DD5 PS PRGSID_LVPRG_LVSID_OUTV CC15 VCOM_OFSTVCOM_OUT GNDGNDFRPSHST SHTEST SIG.C SIG_OFST DCFBOFF GND GND MCLK MCLKX PGND GND GNDGND NC CAL_LCAL_H CXA7000R SH_OUT1 Vsig11 Vsig9 Vsig7 Vsig5 Vsig3 Vsig1 COM Psig Vsig12 Vsig10 Vsig8 Vsig6 Vsig4 Vsig2 PV CC NC TEST PGND GND POSCNT3POSCNT2POSCNT1POSCNT0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 0.1µF COML21 COMR2 OPEN 122 121 120 119 118 117 116 113 112 111 10Ω 10Ω 157 159 20kΩ 15.5V0.1µF VDD PV CC 20kΩ 0.1µF VDD 10Ω136 10Ω161 15.5V VCC VDD R2OUT9 R2OUT8 R2OUT7 R2OUT6 R2OUT5 R2OUT4 R2OUT3 R2OUT2 R2OUT1 R2OUT0 110 109 108 107 106 105 104 103 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 22 – CXA7000R Notes on Operation The CXA7000R has high power consumption, so be sure to take the following radiation measures.  Use four-layer substrate.  GND lines connected to Pins 8, 9, 24, 25, 40, 41, 56 and 57 should be as thick as possible.

– 23 – CXA7000R Sony Corporation Package Outline Unit: mm SONY CODE EIAJ CODE JEDEC CODE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN COPPER ALLOY PACKAGE STRUCTURE 12.0 ± 0.2 ∗ 10.0 ± 0.1 (0.22) b 1 16 3348 0.1 ± 0.1 0.5 ± 0.2 0˚ to 10˚ 64PIN LQFP (PLASTIC) LQFP-64P-L01 P-LQFP64-10x10-0.5 0.3g DETAIL A 0.5 ± 0.2 (11.0) A 1.5 – 0.1 + 0.2 0.1 PALLADIUM PLATING NOTE: Dimension “∗” does not include mold protrusion. 0.13 M 0.5 b = 0.18 ± 0.03 0.125 ± 0.04 DETAIL B : PALLADIUM