CXA2164Q

CXA2164Q SONY | Alldatasheet

Document overview

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Technical content

Features

• Alignment-free VCO and filter
• Audio multiplexing decoder, dbx noise reduction decoder, sound processor — One external input — Volume control are all included in a single chip. Almost any sort of signal processing is possible through this IC.
• Input level, separation adjustments and each mode control are possible through I 2C BUS. Absolute Maximum Ratings(Ta = 25°C)
• Supply voltage V CC 11 V
• Operating temperature Topr –20 to +75 °C
• Storage temperature Tstg –65 to +150 °C
• Allowable power dissipation PD 0.6 W Range of Operating Supply Voltage 9 ± 0.5 V

Applications

TV, VCR and other decoding systems for US audio multiplexing TV broadcasting Structure Bipolar silicon monolithic IC ∗ A license of the dbx-TV noise reduction system is required for the use of this device. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. 2 3 4 5 6 7 8 9 10 11 12 252627282930 36 35 34 313233 SDA SCL DGNDMANIN NC NC NC COMPIN NC PCINT2PCINT1 VCATCVCAINVEOUTVETCVEWGTNC NC NC VE SAPINNC SAPOUT LSOUT-L LSOUT-R NC AUX-L NC NC NC AUX-R NC VCAWGT NC VGR NC GND SAPTC VCC SUBOUT STIN MAINOUT PLINT IREF NC NOISETC NC NC Pin Configuration (Top View)

– 2– CXA2164Q Block Diagram VGR IREF DGND SCL SDA SAPOUT SAPIN STIN VE VEWGT VETC VEOUT VCAIN VCAWGT VCATC MAININ MAINOUT SUBOUT PLINT PCINT1 COMPIN VCC GND NOISETC SAPTC IREF SW LPF LPF HPF RMSDET RMSDET VCAVEDeEm LOGIC VCA LPF LPF 1/21/4VCOLFLT VCA LPF BPF SAPVCO LPF NOISE DET SAPIND "PONRES" STIND "SAP" "NOISE" NRSW/FOMO/SAPC WIDEBAND SPECTRAL "STEREO" DeEm FLT AMP (+4dB) I2C BUS I/F (+6dB) AUX-R AUX-L PCINT2 TVSW LSOUT-R LSOUT-L EXT1/M1 VOL-L 333228 ATT 8 9 11 14 2515 2 1 48 27 34 3635 37 3422 40 MATRIX VOL-R VOL-L VOL-R

– 3– CXA2164Q Pin Description (Ta = 25°C, VCC = 9V) 7.5k ↓ 35µ 2.1V 10.5k × 4 VCC VCC 147 10k 53k VCC Pin No. Symbol Pin voltage Equivalent circuit Description SCL DGND MAININ 4.0V Serial clock input pin. VIH > 3.0V VIL< 1.5V Digital block GND. Input the (L + R) signal from MAINOUT (Pin 4). MAINOUT NC 4.0V (L + R) signal output pin. VCC 147 15k 200µ VCC × 4 5 5 NC — —6 6 NC — —7 7

– 4– CXA2164Q Pin No. Symbol Pin voltage Equivalent circuit Description PCINT1 PCINT2 PLINT 4.0V 4.0V 5.1V Stereo block PLL loop filter integrating pin. Pilot cancel circuit loop filter integrating pin. (Connect a 1µF capacitor between this pin and GND.) VCC 147 20k 26µ 20k 10k20k ↓ 50µ 20k20k 22k VCC 30k 147 VCC × 2 10k 10k 147 COMPIN 4.0V Audio multiplexing signal input pin.12 VCC 16k 50k 147 16k 16k NC — —10 10 NC — —13 13

– 5– CXA2164Q Pin No. Symbol Pin voltage Equivalent circuit Description VGR IREF GND 1.3V 1.3V Band gap reference output pin. (Connect a 10µF capacitor between this pin and GND.) Set the filter and VCO reference current. The reference current is adjusted with the BUS DATA based on the current which flows to this pin. (Connect a 62kΩ (±1%) resistor between this pin and GND.) Analog block GND. Set the time constant for the SAP carrier detection circuit. (Connect a 4.7µF capacitor between this pin and GND.) SAPTC 4.5V18 10k VCC ↓ 50µ VCC 40k 40k 30k 30p 1.8k 16k 6.3k 147 30k 15k 30k VCC × 2 VCC × 4 11k 9.7k 19.4k 2.06k 3k 147 VCC 11k 11k NC — —16 16 NC — —19 19 VCC — Supply voltage pin.20 20 NC — —21 21

– 6– CXA2164Q Pin No. Symbol Pin voltage Equivalent circuit Description SUBOUT STIN NOISETC 4.0V 4.0V 3.0V (L-R) signal output pin. Input the (L-R) signal from SUBOUT (Pin 22). Set the time constant for the noise detection circuit. (Connect a 4.7µF capacitor between this pin and GND.) SAPIN 4.0V Input the (SAP) signal from SAPOUT (Pin 25).27 2k 2k 2k 4k 1k 14758014.4k 580 10P 2k2k Vcc 23k 147 18k 20k 11.7k 23k 147 18k VCC 23 27 3k3k 3.3k Vcc × 2 10k 1k 2k Vcc 200k SAPOUT 4.0V SAP FM detector output pin.25 24k ↓ 10µ 580 Vcc 580 ↓ 50µ 10k 147

– 7– CXA2164Q Pin No. Symbol Pin voltage Equivalent circuit Description VE VETC 4.0V 1.7V Variable de-emphasis integrating pin. (Connect a 2700pF capacitor and a 3.3kΩ resistor in series between this pin and GND.) Determine the restoration time constant of the variable de-emphasis control effective value detection circuit. (The specified restoration time constant can be obtained by connecting a 3.3µF capacitor between this pin and GND.) VEWGT 4.0V Weight the variable de-emphasis control effective value detection circuit. (Connect a 0.047µF capacitor and a 3kΩ resistor in series between this pin and GND.) Vcc 36k 2.9V580 147 580 8k 30k ↓ 8µ ↓ 50µ 20k ↓ 7.5µ4k ↓ 50µ Vcc × 4 × 4 7.5k 147 VCC NC — —26 26 NC — —29 29 NC — —30 30 NC — —31 31

– 8– CXA2164Q Pin No. Symbol Pin voltage Equivalent circuit Description VEOUT VCAIN VCAWGT 4.0V 4.0V 4.0V Variable de-emphasis output pin. (Connect a 4.7µF non-polar capacitor between Pins 34 and 35.) VCA input pin. Input the variable de-emphasis output signal from Pin 34 via a coupling capacitor. Weight the VCA control effective value detection circuit. (Connect a 1µF capacitor and a 3.9kΩ resistor in series between this pin and GND.) VCATC 1.7V Determine the restoration time constant of the VCA control effective value detection circuit. (The specified restoration time constant can be obtained by connecting a 10µF capacitor between this pin and GND.) Vcc 10k 580 580 VCC 30k 8k 36k 2.9V 580 580147 40k 40k 50µ 50µ VCC 4k 20k × 4 × 4 7.5µ VCC 20k VCC 47k 47k

– 9– CXA2164Q Pin No. Symbol Pin voltage Equivalent circuit Description —NC —38 38 AUX-R 4.0V Right channel external input pin.39 AUX-L 4.0V Left channel external input pin.40 VCC 23.5k 23.5k 10k LSOUT-R 4.0V LSOUT right channel output pin.46 LSOUT-L 4.0V LSOUT left channel output pin.47 580 580 VCC

41 NC — —41

42 NC — —42

43 NC — —43

44 NC — —44

45 NC — —45

7.5k 4.5k × 5 7.5k VCC ↓ 35µ 2.1V × 2 SDA — Serial data I/O pin. VIH > 3.0V VIL< 1.5V

– 10– CXA2164Q

Electrical Characteristics

(100% modulation level) (Ta = 25°C, V CC = 9V) Item Current consumption Main output level Main de-emphasis frequency characteristic Main LPF frequency characteristic Main distortion Main overload distortion Main S/N Sub output level Sub LPF frequency characteristic Sub distortion Sub overload distortion Sub S/N Cross talk Stereo → SAP Cross talk SAP → Stereo No. Signal Icc Vmain FCdeem FCmain THDm THDmmax SNmain Vsub FCsub THDsub THDsmax SNsub CTst CTsap Mode MONO MONO MONO MONO MONO MONO ST ST ST ST ST SAP ST Input pin Min. 440 –1.2 –3.0 150 –3.0 Typ. 490 –1.0 0.1 0.15 190 –0.5 0.1 0.2 Max. 540 1.0 1.0 0.5 0.5 230 1.0 1.0 2.0 Unit mA mVrms dB dB dB mVrms dB dB dB dB Input signal No signal Mono 1kHz 100% mod. Pre-em. ON Mono 5kHz 30% mod. Pre-em. ON Mono 12kHz 30% mod. Pre-em. ON Mono 1kHz 100% mod. Pre-em. ON Mono 1kHz 200% mod. Pre-em. ON Mono 1kHz, Pre-em. ON SUB (L-R) 1kHz, 100% mod., NR OFF SUB (L-R) 12kHz, 30% mod., NR OFF SUB (L-R) 1kHz, 100% mod., NR OFF SUB (L-R) 1kHz, 200% mod., NR OFF SUB (L-R) 1kHz, NR OFF ST-L (R) 1kHz, 100% mod., NR ON, SAP Carrier (5f H ) SAP 1kHz 100% mod. NR ON, Pilot (fH ) Measurement conditions 20 log ('5k'/ '1k') 20 log ('12k'/ '1k') 20 log ('100%'/ '0%') 20 log ('12k'/ '1k') 20 log ('100%'/ '0%') 20 log ('NRSW = 0'/ 'NRSW = 1') 20 log ('NRSW = 1'/ 'NRSW = 0') Filter 15kLPF 15kLPF 15kLPF 15kLPF 15kLPF 15kLPF 1kBPF 1kBPF Output pin Main (L + R) (Pre-Emphasis: OFF) = 245mVrms SUB (L – R) (dbx-TV: OFF) = 490mVrms Pilot = 49mVrms SAP Carrier = 147mVrms fH = 15.734kHz

– 11– CXA2164Q No. Item Stereo ON level Stereo ON/OFF hysteresis SAP output level SAP LPF frequency characteristic SAP distortion SAP S/N SAP ON level SAP ON/OFF hysteresis ST separation 1 L → R ST separation 1 R → L ST separation 2 L → R ST separation 2 R → L LSOUT output level LSOUT mute attenuation LSOUT distortion LSOUT overload distortion LSOUT S/N LSOUT volume maximum attenuation Symbol THst HYst Vsap FCsap THDsap SNsap CTsap THsap HYsap STLsep1 STRsep1 STLsep2 Vtv MUls THDIs THDlsmax SNls VOLmin Mode ST SAP SAP SAP SAP SAP ST ST ST ST EXT EXT EXT EXT EXT EXT Input pin Min. –9.0 2.0 130 –3.0 –12.0 2.0 440 Typ. –6.0 6.0 160 2.5 –9.0 4.0 490 –90 0.01 0.03 –90 Max. –3.0 10.0 190 2.5 6.0 –6.5 6.0 540 –80 0.3 0.3 –80 Unit dB dB mVrms dB dB dB dB dB dB dB dB mVrms dB dB dB Input signal Change PILOT (f H ) Level SAP 1kHz 100% mod. NR OFF SAP 10kHz 30% mod. NR OFF SAP 1kHz 100% mod . NR OFF SAP 1kHz, NR OFF Change SAP Carrier (5fH ) Level ST-L 300Hz 30% mod. NR ON ST-R 300Hz 30% mod. NR ON ST-L 3kHz 30% mod. NR ON ST-R 3kHz 30% mod. NR ON Sine wave 1kHz, 490mVrms Sine wave 1kHz, 490mVrms Sine wave 1kHz, 490mVrms Sine wave 1kHz, 2Vrms Sine wave 1kHz, 490mVrms Sine wave 1kHz, 490mVrms Measurement conditions 0dB = 49mVrms 20 log (‘on level'/ 'off level') 20 log ('10k'/ '1k') 20 log ('100%'/ '0%') 0dB = 147mVrms 20 log (‘on level’/’off level’) EXT1 = '1' EXT1 = '1' M1 = '0' EXT1 = '1' EXT1 = '1' EXT1 = '1' EXT1 = '1' VOL-L = '0' VOL-R = '0' Filter 15kLPF 15kLPF 15kLPF 15kLPF 15kLPF 15kLPF 1kBPF 15kLPF 15kLPF 15kLPF 1kBPF Output pin BUS RETURN BUS RETURN

– 12– CXA2164Q Electrical Characteristics Measurement Circuit C21 4.7µ C23 4.7µ 10µ 25262728293036 31 VCATC VCAIN VEOUT VETC VEWGT NC NC NC VE SAPIN NC SAPOUT 3 4 5 6 7 8 10 11 SCL DGND MAININ NC NC NC COMPIN NC PCINT2 PCINT1 MAINOUT PLINT NC VGR NC GND SAPTC VCC SUBOUT STIN IREF NC NOISETC NC40

48 SDA

4.7µ C16 2700p 3.3kC12 3.3µ TANTALUM C13 0.047µ S3 BUFF FILTERS 15kHz LPF fH BPF 1kHz BPF MEASURES 4.7µ C24 4.7µ C17 4.7µ C22 100µ VCC GND GND 62k METAL ± 1% SIGNAL GENERATOR C20 10µ C14 5600p 1MEG 100k C15 0.012µ C11 4.7µ DGND I2C BUS DATA 220 220 21 12 C18 C19 4.7µ AC 35 34 3233 TANTALUM AC 4.7µ 4.7µ GND 3.9k 4.7µ AC

– 13– CXA2164Q Adjustment Method 1. ATT adjustment 1) TEST BIT is set to “TEST1 = 0” and “TEST-DA = 0”. 2) Input a 100Hz, 245mVrms sine wave signal to COMPIN and monitor the LSOUT-L output level. Then, adjust the “ATT ” data for ATT adjustment so that the LSOUT-L output goes to the standard value (490mVrms). 3) Adjustment range: ±20% Adjustment bits: 4 bits 2. Separation adjustment 1) TEST BIT is set to “TEST1 = 0” and “TEST-DA = 0”. 2) Set the unit to stereo mode and input the left channel only signal (modulation factor 30%, frequency 300Hz NR-ON) to COMPIN. At this time, adjust the “WIDEBAND ” adjustment data to reduce LSOUT-R output to the minimum. 3) Next, set the frequency only of the input signal to 3kHz and adjust the “SPECTRAL ” adjustment data to reduce LSOUT-R output to the minimum. 4) The adjustments in 2 and 3 above are performed to optimize the separation. 5) “WIDEBAND ”“ SPECTRAL ” Adjustment range: ±30% Adjustment range: ±15% Adjustment bits: 6 bits Adjustment bits: 6 bits Note)Adjust this IC through Tuner and IF when this IC is mounted in the set.

– 14– CXA2164Q SPECTRAL WIDEBAND ∗∗∗∗0000 ∗∗∗∗0001 ∗∗∗∗0010 ∗∗∗∗0011 ∗∗∗∗0100 ∗∗∗∗0101 SLAVE RECEIVER 84H (1000 0100) SLAVE TRANSMITTER 85H (1000 0101) Register Specifications Slave address Register table Status Registers DATASUB ADDRESS MSB LSB BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 TEST-DA TEST1 STA1 BIT7 POWER ON RESET STA2 BIT6 STEREO STA3 BIT5 SAP STA4 BIT4 NOISE STA5 BIT3 STA6 BIT2 STA7 BIT1 STA8 BIT0 ATT ∗ : Don't Care Note)The microcomputer reads both SAP and NOISE status and judges SAP discrimination. VOL-L VOL-R M1SAPCFOMONRSW∗EXT1

– 15– CXA2164Q Description of Registers Control registers ATT SPECTRAL WIDEBAND TEST-DA TEST1 EXT1 NRSW FOMO SAPC VOL-L VOL-R Input level adjustment Adjustment of stereo separation (3kHz) Adjustment of stereo separation (300Hz) DAC test mode Test mode Selection of TV mode or external input mode. Selection of the output signal (Stereo mode, SAP mode) Forced MONO (Left channel only is MONO during SAP output.) Selection of LSOUT mute function ON/OFF (0: mute ON, 1: mute OFF) Selection of SAP mode or L + R mode according to the presence of SAP broadcasting Left channel volume control Right channel volume control Register Contents A A A T T U U U U S U U Number of bits Classifi- cation∗ Standard setting ∗1 Classification U: User control A: Adjustment S: Proper to set T: Test Status registers PONRES STEREO SAP NOISE POWER ON RESET detection; 1: RESET Stereo discrimination of the COMPIN input signal; 1: Stereo SAP discrimination of the COMPIN input signal; 1: SAP Noise level discrimination of the SAP signal; 1: Noise Register Number of bits Contents

– 16– CXA2164Q Description of Control Registers ATT (4): Perform input level adjustment. 0 = Level min. F = Level max. SPECTRAL (6): Perform high frequency (fs = 3kHz) separation adjustment. 0 = Level max. 3F = Level min. WIDEBAND (6): Perform low frequency (fs = 300Hz) separation adjustment. 0 = Level min. 3F = Level max. TEST-DA (1): Set DAC output test mode. 0 = Normal mode 1 = DAC output test mode In addition, the following output are present at Pin 47. LSOUT-L (Pin 47): DA control DC level TEST1 (1): Monitor SAP BPF and NR BPF output. 0 = Normal mode 1 = SAP BPF and NR BPF output In addition, the following outputs are present at Pins 47 and 46. LSOUT-L (Pin 47): SAP BPF OUT LSOUT-R (Pin 46): NR BPF OUT EXT (1): Select TV mode or external input mode 0 = TV mode 1 = External input mode NRSW (1): Select stereo mode or SAP mode 0 = Stereo mode 1 = SAP mode FOMO (1): Select forced MONO mode 0 = Normal mode 1 = Forced MONO mode M1 (1): Mute the LSOUT-L and LSOUT-R output. 0 = Mute ON 1 = Mute OFF SAPC (1): Select the SAP signal output mode When there is no SAP signal, the conditions for selecting SAP output are selected by SAPC. 0 = L + R output is selected 1 = SAP output is selected

– 17– CXA2164Q VOL-L (6): LSOUT-L output signal level control 0 = Volume min. 3F = Volume max. –1.25dB/STEP VOL-R (6): LSOUT-R output signal level control 0 = Volume min. 3F = Volume max. –1.25dB/STEP

– 18– CXA2164Q Description of Mode Control NRSW FOMO SAPC “Select dbx input and TV decoder output” Conditions: FOMO = 0 NRSW = 0 (MONO or ST output)

• During ST input: left channel: L, right channel: R
• During other input: left channel: L + R, right channel: L + R NRSW = 1 (SAP output)
• When there is “SAP ” during SAP discrimination – left channel: SAP, right channel: SAP
• When there is “No SAP ”, output is the same as when NRSW = 0. “Select dbx input and TV decoder output” Conditions: FOMO = 0 NRSW = 0 (MONO or ST output) As on the left NRSW = 1 (SAP output)
• Regardless of the presence of SAP discrimination, dbx input: “SAP ” left channel: SAP, right channel: SAP However, when there is no SAP, SAPOUT output is soft muted (–7dB) Mode control SAPC = 0 SAPC = 1 “Forced MONO ” FOMO = 1
• During SAP output: left channel: L + R, right channel: SAP
• During ST or MONO output: left channel: L + R, right channel: L + R “MUTE ” M1 = 0: LSOUT-L, R output is muted. Change the selection conditions for “MONO or ST output” and “SAP output”. SAPC = 0: Switch to SAP output when there is SAP discrimination. Do not switch to SAP output when there is no SAP discrimination. SAPC = 1: Switch to SAP output regardless of whether there is SAP discrimination.

– 19– CXA2164Q Decoder Output and Mode Control Table 1 (SAPC = 1) Note (SAP) : The SAPOUT output signal is soft muted (approximately –7dB). The signal is soft muted when NOISE = 1. ∗ : Don’t care. ∗1 SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is inputted in the weak electric field. Then microcomputer reads "NOISE" status from IC and decides whether SAP is outputted. "NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN. 0000 ∗ 1 MUTE L + R L + R

000101 S A P S A P S A P

MONO 000111 S A P L + R S A P 0 ∗ 10 ∗ 1 MUTE L + R L + R 0 ∗ 1101 (SAP) (SAP) (SAP) 0 ∗ 1111 (SAP) L + R (SAP) 10 ∗ 001 L – RL R 10 ∗ 0 1 1 MUTE L + R L + R

111001 L – RL R

STEREO 111011 MUTE L + R L + R

100101 S A P S A P S A P

100111 S A P L + R S A P

1 ∗ 1101 (SAP) (SAP) (SAP) 1 ∗ 1111 (SAP) L + R (SAP) 01 ∗ 0 0 1 MUTE L + R L + R 01 ∗ 0 1 1 MUTE L + R L + R MONO & SAP 010101 S A P S A P S A P

010111 S A P L + R S A P

011101 (SAP) (SAP) (SAP) 011111 (SAP) L + R (SAP) 11 ∗ 001 L – RL R 11 ∗ 0 1 1 MUTE L + R L + R STEREO & SAP 110101 S A P S A P S A P

110111 S A P L + R S A P

111101 (SAP) (SAP) (SAP) 111111 (SAP) L + R (SAP) Input signal mode Mode detection Mode control dbx input Output ST SAP NOISE NRSW FOMO SAPC Lch Rch

– 20– CXA2164Q Decoder Output and Mode Control Table 2 (SAPC = 0) 00 ∗∗∗ 0 MUTE L + R L + R

011000 MUTE L + R L + R

MONO 011010 MUTE L + R L + R 011100 (SAP) (SAP) (SAP) 011110 (SAP) L + R (SAP) 10 ∗ 000 L – RL R 10 ∗ 0 1 0 MUTE L + R L + R 10 ∗ 100 L – RL R STEREO 10 ∗ 1 1 0 MUTE L + R L + R

111000 L – RL R

111010 MUTE L + R L + R

111100 (SAP) (SAP) (SAP) 111110 (SAP) L + R (SAP)

010000 MUTE L + R L + R

010010 MUTE L + R L + R

010100 S A P S A P S A P

MONO & SAP 010110 S A P L + R S A P

011010 MUTE L + R L + R

011100 (SAP) (SAP) (SAP) 011110 (SAP) L + R (SAP)

110000 L – RL R

110010 MUTE L + R L + R

110100 S A P S A P S A P

STEREO & SAP 110110 S A P L + R S A P 111100 (SAP) (SAP) (SAP) 111110 (SAP) L + R (SAP) Input signal mode Mode detection Mode control dbx input Output ST SAP NOISE NRSW FOMO SAPC Lch Rch Note (SAP) : The SAPOUT output signal is soft muted (approximately –7dB). The signal is soft muted when NOISE = 1. ∗ : Don’t care. ∗1 SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is inputted in the weak electric field. Then microcomputer reads "NOISE" status from IC and decides whether SAP is outputted. "NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.

– 21– CXA2164Q Description of Operation The US audio multiplexing system possesses the base band spectrum shown in Fig. 1. Fig. 1. Base band spectrum Fig. 2. Overall block diagram (See Fig. 3 for the dbx-TV block) Fig 3. dbx-TV block PEAK DEV kHz 25 25 L + R 50 – 15kHz L-R dbx-TV NR AM-DSB-SC SAP dbx-TV NR FM 10kHz 50 – 10kHz TELEMETRY FM 3kHz fH = 15.734kHz fH 2fH 3fH 4fH 5fH 6fH 6.5fH f PILOT (COMPIN) STEREO LPF PLL (VCO 8fH ) 2fHL 0° fHL 90° fHL 0° MODE CONTROL PILOT DET MVCA PILOT CANCEL MAIN LPF DE.EM (MAIN OUT) L + R 4.7µ (MAIN IN) L-R (DSB) DET INJ. LOCK SUBVCA SUB LPF WIDEBAND (SUBOUT) (ST IN) 4.7µ NR SW dbx-TV BLOCK MATRIX (Lch) (Rch) MODE CONTROL (SAP IN) 4.7µ SAP(FM) DET SAP LPF I C BUS DECODER MODE CONTROL SAP BPF (SAP OUT) L – R to TVSW NOISE DET I C BUS DECODER SAP DET I2C BUS DECODER A B 12 4 3 NR SW FIXED DEEMPHASIS VARIABLE DEEMPHASIS (VE OUT) (VCA IN) to MATRIX4.7µ HPF LPF LPF RMS DET RMS DET VCA A B (ST IN) (SAP IN) 3534

– 22– CXA2164Q (1) L + R (MAIN) After the audio multiplexing signal input from COMPIN (Pin 12) passes through MVCA, the SAP signal and telemetry signal are suppressed by STEREO LPF. Next, the pilot signals are canceled. Finally, the L – R signal and SAP signal are removed by MAIN LPF, and frequency characteristics are flattened (de-emphasized) and input to the matrix. (2) L – R (SUB) The L – R signal follows the same course as L + R before the pilot signal is canceled. L – R has no carrier signal, as it is a suppressed-carrier double-sideband amplitude modulated signal (DSB-AM modulated). For this reason, the pilot signal is used to regenerate the carrier signal (quasi-sine wave) to be used for the demodulation of the L – R signal. In the last stage, the residual high frequency components are removed by SUB LPF and the L – R signal is input to the dbx-TV block via the NRSW circuit after passing through SUBVCA. (3) SAP SAP is an FM signal using 5f H as a carrier as shown in the Fig. 1. First, the SAP signal only is extracted using SAP BPF. Then, this is subjected to FM detection. Finally, residual high frequency components are removed and frequency characteristics flattened using SAP LPF, and the SAP signal is input to the dbx-TV block via the NRSW circuit. When there is no SAP signal, the Pin 25 output is soft muted. (4) Mode discrimination Stereo discrimination is performed by detecting the pilot signal amplitude. SAP discrimination is performed by detecting the 5f H carrier amplitude. NOISE discrimination is performed by detecting the noise near 25kHz after FM detection of SAP signal. (5) dbx-TV block Either the L – R signal or SAP signal input respectively from ST IN (Pin 23) or SAP IN (Pin 27) is selected by the mode control and input to the dbx-TV block. The input signal then passes through the fixed de-emphasis circuit and is applied to the variable de- emphasis circuit. The signal output from the variable de-emphasis circuit passes through an external capacitor and is applied to VCA (voltage control amplifier). Finally, the VCA output is converted from a current to a voltage using an operational amplifier and then input to the matrix. The variable de-emphasis circuit transmittance and VCA gain are respectively controlled by Each of effective value detection circuits. Each of the effective value detection circuits passes the input signal through a predetermined filter for weighting before the effective value of the weighted signal is detected to provide the control signal. (6) Matrix, TVSW The signals (L + R, L – R, SAP) input to “MATRIX ” become the outputs for the ST-L, ST-R, MONO and SAP signals according to the mode control and whether there is ST / SAP discrimination. “TVSW ” switches the “MATRIX ” output signal and external input signal. (7) Others “MVCA ” is a VCA which adjusts the input signal level to the standard level of this IC. “Bias” supplies the reference voltage and reference current to the other blocks. The current flowing to the resistor connecting IREF (Pin 15) with GND become the reference current.

– 23– CXA2164Q Application Circuit 4.7µ 4.7µ 10µ 25262728293036 31 VCATC VCAIN VEOUT VETC VEWGT NC NC NC VE SAPIN NC SAPOUT 3 4 5 6 7 8 10 11 SCL DGND MAININ NC NC NC COMPIN NC PCINT2 PCINT1 MAINOUT PLINT NC VGR NC GND SAPTC VCC SUBOUT STIN IREF NC NOISETC NC40 4.7µ 2700p 3.3k 3.3µ TANTALUM 0.047µ 4.7µ 4.7µ 4.7µ 100µ GND 62k METAL ± 1% Composite baseband signal input 10µ 5600p 1MEG 100k 0.012µ 4.7µ DGND 220220 21 12 1µ 4.7µ 35 34 3233 TANTALUM 1µ3.9k +9V µ-com 4.7µAUX input 4.7µ 4.7µLS output Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 24– CXA2164Q I2C BUS block items (SDA, SCL) I2C BUS load conditions: Pull-up resistor 4kΩ (Connect to +5V) Load capacity 200pF (Connect to GND) High level input voltage Low level input voltage High level input current Low level input current Low level output voltage SDA (Pin 48) during 3mA inflow Maximum inflow current Input capacitance Maximum clock frequency Minimum waiting time for data change Minimum waiting time for start of data transfer Low level clock pulse width High level clock pulse width Minimum waiting time for start preparation Minimum data hold time Minimum data preparation time Rise time Fall time Minimum waiting time for stop preparation V IH VIL IIH IIL VOL IOL C I fSCL tBUF tHD : STA tLOW tHIGH tSU : STA tHD : DAT tSU : DAT tR tF tSU : STO 3.0 4.7 4.0 4.7 4.0 4.7 250 4.7 5.0 1.5 0.4 100 300 V µA V mA pF kHz µs ns µs ns µs No. Item Symbol Min. Typ. Max. Unit

– 25– CXA2164Q SDA SCL Start Condition S Stop Condition P HLH I Z L I2C BUS Signal There are two I2C signals, SDA (Serial DATA) and SCL (Serial CLOCK) signals. SDA is a bidirectional signal.

• Accordingly there are 3 values outputs, H, L and HIZ.
• I2C transfer begins with Start Condition and ends with Stop Condition. SDA SCL tBUF P S tHD : STA tLOW tHD : DAT tHIGH tR tF tHD : STA tSU : STA Sr tSU : STO PtSU : DAT I2C BUS Control Signal

– 26– CXA2164Q

• I2C data Write (Write from I2C controller to the IC) ∗ Data can be transferred in 8-bit units to be set as required. Sub address is incremented automatically.
• I2C data Read (Read from the IC to I2C controller)
• Read timing ∗ Data Read is performed during SCL rise. S Address 1 67891 89SCL ACK DATA ACK SDA H during Read HIZ P DATA 1 2 34 56789 9 IC output SDA SCL MSB LSB ACK ACK Read timing ACKACKDATA DATA P 891 89 HIZ HIZ DATA (n) DATA (n + 1)ACK 18 9 1 8 9 ACK DATA (n + 2) HIZ HIZ LSBMSB S Address 1234567891 89 SDA SCL MSB L during Write MSB LSB HIZ HIZ ACK Sub Address ACK

– 27– CXA2164Q Input level vs. Distortion characteristics 1 (MONO) Distortion [%] 1.0 0.1 –10 0 10 Input level vs. Distortion characteristics 2 (Stereo) Distortion [%] 1.0 –10 0 10 Input level [dB] Input signal: Stereo L = –R (dbx-TVNR ON), 1kHz 0dB = 100% modulation level V CC = 9V, 30kHz using LPF, ST mode Measurement point: LSOUT-L/R Input level vs. Distortion characteristics 3 (SAP) Distortion [%] 1.0 –10 0 10 Input level [dB] Input level [dB] Standard level (100%) Standard level (100%) Input signal: SAP (dbx-TVNR ON) 1kHz, 0dB = 100% modulation level V CC = 9V, 30kHz using LPF, SAP mode Measurement point: LSOUT-L/R Standard level (100%) Input signal: MONO (Pre-emphasis on), 1kHz 0dB = 100% modulation level V CC = 9V, 30kHz using LPF Measurement point: LSOUT-L/R

– 28– CXA2164Q Frequency [kHz] Gain [dB] Stereo LPF frequency characteristics –10 0 2 04 06 08 0 1 0 0 –20 –50 125 1 0 2 0 5 077 0 1 0 0 –40 –30 –10 Gain (FC main and FC sub) [dB] Frequency [kHz] Main LPF and Sub LPF frequency characteristics –20 20 40 60 80 100 120 –10 SAP frequency characteristics and group delay Group delay [µs] 100 5fH Gain Group delay 3.8fH 6.2fH Frequency [kHz] Gain [dB] 0F 1F Control data VOL-L, VOL-R 2F 3F –20 –40 –60 –80 –100 LSOUT output level [dB] Volume charactiristics Input: AUXIN (Pins 39, 40) 1kHz, 490mVrms Output: LSOUT (Pins 46, 47)

– 29– CXA2164Q Package Outline Unit: mm SONY CODE EIAJ CODE JEDEC CODE M PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 48PIN QFP (PLASTIC) 15.3 ± 0.4 12.0 – 0.1 + 0.4 0.8 0.3 – 0.1 + 0.15 0.24 2536 11 2 2.2 – 0.15 + 0.35 0.9 ± 0.2 0.1 – 0.1 + 0.2 13.5 0.15 – 0.05 + 0.1 QFP-48P-L04 QFP048-P-1212 0.7g 0.15 Sony Corporation