CXA2104S

CXA2104S SONY | Alldatasheet

Document overview

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• PDF pages: 28

Technical content

Features

• Adjustment free of VCO and filter.
• Audio multiplexing decoder and dbx noise reduction decoder are all included in a single chip. Almost any sort of signal processing is possible through this IC.
• All adjustments are possible through I 2C BUS to allow for automatic adjustment.
• Various built-in filter circuits greatly reduce external parts.
• There is an additional SAP output. Absolute Maximum Ratings(Ta = 25°C)
• Supply voltage V CC 11 V
• Operating temperature Topr –20 to +75 °C
• Storage temperature Tstg –65 to +150 °C
• Allowable power dissipation PD 1.35 W Range of Operating Supply Voltage 9 ± 0.5 V

Applications

TV, VCR and other decoding systems for US audio multiplexing TV broadcasting Structure Bipolar silicon monolithic IC * A license of the dbx-TV noise reduction system is required for the use of this device. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. TVOUT-R 2 3 4 5 6 7 8 9 10 11 12 13 14 151 161718192021222324252627282930 TVOUT-L SDA SCL DGND MAININ MAINOUT PCINT1 PCINT2 PLINT COMPIN VGR IREF GND SAPTC SOUT NC VCAWGT VCATC VCAIN VEOUT VETC VEWGT VE SAPIN SAPOUT NOISETCSTIN SUBOUT V CC Standard I/O Level

• Input level COMPIN (Pin 11) 100mVrms 245mVrms (Selected by INSW)
• Output level TVOUT-L/R (Pins 2 and 1) 490mVrms Pin Configuration (Top View)

– 2 – CXA2104S Block Diagram VGR IREF DGND SCL SDA SAPOUT SAPIN STIN VE VEWGT VETC VEOUT VCAIN VCAWGT VCATC MAININ MAINOUT SUBOUT PLINT PCINT1 C O M PIN VCC G N D N O ISETC SAPTC TVO U T-L IR EF SW LPF LPF H PF R M SD ET R M SD ET VC AVED eEm LO G IC M ATR IX VC A LPF LPF 1/21/4VC OLFLT STLPF VC A LPF BPF S A P V C O LPF N O ISE D ET SAPIN D "PO N R ES" STIN D "SAP" "N O ISE" N R SW /FO M O /SAPC W ID EBAN D SPEC TR AL "STER EO " D eEm FLT AM P (+4dB) I2C BU S I/F (+6dB) TVO U T-R PCINT2 SO U T ATT/IN SW LPF 67171098 12 13 5 4 3 20 21 18 22 23 24 25 26 28 27

– 3 – CXA2104S Pin Description (Ta = 25°C, VCC = 9V) 7.5k 4.5k × 5 7.5k VC C ↓ 35µ 2.1V × 2 7.5k ↓ 35µ 2.1V 10.5k × 4 VC C VC C 147 10k 53k VC C Pin No. Symbol Pin voltage Equivalent circuit Description SDA SCL DGND MAININ 4.0V Serial data I/O pin. VIH > 3.0V VIL< 1.5V Serial clock input pin. VIH > 3.0V VIL< 1.5V Digital block GND. Input the (L + R) signal from MAINOUT (Pin 7). TVOUT-R 4.0V TVOUT right channel output pin.1 TVOUT-L 4.0V TVOUT left channel output pin.2 580 580 VC C

– 4 – CXA2104S MAINOUT PCINT1 PCINT2 PLINT 4.0V 4.0V 4.0V 5.1V (L + R) signal output pin. Stereo block PLL loop filter integrating pin. Pilot cancel circuit loop filter integrating pin. (Connect a 1µF capacitor between this pin and GND.) VC C 147 15k 200µ VC C × 4 VC C 147 20k 26µ 20k 10k20k ↓ 50µ 20k20k 22k VC C 30k 147 VC C × 2 10k 10k 147 Pin No. Symbol Pin voltage Equivalent circuit Description

– 5 – CXA2104S COMPIN VGR IREF GND 4.0V 1.3V 1.3V Audio multiplexing signal input pin. Band gap reference output pin. (Connect a 10µF capacitor between this pin and GND.) Set the filter and VCO reference current. The reference current is adjusted with the BUS DATA based on the current which flows to this pin. (Connect a 62kΩ (±1%) resistor between this pin and GND.) Analog block GND. Set the time constant for the SAP carrier detection circuit. (Connect a 4.7µF capacitor between this pin and GND.) SAPTC 4.5V15 VC C 24k 34k 14k 147 24k 24k 10k VC C ↓ 50µ VC C 40k 40k 30k 30p 1.8k 16k 6.3k 147 30k 15k 30k VC C × 2 VC C × 4 11k 9.7k 19.4k 2.06k 3k 147 VC C 11k 11k Pin No. Symbol Pin voltage Equivalent circuit Description

– 6 – CXA2104S VCC SUBOUT STIN NOISETC 4.0V 4.0V 3.0V Supply voltage pin. (L–R) signal output pin. Input the (L-R) signal from SUBOUT (Pin 17). Set the time constant for the noise detection circuit. (Connect a 4.7µF capacitor between this pin and GND.) SAPIN 4.0V Input the (SAP) signal from SAPOUT (Pin 20).21 2k 2k 2k 4k 1k 14758014.4k 580 10P 2k2k Vcc 23k 147 18k 20k 11.7k 23k 147 18k VC C 18 21 3k3k 3.3k Vcc × 2 10k 1k 2k Vcc 200k Pin No. Symbol Pin voltage Equivalent circuit Description

– 7 – CXA2104S SAPOUT VE VETC 4.0V 4.0V 1.7V SAP FM detector output pin. Variable de-emphasis integrating pin. (Connect a 2700pF capacitor and a 3.3kΩ resistor in series between this pin and GND.) Determine the restoration time constant of the variable de-rmphasis control effective value detection circuit. (the specified restoration time constant can be obtained by connecting a 3.3µF capacitor between this pin and GND.) VEWGT 4.0V Weight the variable de-emphasis control effective value detection circuit. (Connect a 0.047µF capacitor and a 3kΩ resistor in series between this pin and GND.) 24k ↓ 10µ 580 Vcc 580 ↓ 50µ 10k 147 Vcc 36k 2.9V580 147 580 8k 30k ↓ 8µ ↓ 50µ 20k ↓ 7.5µ4k ↓ 50µ Vcc × 4 × 4 7.5k 147 VC C Pin No. Symbol Pin voltage Equivalent circuit Description

– 8 – CXA2104S VEOUT VCAIN VCAWGT 4.0V 4.0V 4.0V Variable de-emphasis output pin. (Connect a 4.7µF non-polar capacitor between Pins 25 and 26.) VCA input pin. Input the variable de-emphasis output signal from Pin 25 via a coupling capacitor. Weight the VCA control effective value detection circuit. (Connect a 1µF capacitor and a 3.9kΩ resistor in series between this pin and GND.) VCATC 1.7V Determine the restoration time constant of the VCA control effective value detection circuit. (the specified restoration time constant can be obtained by connecting a 10µF capacitor between this pin and GND.) Vcc 10k 580 580 VC C 30k 8k 36k 2.9V 580 580147 40k 40k 50µ 50µ VC C 4k 20k × 4 × 4 7.5µ VC C 20k VC C 47k 47k

29 NC — 29 —

No. Symbol Pin voltage Equivalent circuit Description

– 9 – CXA2104S SOUT 4.0V Additional SAP output pin.30 VC C 15k × 4 200µ Pin No. Symbol Pin voltage Equivalent circuit Description

– 10 – CXA2104S

Electrical Characteristics

(100% modulation level) (Ta = 25°C, VCC = 9V) = 245mVrms = 490mVrms = 49mVrms = 147mVrms = 100mVrms = 200mVrms = 20mVrms = 60mVrms Item Current consumption Main output level Main de-emphasis frequency characteristic Main LPF frequency characteristic Main distortion Main overload distortion Main S/N Sub output level Sub LPF frequency characteristic Sub distortion Sub overload distortion Sub S/N ST fi SAP Crosstalk No. Signal Icc Vmain FCdeem FCmain THDm THDmmax SNmain Vsub FCsub THDsub THDsmax SNsub CTst Mode MONO MONO MONO MONO MONO MONO ST ST ST ST ST SAP Input pin Min. 440 –1.2 –3.0 150 –3.0 Typ. 490 –1.0 0.1 0.15 190 –0.5 0.1 0.2 Max. 540 1.0 1.0 0.5 0.5 230 1.0 1.0 2.0 Unit mA mVrms dB dB dB mVrms dB dB dB Input signal No signal Mono 1kHz 100% mod. Pre-em. ON Mono 5kHz 30% mod. Pre-em. ON Mono 12kHz 30% mod. Pre-em. ON Mono 1kHz 100% mod. Pre-em. ON Mono 1kHz 200% mod. Pre-em. ON Mono 1kHz, Pre-em. ON SUB (L-R) 1kHz, 100% mod., NR OFF SUB (L-R) 12kHz, 30% mod., NR OFF SUB (L-R) 1kHz, 100% mod., NR OFF SUB (L-R) 1kHz, 200% mod., NR OFF SUB (L-R) 1kHz, NR OFF SUB (L-R) 1kHz, 100% mod., NR ON, SAP Carrier (5f H ) Measurement conditions 20 log ('5k'/'1k') 20 log ('12k'/'1k') 20 log ('100%'/'0%') 20 log ('12k'/'1k') 20 log ('100%'/'0%') 20 log ('NRSW = 0'/ 'NRSW = 1') Filter 15kLPF 15kLPF 15kLPF 15kLPF 15kLPF 15kLPF 1kBPF Output pin Main (L + R) (Pre-Emphasis: OFF) SUB (L – R) (dbx-TV: OFF) Pilot SAP Carrier INSW = 0 INSW = 1 fH = 15.734kHz

– 11 – CXA2104S No. Item Sub pilot leak Stereo ON level Stereo ON/OFF hysteresis SAP output level SAP LPF frequency characteristic SAP distortion SAP S/N SAP fi ST Cross talk SAP ON level SAP ON/OFF hysteresis ST separation 1 L fi R ST separation 1 R fi L ST separation 2 L fi R ST separation 2 R fi L Signal PCsub THst HYst Vsap FCsap THDsap SNsap CTsap THsap HYsap STLsep1 STRsep1 STLsep2 STRsep2 Mode ST ST SAP SAP SAP SAP ST SAP ST ST ST ST Input pin Min. –9.0 2.0 150 –3.0 –12.0 2.0 Typ. –42 –6.0 6.0 190 2.5 –9.0 4.0 Max. –30 –3.0 10.0 230 2.5 6.0 –6.5 6.0 Unit dB dB dB mVrms dB dB dB dB dB dB dB dB dB Input signal PILOT (fH ) 0dB Change PILOT (fH ) Level SAP 1kHz 100% mod. NR OFF SAP 10kHz 30% mod. NR OFF SAP 1kHz 100% mod . NR OFF SAP 1kHz, NR OFF SAP 1kHz 100% mod. NR ON, Pilot (fH ) Change SAP Carrier (5fH ) Level ST-L 300Hz 30% mod. NR ON ST-R 300Hz 30% mod. NR ON ST-L 3kHz 30% mod. NR ON ST-R 3kHz 30% mod. NR ON Measurement conditions 0dB = 49mVrms 0dB = 49mVrms 20 log (‘on level'/'off level') 20 log ('10k'/'1k') 20 log ('100%'/'0%') 20 log ('NRSW = 1'/'NRSW = 0') 0dB = 147mVrms 20 log (‘on level’/’off level’) Filter fH BPF 15kLPF 15kLPF 1kBPF 15kLPF 15kLPF 15kLPF 15kLPF Output pin BUS RETURN BUS RETURN

± 1% SIG N AL G EN ER ATO R AC C 10 5600p R 6 1M EG R 4 100k C 11 0.012µ C 7 4.7µ D G N D I2C BU S D ATA R 3 220 R 1 220 TVOUT-R 2 3 4 5 6 7 8 9 10 11 12 13 14 151 161718192021222324252627282930 TVOUT-L SDA SCL DGND MAININ MAINOUT PCINT1 PCINT2 PLINT COMPIN VGR IREF GND SAPTC SOUT NC VCAWGT VCATC VCAIN VEOUT VETC VEWGT VE SAPIN SAPOUT NOISETC STIN SUBOUT VCC C 1 4.7µ C 3 4.7µ C 15 4.7µ C 16 10µ C 13 C 19 4.7µ C 6 4.7µ C 20 100µC 14 4.7µ C 18 4.7µ C 17 4.7µ C 12 2700P R 7 3.3k C 9 0.047µ R 5 3kC 8 3.3µ TANTALUM C 4 R 2 3.9k C 5 10µ C 2 4.7µ TANTALUM – 12 – CXA2104S Electrical Characteristics Measurement Circuit

– 13 – CXA2104S Adjustment Method (This is the case when standard input level is 245mVrms.) 1.ATT adjustment 1) TEST BIT is set to “TEST1 = 0” and “TEST-DA = 0”. 2) Input a 100Hz, 245mVrms sine wave signal to COMPIN and monitor the TVOUT-L output level. Then, adjust the “ATT” data for ATT adjustment so that the TVOUT-L output goes to the standard value (490mVrms). 3) Adjustment range:±30% Adjustment bits:4 bits 2.Separation adjustment 1) TEST BIT is set to “TEST1 = 0” and “TEST-DA = 0”. 2) Set the unit to stereo mode and input the left channel only signal (modulation factor 30%, frequency 300Hz NR-ON) to COMPIN. At this time, adjust the “WIDEBAND” adjustment data to reduce TVOUT-R output to the minimum. 3) Next, set the frequency only of the input signal to 3kHz and adjust the “SPECTRAL” adjustment data to reduce TVOUT-R output to the minimum. 4) The adjustments in 2 and 3 above are performed to optimize the separation. 5) “WIDEBAND” “SPECTRAL” Adjustment range:±30% Adjustment range:±15% Adjustment bits:6 bits Adjustment bits:6 bits * Adjust this IC through Tuner and IF when this IC is mounted in the set.

– 14 – CXA2104S Description of Operation The US audio multiplexing system possesses the base band spectrum shown in Fig. 1. Fig. 1. Base band spectrum Fig. 2. Overall block diagram (See Fig. 3 for the dbx-TV block) Fig 3. dbx-TV block PEAK D EV kH z 25 25 L + R 50 – 15kH z L-R dbx-TV N R AM -D SB-SC SAP dbx-TV N R FM 10kH z 50 – 10kH z TELEM ETR Y FM 3kH z fH = 15.734kH z fH 2fH 3fH 4fH 5fH 6fH 6.5fH f PILOT (C O M PIN ) STER EO LPF PLL (VC O 8fH ) 2fH L0° fH L90° fH L0° M O D E C O N TR O L PILO T D ET M VC A PILO T C AN C EL M AIN LPF D E.EM (M AIN O U T) L + R 4.7µ (M AIN IN ) L-R (D SB) D ET IN J. LO C K SU BVC A SU B LPF W ID EBAN D (SU BO U T) (ST IN ) 4.7µ N R SW dbx-TV BLO C K M ATR IX (Lch) (R ch) M O D E C O N TR O L (SAP IN ) 4.7µ SAP (FM ) D ET SAP LPF M O D E C O N TR O L SAP BPF (SAP O U T) L – R to TVSW N O ISE D ET I C BU S D EC O D ER SAP D ET A B I C BU S D EC O D ER I C BU S D EC O D ER 11 7 6 17 18 20 21 LPF (SO U T) N R SW FIXED D EEM PH ASIS VAR IABLE D EEM PH ASIS (VE O U T) (VC A IN ) to M ATR IX4.7µ H PF LPF LPF R M S D ET R M S D ET VC A A B (ST IN ) (SAP IN ) 25 26

– 15 – CXA2104S (1) L + R (MAIN) After the audio multiplexing signal input from COMPIN (Pin 11) passes through MVCA, the SAP signal and telemetry signal are suppressed by STEREO LPF. Next, the pilot signals are canceled. Finally, the L – R signal and SAP signal are removed by MAIN LPF, and frequency characteristics are flattened (de-emphasized) and input to the matrix. (2)L – R (SUB) The L – R signal follows the same course as L + R before the pilot signal is canceled. L – R has no carrier signal, as it is a suppressed-carrier double-sideband amplitude modulated signal (DSB-AM modulated). For this reason, the pilot signal is used to regenerate the carrier signal (quasi-sine wave) to be used for the demodulation of the L – R signal. In the last stage, the residual high frequency components are removed by SUB LPF and the L – R signal is input to the dbx-TV block via the NRSW circuit after passing through SUBVCA. (3)SAP SAP is an FM signal using 5f H as a carrier as shown in the Fig. 1. First, the SAP signal only is extracted using SAP BPF. Then, this is subjected to FM detection. Finally, residual high frequency components are removed and frequency characteristics flattened using SAP LPF, and the SAP signal is input to the dbx-TV block via the NRSW circuit. When there is no SAP signal, the Pin 20 output is soft muted. (4)Mode discrimination Stereo discrimination is performed by detecting the pilot signal amplitude. SAP discrimination is performed by detecting the 5f H carrier amplitude. NOISE discrimination is performed by detecting the noise near 25kHz after FM detection of SAP signal. (5)dbx-TV block Either the L – R signal or SAP signal input respectively from ST IN (Pin 18) or SAP IN (Pin 21) is selected by the mode control and input to the dbx-TV block. The input signal then passes through the fixed de-emphasis circuit and is applied to the variable de- emphasis circuit. The signal output from the variable de-emphasis circuit passes through an external capacitor and is applied to VCA (voltage control amplifier). Finally, the VCA output is converted from a current to a voltage using an operational amplifier and then input to the matrix. The variable de-emphasis circuit transmittance and VCA gain are respectively controlled by Each of effective value detection circuits. Each of the effective value detection circuits passes the input signal through a predetermined filter for weighting before the effective value of the weighted signal is detected to provide the control signal. (6)Matrix The signals (L + R, L – R, SAP) input to “MATRIX” become the outputs for the ST-L, ST-R, MONO and SAP signals according to the mode control and whether there is ST / SAP discrimination. (7) Others “MVCA” is a VCA which adjusts the input signal level to the standard level of this IC. “Bias” supplies the reference voltage and reference current to the other blocks. The current flowing to the resistor connecting IREF (Pin 13) with GND become the reference current.

– 16 – CXA2104S SPECTRAL (6) WIDEBAND (6) **0000 0001 0010 0011 **0100 SLAVE RECEIVER 84H (1000 0100) SLAVE TRANSMITTER 85H (1000 0101) Register Specifications Slave address Register table Status Registers DATASUB ADDRESS MSB LSB BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 TEST-DA DATA1 INSW TEST1 DATA2 DATA5 NRSW ATTSW FOMO FST SAPC DATA3 DATA4 STA1 BIT7 POWER ON RESET STA2 BIT6 STEREO STA3 BIT5 SAP STA4 BIT4 NOISE STA5 BIT3 STA6 BIT2 STA7 BIT1 STA8 BIT0 ATT (4) * : Don't Care

– 17 – CXA2104S Description of Registers Control registers ATT SPECTRAL WIDEBAND TEST-DA TEST1 FST NRSW FOMO ATTSW INSW SAPC DATA1 DATA2 DATA3 DATA4 DATA5 Input level adjustment Adjustment of stereo separation (3kHz) Adjustment of stereo separation (300Hz) Turn to DAC test mode by meansof TEST-DA = 1. Turn to test mode by means of TEST = 1. Turn to forced stereo by means of FST = 1. Selection of the output signal (Stereo mode, SAP mode) Turn to forced MONO by means of FOMO = 1. (Left channel only is MONO during SAP output.) Selection of TVOUT mute ON/OFF (0: mute ON, 1: mute OFF) Turn the input stage MVCA off when ATTSW = 1. Selection of standard input level Selection of SAP mode or L + R mode according to the presence of SAP broadcasting Test mode (Normal standard setting value) Register Contents A A A T T T U U U S S S T T T T T Number of bits Classifi- cation* Standard setting *1 ClassificationU: User control A: Adjustment S: Proper to set T: Test Status registers PONRES STEREO SAP NOISE POWER ON RESET detection; 1: RESET Stereo discrimination of the COMPIN input signal; 1: Stereo SAP discrimination of the COMPIN input signal; 1: SAP Noise level discrimination of the SAP signal; 1: Noise Register Number of bits Contents

– 18 – CXA2104S Description of Control Registers ATT (4): Adjust the signal level input to COMPIN (Pin 11) to the standard input level. Variable range of the input signal:standard input level –5.0dB to +3.0dB 0 = Level min. F = Level max. SPECTRAL (6): Perform high frequency (fs = 3kHz) separation adjustment. 0 = Level max. 3F = Level min. WIDEBAND (6): Perform low frequency (fs = 300Hz) separation adjustment. 0 = Level min. 3F = Level max. TEST-DA (1):Set DAC output test mode. 0 = Normal mode 1 = DAC output test mode In addition, the following output are present at Pin 2. TVOUT-L (Pin 2): DA control DC level TEST1 (1): Monitor SAPBPF and NRBPF output 0 = Normal mode 1 = SAPBPF, NRBPF output In addition, the following outputs are present at Pins 1 and 2. TVOUT-L (Pin 2): SAP BPF OUT TVOUT-R (Pin 1): NR BPF OUT FST (1): Select forced STEREO mode 0 = Normal mode 1 = Forced stereo mode NRSW (1): Select stereo mode or SAP mode 0 = Stereo mode 1 = SAP mode

– 19 – CXA2104S FOMO (1): Select forced MONO mode 0 = Normal mode 1 = Forced MONO mode M1 (1): Mute the TVOUT-L and TVOUT-R output. 0 = Mute ON 1 = Mute OFF ATTSW (1) Select BYPASS SW of MVCA 0 = Normal mode 1 = MVCA is passed INSW (1): Select standard input level of COMPIN (Pin 11). 0 = 245mVrms 1 = 100mVrms SAPC (1): Select the SAP signal output mode When there is no SAP signal, the conditions for selecting SAP output are selected by SAPC. 0 = L + R output is selected 1 = SAP output is selected

– 20 – CXA2104S Description of Mode Control NRSW FOMO SAPC “Select dbx input and TV decoder output” Conditions: FOMO = 0 NRSW = 0 (MONO or ST output)

• During ST input: left channel: L, right channel: R
• During other input: left channel: L + R, right channel: L + R NRSW = 1 (SAP output)
• When there is “SAP” during SAP discrimination – left channel: SAP, right channel: SAP
• When there is “No SAP”, output is the same as when NRSW = 0. “Select dbx input and TV decoder output” Conditions: FOMO = 0 NRSW = 0 (MONO or ST output) As on the left NRSW = 1 (SAP output)
• Regardless of the presence of SAP discrimination, dbx input: “SAP” left channel: SAP, right channel: SAP However, when there is no SAP, SAPOUT output is soft muted (–7dB) Mode control SAPC = 0 SAPC = 1 “Forced MONO” FOMO = 1
• During SAP output: left channel: L + R, right channel: SAP
• During ST or MONO output: left channel: L + R, right channel: L + R Change the selection conditions for “MONO or ST output” and “SAP output”. SAPC = 0: Switch to SAP output when there is SAP discrimination. Do not switch to SAP output when there is no SAP discrimination. SAPC = 1: Switch to SAP output regardless of whether there is SAP discrimination. “MUTE” M1 = 0: TVOUT output is muted.

– 21 – CXA2104S Decoder Output and Mode Control Table 1 (SAPC = 1) Note (SAP) :The SAPOUT output signal is soft muted (approximately –7dB). The signal is soft muted when NOISE = 1. * :Don’t care. *1 SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is inputted in the weak electric field. Then microcomputer reads "NOISE" status from IC and decides whether SAP is outputted. "NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN. 0 0 0 0 * 1 MUTE L + R L + R 0 0 0 1 0 1 SAP SAP SAP MONO 0 0 0 1 1 1 SAP L + R SAP 0 * 1 0 * 1 MUTE L + R L + R 0 * 1 1 0 1 (SAP) (SAP) (SAP) 0 * 1 1 1 1 (SAP) L + R (SAP) 1 0 * 0 0 1 L – R L R 1 0 * 0 1 1 MUTE L + R L + R 1 1 1 0 0 1 L – R L R STEREO 1 1 1 0 1 1 MUTE L + R L + R 1 0 0 1 0 1 SAP SAP SAP 1 0 0 1 1 1 SAP L + R SAP 1 * 1 1 0 1 (SAP) (SAP) (SAP) 1 * 1 1 1 1 (SAP) L + R (SAP) 0 1 * 0 0 1 MUTE L + R L + R 0 1 * 0 1 1 MUTE L + R L + R MONO & SAP 0 1 0 1 0 1 SAP SAP SAP 0 1 0 1 1 1 SAP L + R SAP 0 1 1 1 0 1 (SAP) (SAP) (SAP) 0 1 1 1 1 1 (SAP) L + R (SAP) 1 1 * 0 0 1 L – R L R 1 1 * 0 1 1 MUTE L + R L + R STEREO & SAP 1 1 0 1 0 1 SAP SAP SAP 1 1 0 1 1 1 SAP L + R SAP 1 1 1 1 0 1 (SAP) (SAP) (SAP) 1 1 1 1 1 1 (SAP) L + R (SAP) Input signal mode Mode detection Mode control dbx input Output ST SAP NOISE NRSW FOMO SAPC Lch Rch

– 22 – CXA2104S Decoder Output and Mode Control Table 2 (SAPC = 0) 0 0 * * * 0 MUTE L + R L + R 0 1 1 0 0 0 MUTE L + R L + R MONO 0 1 1 0 1 0 MUTE L + R L + R 0 1 1 1 0 0 (SAP) (SAP) (SAP) 0 1 1 1 1 0 (SAP) L + R (SAP) 1 0 * 0 0 0 L – R L R 1 0 * 0 1 0 MUTE L + R L + R 1 0 * 1 0 0 L – R L R STEREO 1 0 * 1 1 0 MUTE L + R L + R 1 1 1 0 0 0 L – R L R 1 1 1 0 1 0 MUTE L + R L + R 1 1 1 1 0 0 (SAP) (SAP) (SAP) 1 1 1 1 1 0 (SAP) L + R (SAP) 0 1 0 0 0 0 MUTE L + R L + R 0 1 0 0 1 0 MUTE L + R L + R 0 1 0 1 0 0 SAP SAP SAP MONO & SAP 0 1 0 1 1 0 SAP L + R SAP 0 1 1 0 0 0 MUTE L + R L + R 0 1 1 0 1 0 MUTE L + R L + R 0 1 1 1 0 0 (SAP) (SAP) (SAP) 0 1 1 1 1 0 (SAP) L + R (SAP) 1 1 0 0 0 0 L – R L R 1 1 0 0 1 0 MUTE L + R L + R 1 1 0 1 0 0 SAP SAP SAP STEREO & SAP 1 1 0 1 1 0 SAP L + R SAP 1 1 1 0 0 0 L – R L R 1 1 1 0 1 0 MUTE L + R L + R 1 1 1 1 0 0 (SAP) (SAP) (SAP) 1 1 1 1 1 0 (SAP) L + R (SAP) Input signal mode Mode detection Mode control dbx input Output ST SAP NOISE NRSW FOMO SAPC Lch Rch Note (SAP) :The SAPOUT output signal is soft muted (approximately –7dB). The signal is soft muted when NOISE = 1. * :Don’t care. *1 SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is inputted in the weak electric field. Then microcomputer reads "NOISE" status from IC and decides whether SAP is outputted. "NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.

– 23 – CXA2104S I2C BUS block items (SDA, SCL) I2C BUS load conditions:Pull-up resistor 4kΩ (Connect to +5V) Load capacity 200pF (Connect to GND) I2C BUS Control Signal High level input voltage Low level input voltage High level input current Low level input current Low level output voltage SDA (Pin 3) during 3mA inflow Maximum inflow current Input capacitance Maximum clock frequency Minimum waiting time for data change Minimum waiting time for start of data transfer Low level clock pulse width High level clock pulse width Minimum waiting time for start preparation Minimum data hold time Minimum data preparation time Rise time Fall time Minimum waiting time for stop preparation V IH VIL IIH IIL VOL IOL C I fSCL tBUF tHD : STA tLOW tHIGH tSU : STA tHD : DAT tSU : DAT tR tF tSU : STO 3.0 4.7 4.0 4.7 4.0 4.7 250 4.7 5.0 1.5 0.4 100 300 V µA V mA pF kHz µs ns µs ns µs SD A SC L tBU F P S tH D : STA tLO W tH D : D AT tH IG H tR tF tH D : STA tSU : STA Sr tSU : STO PtSU : D AT No. Item Symbol Min. Typ. Max. Unit

– 24 – CXA2104S I2C BUS Signal There are two I2C signals, SDA (Serial DATA) and SCL (Serial CLOCK) signals. SDA is a bidirectional signal.

• Accordingly there are 3 values outputs, H, L and HIZ.
• I2C transfer begins with Start Condition and ends with Stop Condition. SD A SC L Start C ondition S Stop C ondition P H L H IZ L

– 25 – CXA2104S

• I2C data Write (Write from I2C controller to the IC) * Data can be transferred in 8-bit units to be set as required. Sub address is incremented automatically.
• I2C data Read (Read from the IC to I2C controller)
• Read timing * Data Read is performed during SCL rise. S Address 1 6 7 8 9 1 8 9SC L AC K D ATA AC K SD A H during R ead H IZ P D ATA 1 2 3 4 5 6 7 89 9 IC output SD A SC L M SB LSB AC K AC K R ead tim ing AC KAC KD ATA D ATA P 8 9 1 8 9 H IZ H IZ D ATA (n) D ATA (n+1)AC K 1 8 9 1 8 9 AC K D ATA (n + 2) H IZ H IZ LSBM SB S Address 1 2 3 4 5 6 7 8 9 1 8 9 SD A SC L M SB L during W rite M SB LSB H IZ H IZ AC K Sub Address AC K

– 26 – CXA2104S Input level vs. D istortion characteristics 1 (M O N O ) Distortion [% 1.0 0.1 –10 0 10 Input level vs. D istortion characteristics 2 (Stereo) Distortion [% 1.0 –10 0 10 Input level [dB] Input signal: Stereo L = –R (dbx-TVN R O N ), 1kH z 0dB = 100% m odulation level VC C = 9V, 30kH z using LPF, ST m ode M easurem ent point: TVO U T-L/R Input level vs. D istortion characteristics 3 (SA P) Distortion [% 1.0 –10 0 10 Input level [dB] Input level [dB] Standard level (100% ) Standard level (100% ) Input signal: SAP (dbx-TVN R O N ) 1kH z, 0dB = 100% m odulation level VC C = 9V, 30kH z using LPF, SAP m ode M easurem ent point: TVO U T-L/R Standard level (100% ) Input signal: M O N O (Pre-em phasis on), 1kH z 0dB = 100% m odulation level VC C = 9V, 30kH z using LPF M easurem ent point: TVO U T-L/R

– 27 – CXA2104S Frequency [kH z] Gain [dB] Stereo LPF frequency characteristics –10 0 20 40 60 80 100 –20 –50 1 2 5 10 20 507 70 100 –40 –30 –10 Gain (FC m ain and FC sub) [dB] Frequency [kH z] M ain LPF and Sub LPF frequency characteristics –20 20 40 60 80 100 120 –10 SA P frequency characteristics and group delay Group delay [µs] 100 5fH G ain G roup delay 3.8fH 6.2fH Frequency [kH z] Gain [dB] Frequency [kH z] A dditional SA P frequency characteristics Output level [m Vrm 500 100 1.0 10 100% m odulation 30% m odulation 10% m odulation 1% m odulation 0.1

– 28 – CXA2104S Package Outline Unit: mm SO N Y C O D E EIAJ C O D E JED EC C O D E 30PIN SD IP (PLASTIC ) 26.9 – 0.1 + 0.4 1630 1.778 10.16 8.5 – 0.1 + 0.3 0.25 – 0.05 + 0.1 0° to 15° 0.5 ± 0.1 0.9 ± 0.15 3.0 M IN 0.5 M IN 3.7 – 0.1 + 0.4 SD IP-30P-01 SD IP030-P-0400 PAC KAG E STR U C TU R E M O LD IN G C O M PO U N D LEAD TR EATM EN T LEAD M ATER IAL PAC KAG E M ASS EPO XY R ESIN PLATIN G C O PPER ALLO Y 1.8g SO LD ER /PALLAD IU M 1.All m at surface type. Tw o kinds of package surface: 2.All m irror surface type. N O TE : PALLAD IU M PLATIN G This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Fram e).