CXA2096

CXA2096N SONY | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 16

Technical content

Features

• High sensitivity made possible by a high-gain AGC amplifier
• Blanking function provided for the purpose of calibrating the CCD output signal black level
• Regulator output pin provided for A/D converter reference voltage
• Built-in sample-and-hold circuits for camera signals required by external A/D converters Absolute Maximum Ratings
• Supply voltage V CC 11 V
• Operating temperature Topr –20 to +75 °C
• Storage temperature Tstg –65 to +150 °C
• Allowable power dissipation PD 417 mW Operating Conditions Supply voltage V CC 1, 2, 3 3.0 to 3.6 V

Applications

DVC/still cameras for consumer use Structure Bipolar silicon monolithic IC – 1 – E97449B8Y Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. CXA2096N 24 pin SSOP (Plastic)

– 2 – CXA2096N Block Diagram and Pin Configuration BU F VR T D M SW 1 9 10 11 12 13141516 2 3 4 5 6 7 81 1718192021222324 C D S C LP1 AG C SH 3 D M SW 2 C AM SH PO W ER SAVE C O N T SH 1 SH 2 D C SH IFT VR T D R V VR B D R V VR BD R V VR EF C D S C LP2 AG C C LP O B SW O FFSET BLK SW ICONT V CC2 DIN PIN CLPDM GND1 SHD SHP V CC1 CCDLEVEL AGCCONT AGCCLP GND2 PS GND3 DRVOUT V CC3 N.C. VRB VRT OFFSET PBLK XRS CLPOB

– 3 – CXA2096N Pin Description (VCC 1, 2, 3 = 3V) 2 PS Power saving mode. GND2 GND3 GND1 Ground. VTH = 1.5V GND 145 5k10µA 1.5V 60k 30k

4 DRVOUT

DC coupling. Dynamic range = 1Vp-p. V RB to VRB + 100mV V CC 3 VCC 1 VCC 2 Power supply.VCC C AM signal 50µA 145 IC O N T 3.2 to 6.4m A 200µA 50µA 25µA25µA IO FFSET 0 to 50µA VR B = 1.35V Pin No. Symbol Pin voltage Equivalent circuit Description

– 4 – CXA2096N

7 VRB

1.35V regulator output. Be sure to decouple this pin near the IC pins to prevent the oscillation and external noise when this pin is not used. (Recommended capacitor value: 4.7µF) 1.35V 2.35V8 VRT 2.35V regulator output. Be sure to decouple this pin near the IC pins to prevent the oscillation and external noise when this pin is not used. (Recommended capacitor value: 4.7µF) 200 30k 16.5k 13.5k 145 1.35V 110µA 30k 6.5k 23.5k 145 2.35V 220µ 55µ55µ 200

9 OFFSET

offset. When 3V: VRB When 1.5V: VRB + 100mV When 0V (preset mode): V RB + 35mV 1.5 to 3V 2k30k 30k 50k 50k 1.5k 3k 25k VR B 145 50µA 50µA 50µA 1.85V

10 PBLK

input. Active when Low. Calibrates the black level of the AGC output waveform. When PBLK is Low, the DRVOUT potential is forced to V RB . VTH = 1.85V 145 50µA 30k 30k 1.85V 30k Active: Low 6 N.C. No connection; normally ground. Pin No. Symbol Pin voltage Equivalent circuit Description

– 5 – CXA2096N

11 XRS

pulse input. VTH = 0.68V 24k 0.68V 770µA40µA 97µ 145

12 CLPOB

AGC amplifier. VTH = 1.5V 145 50µA 30k 30k 1.5V 30k Sam pling Active: Low

13 AGCCLP

AGC clamp capacitor. (Recommended value: 0.1µF) Approx. 1.3V AGCCONT AGC gain control. When 1.5V: –1dB (Minimum gain) When 3.0V: 31.5dB (Maximum gain) 1.5 to 3.0V 50k 145 145 5k5k 3k 145 200µA 3.4k 3.4k 200µA 2.14V 100µA300µA 300µA 100µA 2.29V IC O N T 3.4k 3.4k 3.3k 3.3k Pin No. Symbol Pin voltage Equivalent circuit Description

– 6 – CXA2096N Pin No. Symbol Pin voltage Equivalent circuit Description

15 CCDLEVEL

camera signal. CCD signal black level of DIN input approx. 2.2V

17 SHP Preset level sample-

and-hold pulse input.

18 SHD Data level sample-

and-hold pulse input. VTH = 0.65V 500 340 100µA 36k 10k 0.65V 365µA20µA 145 Sam pling

20 CLPDM

input CCD signal. VTH = 1.5V 145 50µA 30k 30k 1.5V 20 PIN DIN ICONT CCD signal input. DRVOUT output waveform rise time control. When 1.5V:Maximum rise time When 3V: Minimum rise time Black level approx. 2.1V 1.5 to 3V 145 145 200µA 50µA 23k 7k14k 15µA 15µA 145 100µA 15k 45k 6k6k 2.25V 24 Active: Low

– 7 – CXA2096N Electrical Characteristics (Ta = 25°C, VCC 1, 2, 3 = 3V) PS = OFF (PS indicates Power Save) PS = ON Maximum gain Minimum gain Range of gain variance Dynamic range maximum Dynamic range typical Offset high Offset low Offset preset V RT DC level VRB DC level VRT – VRG Offset Dynamic range I DC IDP A CONT max. A CONT min. AGC G AGCmax. D AGC TYP . D CAOF high CAOF low CAOF pre VRTO VRBO ∆VR BLKOF SH3 D AGCCONT = 1.5V, open between VRT and VRB PS = 3V, ICONT = 3V PS = 0V DIN = 1µs, 20mVp-p pulse AGCCONT = 3V, ICONT = 3V DIN = 1µs, 500mVp-p pulse AGCCONT = 1.5V, ICONT = 3V A CON max. – A CON min. AGCCONT = 3V DRVOUT output signal at saturation level AGCCONT = 2V DRVOUT output signal at saturation level OFFSET = 1.5V OFFSET = 3.0V OFFSET = 0V With a 400Ω load With a 400Ω load With a 400Ω load BLKOF (PBLK = 3V) – BLKOF (PBLK = 0V) DIN = 1µs, 1Vp-p pulse Item Symbol Conditions Min. Typ. Max. Unit Current consump -tion AGC DRV mA dB mV mV mV mV REF BLK 25.1 28.5 27.1 800 900 2300 1300 950 –15 600 37.1 1.8 31.3 –0.8 32.1 970 960 2340 1353 988 790 49.0 4.2 1.4 2400 1400 1050 — mVSH3

– 8 – CXA2096N Electrical Characteristics Measurement Circuit BU F VR T D M SW 1 9 10 11 12 13141516 2 3 4 5 6 7 81 1718192021222324 C D S C LP1 AG C SH 3 D M SW 2 C AM SH PO W ER SAVE C O N T SH 1 SH 2 D C SH IFT VR T D R V VR B D R V VR BD R V VR EF C D S C LP2 AG C C LP O B SW O FFSET BLK SW ICONT V CC2 DIN PIN GND1 SHD SHP V CC1 CCDLEVEL AGCCONT AGCCLP GND2 PS GND3 DRVOUT V CC3 N.C. VRB VRT OFFSET PBLK XRS CLPOB L H SW 1 C 3 0.1µF 1.5 to 3V VC C 1 PL3PL2PL1 C 2 1µF C 1 1µF AC VC C 2 1.5 to 3V G N DPL4PL5PL6 0 to 3VC 4 4.7µ C 5 4.7µ SW 2 VC C 3 C 6 40pF R 2 R 3 10k 1.85V CLPDM R 1 400 SW1 H L POWER SAVE OFF ON

– 9 – CXA2096N Measurement Timing Chart D ifferent for each test 2.5V G N D 2.5V G N D 2.5V G N D 2.5V G N D 2µs 2µs Equivalent to C C D signal black level PL4 (C LPO B) PL1 (C LPD M ) PL6 (PBLK) V2 (D IN ) PL2 (SH D ) PL3 (SH P) PL5 (XR S)

– 10 – CXA2096N Application Circuit VAG C C O N T 1.5 to 3V BU F VR T D M SW 1 9 10 11 12 13141516 2 3 4 5 6 7 81 1718192021222324 C D S C LP1 SH 3 D M SW 2 C AM SH PO W ER SAVE C O N T SH 1 SH 2 D C SH IFT VR T D R V VR B D R V VR BD R V VR EF C D S C LP2 AG C C LP O B SW O FFSET BLK SW ICONT V CC2 DIN PIN GND1 SHD SHP V CC1 CCDLEVEL AGCCONT AGCCLP GND2 PS GND3 DRVOUT V CC3 N.C. VRB VRT OFFSET PBLK XRS CLPOB 0.1µF SH PSH DC LPD M 1µF1µF VIC O N T 1.5 to 3V C LPO BXR SPBLKVO FFSET 0 to 3V 4.7µF 4.7µ VC C C C D VC C VC C VR B A/D IN A/D VR T G N D CLPDM AG C Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 11 – CXA2096N Description of Operation Refer to the Block Diagram. Operating Conditions The camera signal processing system operates when PS is High. Timing Chart (when VCC = 3V) PBLK (10µ during the idle transfer interval) Signal interval O PB interval Signal interval Precharge level Signal level 2.1V 2.1V [∗1] [∗2] 2µs 0.65V Black levelBasic black level [∗3] 2µs 0.65V 10µs 1.35V [∗4] [∗5] Approx. VR B + 35m V w hen O FFSET = 0V Approx. VR B + 100m V w hen O FFSET = 1.5V Applox. VR B w hen O FFSET = 3V C C D output SH P SH D SH 1 output SH 2 output SH 3 output C LPD M (2µ dum m y bit portion during the idle transfer interval) XR S C LPO B (2µ during the O PB interval) C AM SH output BLK SW output D R VO U T output AG C output SH 3 output –SH 2 output × (–N ) Idle transfer interval

– 12 – CXA2096N CDS (SH1, SH2, SH3): The CCD signal from the CCD image sensor is input to PIN and DIN where correlated double sampling (CDS) is performed by SH1, SH2 and SH3. The precharge level of the CCD output signal is sampled, held and output by the SH2 output, and the signal level is sampled, held and output by the SH3 output. SH1 and SH2 are the sample-and-hold circuits for the precharge level; SH3 is the sample-and-hold circuit for the signal level. CDSCLP 1, 2: CDSCLP1 and 2 stabilize the input signal DC level, clamp (CLPDM) the input signal during the idle transfer interval for the purpose of eliminating the AGC input offset, and adjust the DC level ([*1], [*2]) of SH2 and SH3 in line with V REF . CDSCLP1 is the clamp circuit for the precharge level, and CDSCLP2 is the clamp circuit for the signal level. AGC: AGC is the gain control amplifier for the camera signal. The gain can be varied from –1 to +31dB by adjusting the AGCCONT voltage control V AGCCONT from 1.5 to 3.0V. CAM SH: CAM SH is the sample-and-hold circuit for synchronizing the data read-in timing for the external A/D. Sampling is possible according to the approximately 10ns sampling pulse width input to XRS. AGCCLP: The basic black level is set ([*3]) by clamping the AGC output waveform with the CLPOB clock during the OPB interval. When PBLK is High and CLPOB is Low, the clamping circuit operates, adjusting the AGCCLP current so that the DRVOUT potential equals the OFFSET potential (which is determined by the voltage applied to the OFFSET pin), thus setting the AGCCLP potential. The AGCCLP capacitance is connected to the AGCCLP pin. DC SHIFT: This circuit functions when AGCCLP operates, following the AGCCLP potential and forcing a DC shift of the AGC output waveform OPB interval to the basic black level. When AGCCLP is not operating, the basic black level is maintained at its previous setting. BLK SW: The black level is calibrated by blanking the black level signal of the AGC output waveform so that it does not fall below the basic black level and replacing the DC potential with V RB . ([*4]) The signal is blanked when PBLK is Low. OFFSET: OFFSET controls the DRV output waveform black level offset. The offset of the DRVOUT camera signals can be adjusted when a voltage is applied to OFFSET. ([*5]) The voltage controlled by OFFSET is output as the DRV output DC offset via AGCCLP, DCSHIFT, CAMSH and BLKSW. When the OFFSET voltage is 1.5 to 3.0V, DRVOUT DC can vary in a linear fashion from V RB + 100mV to VRB . In addition, when the OFFSET voltage is 0V, DRVOUT DC is preset to VRB + 35mV.

– 13 – CXA2096N DRV: DRV drives the external A/D. The current that flows to the last-stage amplifier in DRV is controlled by applying voltage to the ICONT pin, making it possible to adjust the rise time of the output waveform, which affects the external A/D load capacitance. The variable range is 1.5 to 3V, with 1.5V yielding the maximum and 3V yielding the minimum. The optimum rise time for the external A/D input capacitance can be selected. V RT DRV, VRB DRV: These are the external A/D reference voltage drivers. These circuits are connected to A/D VRT and VRB , supplying 2.35V and 1.35V, respectively, when VCC is 3V. The IC's internal primary voltage is also generated on the basis of the VRT and VRB voltage. (VRB , VB and VCENT ) POWER SAVE CONTROL: The PS pin is the power save pin; the operating state is enabled when this pin is High, while the power saving function operates when it is Low.

– 14 – CXA2096N Characteristics Graphs A G C C O N T control supply voltage characteristics VA G C C O N T vs. G ain VAG C C O N T [V] Gain [dB] O FFSET control supply voltage characteristics VO FFSET vs. O FFSET VO FFSET [V] 0 1.0 2.0 3.0 3.5 100 OFFSET [m (VR B =) 0 A G C C O N T control tem perature characteristics A G C C O N T vs. G ain AG C C O N T [V] 1.5 2.0 2.5 3.0 Gain [dB] VC C = 3.0V Tc = –20°C Tc = +27°C Tc = +75°C O FFSET control tem perature characteristics VO FFSET vs. O FFSET VO FFSET [V] 0 1.0 2.0 3.0 100 OFFSET [m VC C = 3.0V 150 Tc = –20°C Tc = +27°C Tc = +75°C (VR B =) 0–4 Tc = 27°C VC C = 3V VC C = 3.15V VC C = 3.6V 120 140 Tc = 27°C VC C = 3.6V VC C = 3V

– 15 – CXA2096N M axim um signal am plitude tem perature characteristics (M in. gain) Tc vs. Vout Tc [°C ] –20 0.6 Vout [Vp-p] 0.7 0.8 0 50 100 0.53 VC C = 3.0V, AG C C O N T = 1.5V Input am plitude D IN = Input am plitude D IN = Input am plitude D IN = Input am plitude D IN = Input am plitude D IN = 870m Vp-p 800m Vp-p 750m Vp-p 700m Vp-p 600m Vp-p 0.9 D IN = 870m Vp-p D IN = 800m Vp-p D IN = 750m Vp-p D IN = 700m Vp-p D IN = 600m Vp-p M axim um signal am plitude tem perature characteristics (M ax. gain) Tc vs. Vout Tc [°C ] –20 0.8 Vout [Vp-p] 0.9 1.0 0 50 100 0.75 VC C = 3.0V, AG C C O N T = 3.0V Input am plitude D IN = Input am plitude D IN = Input am plitude D IN = 28m Vp-p 24m Vp-p 21m Vp-p 30.99dB 30.99dB 30.76dB 31.41dB 31.41dB 31.03dB 31.45dB 31.45dB 31.12dB D IN = 28m Vp-p 30.99 dB+0 –0.23 D IN = 24m Vp-p 31.41 dB+0 –0.38 D IN = 21m Vp-p 31.45 dB+0 –0.33 G ain tem perature characteristics from –20 to +100°C VR T, VR B , VR T – VR B tem perature characteristics Tc vs. VR T, VR B , VR T – VR B VC C = 3.0V Tc [°C ] –20 V RT, V RB, V RT – V RB [V] 0.8 800 20 40 60 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 VR T VR B VR T – VR B

– 16 – CXA2096N Package Outline Unit: mm SO N Y C O D E EIAJ C O D E JED EC C O D E SSO P-24P-L01 SSO P024-P-0056 PAC KAG E M ATER IAL LEAD TR EATM EN T LEAD M ATER IAL PAC KAG E M ASS EPO XY R ESIN SO LD ER /PALLAD IU M 42/C O PPER ALLO Y PAC KAG E STR U C TU R E PLATIN G 0.1g 24PIN SSO P(PLASTIC ) 0.1 ± 0.1 0° to 10° 0.5 ± 0.2 D ETAIL A ∗5.6 ± 0.1 ∗7.8 ± 0.1 0.65 121 7.6 ± 0.2 0.1 1.25 – 0.1 + 0.2 A 0.13 M N O TE: D im ension “∗” does not include m old protrusion. b=0.22 – 0.05 + 0.1 0.15 – 0.02 + 0.05 (0.22) (0.15) 0.15 – 0.01 D ETAIL B : SO LD ER D ETAIL B : PALLAD IU M + 0.03 b=0.22 ± 0.03 B b N O TE : PALLAD IU M PLATIN G This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Fram e).