CXA2067S

CXA2067S SONY | Alldatasheet

Document overview

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• PDF pages: 18

Technical content

Features

• Wide-band amplifier: 170 MHz@–3 dB (Typ)
• Input dynamic range: 1.0 Vp-p (typ)
• High gain preamplifier (17 dB)
• R, G and B in a single package (SDIP 30 pins)
• I2C bus control Contrast control Sub contrast control Brightness control OSD contrast control Cut-off control: 4 channels of DAC output 2 blanking level modes (0.5 V fixed, pedestal –0.3 V)
• Sync separator for sync-on-green
• Blanking mixing function
• OSC mixing function
• Video interval detection function
• VBLK sync DAC refresh system
• 12 V power supply interlocked power saving function

Applications

High-resolution computer displays Structure Bipolar silicon monolithic IC Preamplifier for High-Resolution Computer Display 30 pin SDIP (Plastic) CXA2067S

— 2— CXA2067S LPF SDA SC L C O F R C O F G C O F B C O F R G B R IN VC C G IN SYN C IN BIN C LP O SD -R O SD -G O SD -B C SYN C /VD ET VC C R S/H -R R O U T G N D -R S/H -G G O U T G N D -G VC C G S/H -B BO U T G N D -B BLKIN G YS VC C B to O SD SW to O SD SW to O SD SW to O SD SW R ch Bch O SD YS G EN ER ATO R G AIN C O N TR O L AM P G AIN C O N TR O L DATA SYN C SEP/VD ET VD ET C O M PAR ATO R SYN C SEPAR ATO R SVSW SU B C O N TR AST C O N TR AST O SD SW BLAN KIN G M O D E BLAN KIN G PU LSE BR IG H TN ESS O SD G AIN (R ) O SD PU LSE (13PIN ) YS PU LSE (17PIN ) To each M O D E SW I C BU S D EC O R D ER BLAN KIN G BU FFER AM P Sam e as R channel Sam e as R channel G ch 301 12V 12V 12V D /A C O N VERTO R C O N TR AST SU B C O N TR AST (R ) SU B C O N TR AST (G ) SU B C O N TR AST (B) O SD G AIN (R ) O SD G AIN (G ) O SD G AIN (B) BR IG H TN ESS (R G B) C U TO FF (R ) C U TO FF (G ) C U TO FF (B) C U TO FF (R G B) Block Diagram

— 3— CXA2067S Pin Description SDA SCL COF R COF G COF B COF RGB RIN GIN BIN VCC 1.7 V (Clamp) 5 V VC C 10k VC C 100 VC C VC C VC C VC C VC C VC C VC C14k VC C VC C 9 300 I2C bus standard SDA (serial data) input/output. VILMAX=1.5 V VIHMIN=3.5 V VOLMAX=0.4 V I 2C bus standard SCL (serial clock) input/output. VILMAX=1.5 V VIHMIN=3.5 V DAC output for cut-off adjustment. Output DC is 1 to 4 V. R, G and B signal inputs. Input via a capacitor. 5 V power supply. Pin Symbol Pin Equivalent circuit DescriptionNo. voltage

— 4— CXA2067S SYNC IN CLP OSD-R OSD-G OSD-B V CC B YS 2.8 V 12 V 100 VC C VC C VC C 150 VC C VC C 10k 10k10k VC C VC C 10k VC C VC C 10k Sync-on-green signal input. Input via a capacitor. Clamp pulse (positive polarity) input. VILMAX=0.8 V VIHMIN=2.8 V OSD control inputs. VILMAX=0.8 V VIHMIN=2.8 V 12 V power supply. (B channel) YS (OSD BLK) control input. VILMAX=0.8 V VIHMIN=2.8 V Pin Symbol Pin Equivalent circuit DescriptionNo. voltage

— 5— CXA2067S BLKING GND-B GND-G GND-R BOUT GOUT ROUT S/H-B S/H-G S/H-R V CC G VCC R 0 V 12 V 12 V VC C VC C VC C 10k 30k VC C R /G /B 310 VC C R /G /B VC C R /G /B VC C VC C VC C 300 Blanking pulse input. Set the V blanking pulse width to 300 µs or more. VILMAX=0.8 V VIHMIN=2.8 V Ground. R, G and B outputs. Brightness sample-and-hold. Connect to GND via a capacitor. 12 V power supply. (G channel) 12 V power supply. (R channel) Pin Symbol Pin Equivalent circuit DescriptionNo. voltage

— 6— CXA2067S

30 CSYNC

/VDET — VC C VC C VC C 500 100 VC C 20k Sync-on-green signal sync separator output/video detector output. Either of them is selected by SVSW of I 2C bus. Typ. :High=4.3 V Low=0.2 V (positive polarity) Pin Symbol Pin Equivalent circuit DescriptionNo. voltage

— 7— CXA2067S Definitions of I2C Bus Register Slave Address SLAVE RECEIVER : 40 (HEX) Register Table SUB ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 CONTRAST

0 BLK MODE BRIGHTNESS

Note)*: don’t care Sub Address CONTRAST (8): Performs the gain control for R, G and B channels in common. 0000 Control is performed by the multiplication with SUB CONTRAST. The white balance is adjusted by SUB CONTRAST and the luminance is adjusted by CONTRAST. 0 : Gain minimum (–30 dB or less) 255 : Gain maximum (+17 dB) Sub Address BLK MODE (1): Switches the blanking level. 0001 0 : Pedestal–0.3 V 1 : 0.3 V fixed Sub Address BRIGHTNESS (6): Performs the black level control for R, G and B channels in common. 0001 0 : Black level minimum (0.9 V) 63 : Black level maximum (2.8 V) Sub Address CUT OFF R (8): Performs the Pin 3 (COF R) output voltage control. 0010 0 : Output voltage minimum (1 V) 255 : Output voltage maximum (4 V) Sub Address CUT OFF G (8): Performs the Pin 4 (COF G) output voltage control. 0011 0 : Output voltage minimum (1 V) 255 : Output voltage maximum (4 V) Sub Address CUT OFF B (8): Performs the Pin 5 (COF B) output voltage control. 0100 0 : Output voltage minimum (1 V) 255 : Output voltage maximum (4 V)

— 8— CXA2067S Sub Address VDET LEVEL (2): Controls the signal detection (VDET) slice level. 0101 0 : Slice level minimum (RIN or GIN or BIN=30 mV) 1 : Slice level maximum (RIN or GIN or BIN=220 mV) Sub Address OSD GAIN (6): Performs the OSD gain control for R, G and B channels in common.

0110 Control is performed by the multiplication with SUB CONTRAST (upper 6

bits) so that the video white balance and tracking are obtained. 0 : Gain minimum (0 Vp-p) 63 : Gain maximum (5 Vp-p) Sub Address CUT OFF RGB (8): Performs the Pin 6 (COF RGB) output voltage. 0110 0 : Output voltage minimum (1 V) 255 : Output voltage maximum (4 V) Sub Address SUB CONTRAST R (8): Performs the R channel gain control. 0111 Control is performed by the multiplication with CONTRAST. Use for the white balance adjustment. 0 : Gain minimum (–30 dB or less) 255 : Gain maximum (+17 dB) Sub Address SUB CONTRAST G (8): Performs the G channel gain control. 1000 Control is performed by the multiplication with CONTRAST. Use for the white balance adjustment. 0 : Gain minimum (–30 dB or less) 255 : Gain maximum (+17 dB) Sub Address SUB CONTRAST B (8): Performs the B channel gain control. 1001 Control is performed by the multiplication with CONTRAST. Use for the white balance adjustment. 0 : Gain minimum (–30 dB or less) 255 : Gain maximum (+17 dB) Sub Address VDET OFF (1): Performs the Pin 30 output control. 1010 0 : Output ON 1 : Output OFF Sub Address SV SW (1): Switches the Pin 30 output signal (sync separator/video detector). 1010 0 : Sync separator output 1 : Video detector output Sub Address VS OFF (1): Performs the control of VBLK sync DAC refresh function. 1010 0 : Function operation ON 1 : Function operation OFF

— 9— CXA2067S I2C Bus Logic System No. Item High level input voltage Low level input voltage Low level output voltage with 3 mA SDA current inflow Maximum clock frequency Minimum waiting time for data change Minimum waiting time for data transmission start Low level clock pulse width High level clock pulse width Minimum waiting time for start preparation Minimum data hold time Minimum data preparation time Rise time Fall time Minimum waiting time for stop preparation Symbol V IH VIL VOL fSCL tBUF tHD : STA tLOW tHIGH tSU : STA tHD : DAT tSU : DAT tR tF tSU : STO Min. 3.0 4.0 4.0 4.7 4.0 4.7 250 4.7 Typ. Max. 5.0 1.5 0.4 400 300 Unit V V V kHz µs µs µs µs µs ns ns µs ns µs

— 10— CXA2067S

Electrical Characteristics

No. Measurement item Current consumption (5 V) Current consumption (12 V) Current consumption (12 V OFF) Frequency response (50 MHz) Frequency response (100 MHz) Contrast control 1 Contrast control 2 Sub contrast control Symbol ICC 1 ICC 2 ICC 3 F50 F100 GCONT1 GCONT2 GSUB Measurement contents VCC (5 V) pin inflow current RGB signal input: None V CC R/G/B (12 V) pin inflow current RGB signal input: None V CC pin inflow current for 12 V OFF RGB signal input: None Input the continuous 1 MHz, 50 MHz and 100 MHz sine waves (0.7 Vp-p). Measure the output amplitude gain difference at this time. Vout (50 MHz) Gain difference [dB]=20 logVout (1 MHz) Vout (100 MHz)Gain difference [dB]=20 logVout (1 MHz) Measure the output signal amplitude Vout level when a 0.7 Vp-p video signal is input. GCONT1 : Contrast=SubContrast=FF GCONT2 : Contrast=00/SubContrast=FF Measure the output signal amplitude Vout level when a 0.7 Vp-p video signal is input. Contrast=FF/SubContrast=00 Min. Typ. Max. Unit 85 115 140 mA 29.5 45 55.5 mA 20 30 40 mA –1.5 0 1.9 dB –3.0 0 3.0 dB 5.6 6.2 — Vp-p — 0 100 mVp-p — 0 100 mVp-p 0.7Vp-p G N D C LP potential (Approx. 1.7 V) R G B input signal (R G B input pins) 0.7Vp-p Input signal 0.7Vp-p Input signal

— 11— CXA2067S Min. Typ. Max. Unit 4.5 5 — Vp-p — 0 150 mVp-p 0.4 0.7 1 V 2.2 2.6 3 — 0.3 0.6 V — 0.3 0.6 — 30 40 ns — 60 80 — 20 40 ns — 30 60 No. Measurement item OSD gain control Brightness control BLK control (BLK MODE=0) BLK control (BLK MODE=1) Sync separator output rise delay Sync separator output fall delay VDET output rise delay VDET output fall delay Symbol GOSD1 GOSD2 VBRT1 VBRT2 VBLK1 VBLK2 SDLYR SDLYF DDLYR DDLYF Measurement contents Measure the OSD level of the output signal when the OSD pulse is input. GOSD1 : OSD=3F/SubContrast=FF GOSD2 : OSD=00/SubContrast=FF Measure the black level of the RGB output signal. VBRT1 : Brightness=00 VBRT2 : Brightness=3F Measure the BLK level of the output signal when the BLK pulse is input. R G B output signal O SD interval O SD level G N D Black level R G B output signal G N D BLK level (VBLK1) BLK level (VBLK2) Vth=50% Vth=50% R ise D elay Fall D elay Vth=50% Vth=50% R ise D elay Fall D elay 0.7Vp-p

— 12— CXA2067S Min. Typ. Max. Unit — 1 1.3 V 3.9 4 — 3.85 4 — Vp-p No. Measurement item DAC output voltage (COFF=00) DAC output voltage (COFF=FF) VDET output amplitude Symbol VCUT1 VCUT2 VDET Measurement contents Measure the DAC output voltage (Pin 6) for COFF=00/FF. Input the crosshatch signal of DotClock=100 MHz/0.7 Vp-p and measure the VDET output amplitude. SW SW=1/VDET LEVEL=0 0.7Vp-p Input signal 10ns 10ns

— 13— CXA2067S Electrical Characteristics Measurement Circuit SYN C SEP/VD ET O utput 47µF 0.1µF 47µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF SD A SC L C O F R C O F G C O F B C O F R G B R IN VC C G IN SYN C IN BIN C LP O SD -R O SD -G O SD -B C SYN C /VD ET VC C R S/H -R R O U T G N D -R S/H -G G O U T G N D -G VC C G S/H -B BO U T G N D -B BLKIN G YS VC C B 12V 47µF 0.1µF 12V 47µF 0.1µF 12V 220 220 I C BU S D AC O utput 0.1µF 0.1µF R ch O utput G ch O utput Bch O utput

— 14— CXA2067S Electrical Characteristics Measurement Circuit (Frequency response) SYN C SEP/VD ET O utput 47µF 0.1µF 47µF 0.1µF 0.1µF 0.1µF 0.1µF SD A SC L C O F R C O F G C O F B C O F R G B R IN VC C G IN SYN C IN BIN C LP O SD -R O SD -G O SD -B C SYN C /VD ET VC C R S/H -R R O U T G N D -R S/H -G G O U T G N D -G VC C G S/H -B BO U T G N D -B BLKIN G YS VC C B 12V 47µF 0.1µF 12V 47µF 0.1µF 12V 220 220 I C BU S D AC O utput 0.1µF 0.1µF R ch O utput G ch O utput Bch O utput 0.1µF 0.1µF

— 15— CXA2067SThe VBLK signal is extracted form the composite BLK signal input to Pin 18. The DAC data rewrite for each control is simultaneously performed, synchronizing to the VBLK signal. The received I2C bus data is held by the latch till the next VBLK signal comes. Therefore, the timing of I2C bus data transmission from the microcomputer is free. The V blanking pulse width input to Pin 18 should be 300µs or more. VBLK Bus data transm ission DAC refresh Enable signal DAC refresh signal Transm ission interval D ata 1 D ata 2 D ata 3 enable disable The latest data w hich w as sent before VBLK is w ritten to DAC. In this case, D ata 1 is w ritten. DAC rew rite is not perform ed w hen the bus data transm ission is in progress for the VBLK interval. The sent data is hold. R ew rite to D ata 3. W hen D ata 3 is not transm itted, rew rite to D ata 2. VBLK Sync DAC Refresh System

— 16— CXA2067S Application Circuit SYN C SEP/VD ET O utput 47µF 0.1µF 47µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF SD A SC L C O F R C O F G C O F B C O F R G B R IN VC C G IN SYN C IN BIN C LP O SD -R O SD -G O SD -B C SYN C /VD ET VC C R S/H -R R O U T G N D -R S/H -G G O U T G N D -G VC C G S/H -B BO U T G N D -B BLKIN G YS VC C B 12V 47µF 0.1µF 12V 47µF 0.1µF 12V 220 220 I C BU S D AC O utput 0.1µF 0.1µF R ch O utput G ch O utput Bch O utput YS input Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

— 17— CXA2067S Notes on Operation 1. The ROUT, GOUT and BOUT outputs should be received in the high impedance state. 2. The wiring from ROUT, GOUT and BOUT to the power amplifier should be as short as possible. 3. For the decoupling capacitors for VCC and VCC R/G/B, the ceramic capacitor and the electrolysis capacitor should be connected in parallel as closely to the IC as possible. 4. The clamp capacitors for RIN, GIN, BIN, S/H R, S/H G and S/H B should be connected as close to the IC as possible. 5. The signals to RIN, GIN and BIN should be input via a clamp capacitor with the low impedance. 6. Set the output OFF when the VDET output is not used (The cross talk may deteriorate).

30PIN SD IP (PLASTIC ) 26.9 – 0.1 + 0.4 1630 1.778 10.16 8.5 – 0.1 + 0.3 0.25 – 0.05 + 0.1 0° to 15° 0.5 ± 0.1 0.9 ± 0.15 3.0 M IN 0.5 M IN 3.7 – 0.1 + 0.4 SD IP-30P-01 SD IP030-P-0400 PAC KAG E STR U C TU R E M O LD IN G C O M PO U N D LEAD TR EATM EN T LEAD M ATER IAL PAC KAG E M ASS EPO XY R ESIN PLATIN G C O PPER ALLO Y 1.8g SO LD ER /PALLAD IU M 1.All m at surface type. Tw o kinds of package surface: 2.All m irror surface type. Package Outline Unit : mm CXA2067S — 18— Sony Corporation