CXA2016S SONY | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 12

Technical content

Features

  • Power save function available (5 V power supply)
  • Clamp pulse output position selectable among sync interval, back porch interval, and AUTO.
  • Polarity information of sync signals is output.
  • Polarity and amplitude of input signals: Polarity Amplitude (Vp-p) V. separate sync: Positive/Negative 1 to 5 H. separate sync: Positive/Negative 1 to 5 Composite sync: Positive/Negative 1 to 5 Sync on video: Sync signals part of Negative 0.2 to 0.4 Video part 0 to 1.4

Applications

Pin Configuration (Top View) Block Diagram 11 12 22VS IN PVC EVC CS IN PHC EHC Video IN HD SEL ISC ISJ GND V CC VD VSS IN VSS OUT HD PV PH CLP SEL CLP OUT VSS REF CLP OUT Polarity Check V. Ramp Generator Exist Check Polarity Check Exist Check Sync Sep Level Control Bias Sync Check Logic Clamp Pulse Generator 10 19 20 12 2211 2 3 PVC EVC VS IN PV PH CS IN PHC EHC Video IN ISJ V SS OUT V SS IN VSS REF GND V CC VD HD SEL HD ISC CLP OUT CLP SEL CLP OUT

— 2— CXA2016S Pin Description (Ta=25 °C, VCC =5 V) Pin Symbol Pin Equivalent circuit DescriptionNo voltage VC C G N D 100 VC C G N D 96k 200 200 200 VC C G N D VC C G N D 100 VC C G N D 96k 1001k VC C G N D VS IN PVC EVC CS IN PHC EHC 2.6 V 2.6 V V. separate sync (positive/negative polarity) as capacitor input. Amplitude is 1 to 5 Vp-p. This pin connects a 0.22 µF integrating capacitor for the vertical signal polarity check circuit to GND. When connecting the capacity at positive polarity, it is 2.9 V and at negative polarity, 120 mV. V. ramp waveforms generation part of vertical signal exist check circuit. Generates ramp waveforms synchronously with the input signal cycle and connects 0.22 µF to GND. Inputs composite sync (positive/negative polarity) and H. separate sync (positive/negative polarity) as capacitor input. Amplitude is 1 to 5 Vp-p. This pin connects a 0.1 µF integrating capacitor for the horizontal signal polarity check circuit to GND. When connecting the capacity at positive polarity, it is 2.6 V and at negative polarity, 350 mV. A 33 kΩ resistance and a nearly peak hold circuit for 0.22 µF capacitor are connected to this pin for input signal exist check at CS IN input pin. When a signal is input at CS IN pin, a nearly peak hold is executed at 2.1 V to 2.7 V, a comparison is made with the 1.4 V reference voltage, and input signal exist is identified.

— 3— CXA2016S VC C G N D VC C G N D 2k 1k VC C G N D 50k 100 4k 1k VC C G N D 50k 100 12k 20k VC C G N D Video IN HD SEL ISC ISJ GND VSS REF 1.2 V 1.2 V 0 V 3.125 V Inputs sync on video (sync at negative polarity). Connects in series a 1 µF capacitor and a 270 Ω resistance to input signals. Selects output processing of HD (H. Drive Pulse) at a VD interval. Input at TTL level. When Low level is selected, HD is not output at a VD interval. When High level is selected, HD is output at the VD interval. Resistance connecting pin for reference current source of clamp pulse output circuit, and connects 12 kΩ resistance to GND. When a 12 kΩ resistance is connected, a 100 µA current flows through this pin (pulse width is approximately 300 ns). Clamp pulse output pulse width is varied by changing the value of the resistance. *Use a metal film resistor with an accuracy of ±1 % Resistance connecting pin for reference current source and connecting 12 kΩ resistance to GND. When the resistance is connected, a 100 µA current flows through this pin. *Use a metal film resistor with an accuracy of ±1 % GND pin. Reference pin for V. sync separator of composite sync and video sync. Pin Symbol Pin Equivalent circuit DescriptionNo voltage

— 4— CXA2016S 500 40k VC C G N D 43k 30k 20k VC C G N D 20k 20k VC C G N D 333 6k VC C G N D 200 5k 2.5k 17.5k VC C G N D VC C G N D CLP OUT CLP OUT CLP SEL PH PV HD V SS OUT VSS IN Clamp pulse output; Open collector- type pin at positive polarity. Clamp pulse output; Open collector- type pin at negative polarity. Selects output position of a clamp pulse. Input at TTL level. When Low level is selected, a clamp pulse is output at a back porch interval. When High level is selected, clamp pulse is output at a sync interval. See the Description of Operation for Input/Output Matrix. Output polarity information of horizontal and vertical sync signals. See the Description of Operation for Input/Output Matrix. HD (H. Drive Pulse) output; Push-pull type pin at positive polarity. Composite sync or sync signal separated from video sync is output. Output is at positive polarity. Input for V. sync separator comparator. Integrates the output at Pin 19 and inputs it. Pin Symbol Pin Equivalent circuit DescriptionNo voltage

— 5— CXA2016S 10k 10k 10k VC C G N D VD VCC 5 V VD (V. Drive Pulse) output pin. Output is at positive polarity. Power supply pin. Pin Symbol Pin Equivalent circuit DescriptionNo voltage

— 6— CXA2016S No. Item Symbol Measurement contents Measurement Min. Typ. Max. Unitpoint VD output voltage HD output voltage Clamp pulse output voltage Clamp pulse output pulse width HD delay Clamp pulse delay Polarity identification output voltage Current consumption Measure VD output peak value during V. separate sync input. Input signal A. (tw=60 µs) Measure HD output peak value during sync on video input. Input signal C. (tw=1 µs) Measure clamp pulse output peak value during composite sync input. Input signal B. (tw=1 µs) Measure clamp pulse output pulse width during composite sync input. Input signal B. (tw=1 µs) Measure delay difference between CS and HD during composite sync input. Or the time from CS (positive polarity) rise time (50 %) to HD output rise time (50 %). Input signal D. Measure delay difference between HD and clamp pulse during composite sync input. Or the time from HD output fall time (50 %) to clamp pulse output rise time* 1 (50 %). Input signal B. Sync signal polarity information is output. Measure high level voltage. (No load) Sync signal polarity information is output. Measure low level voltage. (No load) V CC =5 V. Measure current consumption during no signal input. E VD EHD ECP tC thd tcd1 PN PP ICC VD (Pin 21) HD (Pin 18) CLAMP (Pin 13) CLAMP (Pin 14) CLAMP (Pin 13) CLAMP (Pin 14) HD (Pin 18) CLAMP (Pin 13) CLAMP (Pin 14) PH, PV (Pins 16 and 17) PH, PV (Pins 16 and 17) VCC (Pin 22) High level 4.3 4.9 — Low level — 0.1 0.4 High level 3.3 4.2 — Low level — 0.3 0.5 High level 4.3 4.9 — Low level — 0.3 0.8 High level 4.3 4.9 — Low level — 0.4 0.9 260 305 380 260 310 380 — 75 100 — 5.0 30 — 5.0 30 4.3 — — — — 0.4 — 26.5 45 V V V V ns ns ns ns V V mA Electrical Characteristics(Ta=25 °C, VCC =5 V. See the Electrical Characteristics Measurement Circuit.) *1 CLAMP is for the fall time.

— 7— CXA2016S Video IN (Pin 7) fV=40 Hz tWV =60 µs fH =50 kHz tWH =1 µs Signal A B C D Composite SYNC IN (Pin 4) fv=40 Hz tWV =60 µs Negative logic

1 Vp-p

fH =50 kHz tWH =1 µs Negative logic fH =50 kHz tWH =1 µs Positive logic 1 Vp-p Item 3, 4, 6 V. SYNC IN (Pin 1) fv=40 Hz tWV =60 µs Negative logic V 1W V H 1W H V 60µs 10H 3H 0.7V 0.2V H 1µs 3µs 0.7V 0.2V 15µs Types of Signal Source 1W V

— 8— CXA2016S Electrical Characteristics Measurement Circuit C LAM P PH PV VD 2.2k H D C LAM P 220 VS IN PVC EVC C S IN PH C EH C Video IN H D SEL ISC ISJ G N D VC C VD VSS IN VSS O U T H D PV PH C LP SEL C LP O U T C LP O U T VSS R ef Video Sync H S or C S VS 2.2µ 0.22µ 0.22µ 0.1µ 33k 0.22µ 10k 12k 12k 1µ 10µ 5V 3300p 0.01µ 0.1µ 0.01µ

  • VS IN (Pin 1) f V : 40 to 200 Hz VS : 1 to 5Vp-p (positive/negative polarity)
  • HS IN (Pin 4) fH : 15k to 130 kHz VS : 1 to 5 Vp-p (positive/negative polarity)
  • CS IN (Pin 4) fH : 15 k to 130 kHz fV : 40 to 200 Hz VS : 1 to 5 Vp-p (positive/negative polarity)
  • Video IN (Pin 7) fH : 15 k to 130 kHz fV : 40 to 200 Hz VV : 0 to 1.4 Vp-p VS : 0.2 to 0.4 Vp-p Clamp Pulse Output
  • Clamp pulse (Pins 13 and 14) is output under the following conditions. Pin 13 is for open collector output and is at positive polarity. Pin 14 is for open collector output and is at negative polarity. td: Clamp pulse delays for 10 to 20 ns from HD. tw: Clamp pulse width varies depending on the value of the resistance connected to Pin 9. <Conditions> (1)When CS IN or Video IN is selected, a clamp pulse at the VD interval is not output. (2)During H./V. Separate Sync, a clamp pulse at the VD interval is also output. (3)When Pin 15 (CLP SEL) is connected to GND, a clamp pulse is output at the back porch interval. When Pin 15 (CLP SEL) is connected to V CC , a clamp pulse is output at the SYNC interval. If a capacitor is connected between this pin and GND, the output position is automatically selected. Clamp Pulse Input/Output Matrix — 9— CXA2016S CLP SEL VS IN CS IN Video IN Clamp pulse output position GND * * * Back porch interval VCC * * * SYNC interval * — O Back porch interval AUTO * O — SYNC interval * — — (Back porch interval) [O] indicates that input SYNC exists. [—] indicates no signal (no SYNC). [ * ]has no relation with input signal.

— 10— CXA2016S HD Select Function When HD SEL is Low, HD at the VD interval is not output. When HD SEL is High, HD at the VD interval is output. During separate sync output, HD is output regardless of HD SEL. Mode Matrix of SYNC Polarity Identification Signal VS IN CS IN PV out PH out (Pin 1) (Pin 4) (Pin 17) (Pin 16) No signal Low Low VS (positive polarity)HS (positive polarity) Low Low HS (negative polarity) Low High No signal High Low VS (negative polarity)HS (positive polarity) High Low HS (negative polarity) High High No signal Low Low No signal COMP (positive polarity) Low Low COMP (negative polarity) Low High VS IN CS IN Video IN VD OUT HD OUT O O * VS CS — O * CS CS — — O Video Video — — — (Video) (Video) O — O VS Video O — — VS (Video) Note) The corresponding sync signals are input to VSIN and Video IN. [O] indicates that input SYNC exists. [—] indicates no signal. [ * ]has no relation with input signal. Low level: 0 to 0.4 V, High level: VCC Input/Output Matrix

— 11— CXA2016S Application Circuit C LP O U T PH PV VD O U T 2.2k H D O U T C LP O U T VS IN PVC EVC C S IN PH C EH C Video IN H D SEL ISC ISJ G N D VC C VD VSS IN VSS O U T H D PV PH C LP SEL C LP O U T C LP O U T VSS R ef VS 2.2µ 0.22µ 0.1µ 33k 0.22µ 12k∗ 12k∗ 3300p 0.1µ 0.22µ 27075 0.01µ VC C Video (G ) C S or H S U se m etal film resistor w ith an accuracy of ±1% for the resistor m arked ∗. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

22PIN SDIP (PLASTIC) SDIP-22P-01 SDIP022-P-0300 0.95g 1.778 19.2 – 0.1 + 0.4 7.62 6.4 – 0.1 + 0.3 0.25 – 0.05 + 0.1 0° to 15° 0.5 ± 0.1 0.9 – 0.1 + 0.15 3.25 – 0.2 + 0.15 0.51 M IN 3.9 – 0.1 + 0.4 1.All mat surface type. Two kinds of package surface: 2.All mirror surface type. Package Outline Unit : mm CXA2016S —12—