CXA1201Q | DigiCamel IC Datasheet

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CXA1201M SONY | Alldatasheet

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SONY. CXA1201M/Q] VCR Image I/O Signal Processing

Description

CXA1201 is an IC developed for the VIDEO, AGC, and IN/OUT processes of the VCR. A CXA1201M CXA12010 combination with CXA1200 permits consistent Y/C 30pin SOP (Plastic) 32pin QFP (Plastic) main signal processing with a 8 mm video. Features LP ¢ Single power supply operatition 5V. LEA LO» * Reduced external parts by containing the AGC La BN time constant. ea “ * Accommodation to BUS LINE. aa * Compatible to any VCR format. Functions « INPUT-Select-SW « VIDEO-AGC AMP « SYNC SEPARATOR * DDS (Y singal superimpose circuit) « JOG and PCM after-recording applicable. «* VIDEO output buffer * 75Q VIDEO-OUT driver « AGC OFF 2dB Amplifier ¢ BUS LINE input and serial data output. ¢ 4.2V built-in regulator Structure Bipolar silicon monolithic IC Absolute Maximum Ratings (Ta=25°C) « Supply voltage Vec 7 Vv ¢ Operating temperature Topr -10 to +75 °C * Storage temperature Tstg -55 to +150 °C ¢ Allowable power Po 930 mV dissipation (When mounted on the board) Recommended Operating Conditions (Ta=25°C) « Supply voltage Vec 5 + 0.25 V -1- Sony reserves the right to change products and specifications without prior notice. This information does not convey any license 90735-VA by any implication or otherwise under any patents or other right Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

Block Diagram and Pin Configuration CXA1201M In2 ont vREG INI VEC! SI CS -cK~«SO_~MASK ARKO Vow vos DOC SYNC G2) 49 4) 2949) 8) (IDI r YT TY 7 7 ' socom | tt an i cor i ot Cm} | ff } eee SNE I eseee I Mecano 17 Th ! tot mt } Ab 11| 1 { > te re | TT tee0 O-@-O-O—S O-®9)-OW HY) 9-O*9 IREF INS AGC REC L PB IN PBL RF JOG V¥ INV GNOZ V OUT VCC2 CLP REC Vv SSIN Te w OUT IN IN CXA1201Q i - 8 4 8 5 Fs i PPO 69-8 tt ase 1m QS) ——o fe33> to fn ---(78) vo8 3 . “T = | [” ae we) (fe PE eS" ar el t Ls “eo V7 ! BS (8) vee2 OO —-D-O)--©O--—-®

2 E + 5 2 z 3 5

-2-

Pin Description (__) indicates the pin number of CXA1201Q. Veco _=5V, Ta=25°C Symbol Voltage Equivalent Circuit Description 1/2 potential of VREG. Vee The internal reference current is made by attach- 1 IREF 24V wae © ing a resistor externally. (80) pen iC) @ potoge nD 1008 t Video signal Vee Video signal input pin by input (0.5Vp-p) diode clamp. IN 3 é (31) nls @ F 2.1V clamp External +04] 6 Le Qt Vee AGC time constant pin. 3 3 (32) AGC TC | Open emitter @ avo yi 0 dB level adjusting pin Vase for REC. 4 22K (1) REC L | 2.0V center 40% o Vee 208 4 External Video signal —— Vee Video signal input pin by input (0.5Vp-p) z diode clamp (input for 5 an PB). PB IN (2) @ vw 4 External AI 2.4V clamp ano a —_ 0 dB level adjusting pin Ynce for REC (adjustment for 22K PB). @) PBL 2.0V center -—©® 40% Vee 20% ® External ~3-

Symbol Equivalent Circuit Description Video signal Output pin to RF MOD IC. input (1Vp-p)* Vee 7 RF (4) | MouT wok ® arr [bos] >-O no VOUT Pin that inputs the dummy Pulse Input Vee V signal upon playback at a changed speed. 8 ——- SV o 6) JOG V ay ® OTE e438 t (Vt: 1.7V) ano Jgt Video signal Inversion input pin for V input (1Vp-p) Vee sag calibration of the Peal > VIDEO OUT 759 driver. eno External

10 GND for the VIDEO OUT

Video signal a Output pin of the VIDEO | input (2Vp-p) 7 Vee OUT 759 driver. |v out 4 2 | _ @) o C He te sooo ----U. ® External 12 a Vee for the VIDEO OUT “poy sev __ 780 driver Video signal The RECV output of the input (0.5Vp-p) Vee video signal is C-coupled, treated with synchroniza- tion clamp, then input to 13 CLP IN ® the IC again. “) vet he rer’ ano External rec ani *Note) For the 0 dB video Input and AGC ON. The same applies to the following, 4

ee SsSSSSSsSSseeeesessSsSSSSSSSSSsSSSsSSSSsSSSSSeeses [ No. | Symbol Equivalent Circuit Description Video signal REC VIDEO output pin. input (1Vp-p) Vee VCA or 2 dB Amp output. o mm aud ke { ___.--LE (0) ~ TSS exo vo Video signal Diode clamp input pin of input (0.5Vp-p) Vee the SYNCSEP circuit. a | SNE UL, @ er a07 * ano External “i r Comp Syne Comp Sync output pin. output vee =-- 2.5V

16 SYNC

(14) TH ov @ 5eS Pulse input ~ AGC DET hold draw control pulse input pin. Vee 17 -~- 3.29 Doce " a ” Poa, - xO = ? (Vin 2.1) Inhibited at “H” Input of the DDS back- Pulse input ulse inpu y ground level and SW “ pulse. Vue 18 4 (16) VOB Th — 1 ono dba: E> | com -~5-

[ No. | Symbol Equivalent Circuit Description _ Input of the DDS charac- Pulse input Vee ter level and SW pulse. Voce G7) | VOW | tat C) | oY : PCM after recording area Pulse Input Vee HD pulse input pin.

2 ARHD ~~ 8V

18) " Sh. ® sent No (VtH: 2.7V) one Ise i PCM after recording mask Pulse input Vee pulse input pin. 21 -— SV (19) | MASK JST icy rt tJ 390 tht (Vt: 1.7V) . Mode switching logic Pulse input vee pulse output pin. (0) so ~Y J otw @ exp Mode switching logic Pulse Input Vee pulse input pin (clock). 23 cK —- sv _— 1) Jew [jl #2 a Mode switching logic Pulse input vee pulse input pin (chip select). (22) cs i sv nv 2) o-oo exo -~6-

Voltage _ Equivalent Circuit Description ji Mode switching logic Pulse input Vee pulse input pin (serial in). es) Sl —— sv Slew

26 Vcc other than VIDEO

Vec 1 Apply 5.0V —_ Video signal Vee Video signal input pin by Input (0.5Vp-p) diode clamp. (25) 1 ml L r 6 . External ~~ 2.1V clamp _ exo 4 Vee 28 are Built-in voltage regulator (26) Ves 4.2 T @ output pin. exo GND other than VIDEO 29 OUT. (27) GND 1 Video signal Vee Video signal input pin by input (0.5Vp-p) diode clamp.

30 IN 2

(28) ad 8 External “i 2.1V clamp SND af 7 _ a -7-

Electrical Characteristics

(Vcc = 5V, Ta = 25°C) [Test tem [Symbol Goneitions | pot | Min. | Typ. | Max. | Unt | REMOUT frequency A357m Vp-p Sin wave Is put on characteristic 5M/S00K the input SYNC 0 dB 50% white 7 dB signal V out frequency charac- A 357m Vp-p Sin wave Is put on teristic 5M/500K Vo-f | the Input SYNC 0 dB 50% white dB signal pre AGC Input small | agc.t| input SYNC-6 dB all black signal pw | | us | mVp-p pync AGC Input large | ago.H] input SYNC+6 dB Pw [| jw] | mVp-p Peak AGC operation AGc.p| Input SYNC-6dB 100% white all 14 mVp-p sections DDS 6 dB amplifier Input SYNC 0 dB 100% white all fz [ss] | os | ae gain sections Input-Vout amplifier gain Vo+6 Input SYNC 0 dB 100% white all 112 126 dB sections AGC OFF mode ampli- AGC | Input SYNC 0 dB 100% white all 2 dB fier gain OFF | sections SYNC SEP output LO Input SYNC 0 dB all black |i | | | oa] v SYNC SEP output HI | SS-H | input SYNC 0 dB all black [iw | 2s] | |v SYNC SEP output delay | SS-D | Input SYNC 0 GB all black lie | | | ov | BS ow SEP output pulse Input SYNC 0 B all black 16 le] | us SYNC SEP operation 1 Input SYNC 0 dB all black 14 || +6 dB SYNC SEP operation r Input SYNC 0 dB all black “ =| | | “ level Pies CS input HI | uin-H | input CMOS drive | feet ft | Vv 80 output LO level | sor]Nowad | || te |v SO output HI level No load | 2 fas] | | Vv CK-SO delay CK-SO| No load |_| 150 | | 850 | ns VREG D.C. [ res |Loadzsin | 28 | aoe || ase |v IREF D.C. | virer| toad toon | tf aoe | fate |v REMOUT SYNC DC For SYNC 0 dB | 7 | 1450 | 1600 | 1750 | mv -~8-

SONY CxAr201M/O. eee CXA1201 SYNC & PEAK AGC Operation Chart 1) SYNC AGC SYNC large SYNC small Input (IN1, etc.) + | A a u u 008 eens |e | Res | rs 143mVp-p Output (RECY) PI oge 143mvp-p SYNC is set to a constant size. Always 0 dB within the cover range. 2) PEAK AGC Continuous white level large — Short-period white level large Input al “Og TT meine nes : se cere a Outpu cal i dB The p-p value of SYNC-white level is set to a constant or smaller value. The AGC operation is low if the white level large period is short. 3) SYNC & PEAK AGC Input “ ae Se eS Output “| | The PEAK AGC operation Is higher. When the SYNC shrinking Y signal comes in, SYNC AGC tries to elongate. However, PEAK AGC works stronger and suppresses to a certain level. ~10-

Y Signal Superimpose Circuit (a) Fringed display Character signal 4 lu _ _ - = vow Fringe signal Pe (b) Background display No background Oo oo. Character signal oe vow Background signal a vos Timing of the character signal, fringe signal, and background signal eovwen (CT Fringe signal Sr VOB ma tat ua Yo Character level _.!! i { i tt i i fi i cmetesew (HOU en Fringe or oho level -W-

Operation for PCM after recording Masked semi-transparently upon after recording in SP mode (for every two fields) Completely masked upon after recording in SP or LP mode Noise due to crosstalk factor of the PCM recording PCM audio recording or flying current or flying erase current NN erase part for after recording _—— es HD INSERT circuit input Ni DUB AREA MASK HD INSERT ARHD HD INSERT circuit output Ye \\ ~12-

CXA1201 DDS and JOG PCM Logic Chart Input Output mute | Jocvo | mask | ARHD a 1.9V Fe ee = VOB and VOW 1/O Chart RF MOUT (V) - VOW 2.6 “VO 1. VOB an ! ’ I \\ 20 ! ' PED ----- A aan) t ' i ' 7 SYNC ---1.6 { i I { ' ' 1 i 0 25 5 (v) VOB , VOW ~ 13 -

measurement 7 The sin wave is put on 357 50% white. The frequency mv s76.5mV | is So0KHz and 5MHz. $G14 143mV SYNC AGL iy ated SYNC+6dB : SG-A | 286mv p-p detection at SYNC and VIDEO timings 14-pin output Peak AGL seenege SYNC-6dB SG-A [ 357mV -f--. Pp-p detection of the 100% --E715mV | bite all field output GAIN measure- ment woul eee NTSC standard Y signal 357mv 500mVp-p SG-A SYNC 0dB ' H “F443mv 100% white hot ' te oo Sys TK 4.5ys 15yS*) | DC is measured at the ' SYNC and VIDEO timings, i ' and the difference is 14-pin SYNC VIDEO specified. ~14-

SGA aan 210mvp-p color burst. ui ct 3.58MHz “Yramy 1) DC is measured at the belo timings of SYNC and ' Sys VIDEO 7 1 ----25V 2) The SYNC delay and 16-pin output ' pulse width are meas- tw osv ured for the output. d ---0. he td p-p detection at the oi 5 — -- —— r timings of SYNC and 14-pin output VIDEO, Serial data 1/O Test Method H $G23 (CS) 1 ho bo mo 1 . yo seach fy fF 1 L 1 i i | ro t i I | $G25 (SI) ‘tps 59590" to) '® 1 ' ! \\ ' ! p-p detection at ! H 1 w2--p-- the CK timing. so ce WW it jeasure the APL be el fe delay between CK and SO. -15-

Serial Data Input Example _ (H & L of CMOS are used.) H 6 be SG23 — _ IN1, AGC ON, MUTE OFF L “TLE LELE LE Each timing and cycle are S$G24 ! ro same as in the serlal data # | TFL LL 1/O test method. $G25 to at qs 5ocns H i $G23 t $G24 : TLELlY 1S IN2, AGC ON, MUTE OFF L i a $G23 L sGo4 as ee ee IN3, AGC ON, MUTE OFF seas ee ee ee Ll H i $G23 L

4 PBIN, AGC ON, MUTE

L 3 _ ce ee 0 SG23 4 t $G24 L of UU IN1, AGC ON, MUTE ON $G25 Lt iyS 500nS H i $G23 L qo sG24 L ~LELELE LS IN1, AGC OFF, MUTE OFF $G25 4 ee es ee L - 16 -

©-8 i ©) Be or @4s0 « ey os ol @ 78 . 2 3 : ae \\ pode se Or sk Ori 5 =O-Te et 8 3 3 fs a = On Ho 2OH8 re a ei yi © 2 ope ue Hb J ui 8 = ®3--- A “TO ¢ z ty v/ L 8) { ‘ Fi Or it OH atk ey a z= @z 8) > O 3] 3 alti aria dp i aed a eS mer © Blues ©= © e the |/-4 |] TURE 2 a = Slat 3 2 8 88 2 : @; npr & 3 . E s © gS gk be S Shs 3 @le PE Soap : @43 Lt 1d e

8 Ors

g Lote. E 3 oO mB ge ai -17-

Package Outline = Unit:mm CXA1201M 30pin SOP (Plastic) 375mil 0.79 rep'tt 23's als} .| | [fortes BURBOSHBOHHHUBE 4 oastt 272028 015 Bs Oe TT I NE0e0-COOE| = gene) CXA1201Q 32pin GFP (Plastic) 0.2¢ 32pin GFP (Plastic) 0.29 109.0 #92 ono!t 90%? say9( WLS] a5 t88 sas’? GAAH08R4 Pp LAA AA A f Haegeeqaqa f ‘ial HHARRAR A ast od 16 Ky It as bo ir} 16 ox = Yt on on ox} = = fl mi | on mia) ox} — =a m= Ps om om a ox Eo mo 3 a - or} arm sg ox oo = f Ct or} ate) ox = Ch I or oD am poe Host xa) Fm » yoo ee teint S sosuin HHEBEEEASE ) eel WHHHRHHH : “al evel HHEEARAA = ga os SHELL ereareyay 0427 sine tT Tos pases! [* a § ornsor [Sony wane] GP=a2P=L01 | [eta nave orPose-p-o707- ~ 18 -

Product Information

CXA1201Q specifications and overview.

Summary

VCR IMAGE I/O SIGNAL PROCESSING

Description

VCR IMAGE I/O SIGNAL PROCESSING

Source title CXA1201Q Datasheet(PDF) - Sony Corporation

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