CXA1016P SONY | Alldatasheet
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SONY. CXA1016P/CXA1016K/ CXA1056P/CXA1056K 8 bit 30/50 MSPS Flash A/D Converter ———e~ee'resee _>=ave®gq0sSSsmmoeeem Evaluation Board Avai — CXA1016PPCB/CXA1016KPCB i Board Available — Cya1os6PPCB/OXA10S6KPCB
Description
CXA1016P/CXA1016K/CXA1056P/CXA 1056K are 8 bit (28 pin DIP (Plastic) 44 pin LCC (Ceramic) high-speed A/D converter ICs for various applications. They can be used widely for various purposes which require high- speed A/D conversions. CXA1016P/CXA1056P are assembled in the plastic DIP packages and CXA1016K/CXA1056K are in the ceramic TRE gS lead-less chip carriers. Ni Features (CXA1016P/CXA1016K) + Resolution 8 bits + 1/2 LSB + High-speed operation Maximum conversion Rate 30 MSPS + Wide analog input bandwidth 30MHz (—3d8) + Low input capacitance 35 pF (typ) + Low power consumption 420 mW (typ) Features (CXA1056P/CXA1056K) + Resolution 8 bits + 1/2 LSB « High-speed operation Maximum conversion Rate 50 MSPS + Wide analog input bandwidth 50MHz (-3dB) + Low input capacitance 35 pF (typ) + Low power consumption 550 mW (typ) a Block Diagram vin var ° Ho tir | sor HH > 2 06 i « © els } gre E Yam © 83 8 Ba] *° g ie 3 | 3 74 2]: i © DO Ute tt) cLK © tT minv °? Lin E89643-ST
SONY. (CXA1O16P/CXAT016K /CXA1056P/CXA1056K Absolute Maximum Ratings (Ta=25°C) + Supply voltage Vee 0 to -7 v + Analog input voltage vin 05 to Vee v + Reference input voltage Var, Vra, VAM 0.5 to Vee v | Var-Vae | 25 v + Digital input voltage CLK, CLK, MINV, LINV 0.5 to —4 v + VRM pin input current Wan —3to+3 mA + Digital output current IDo to 1D? Oto-10 = mA + Operating temperature Ta ~20 to +100 °C (CXA1016P/CXA1056P) Te 25 to +125 °C (CXA1016K/CXA1056K)"? + Storage temperature Tstg —55 to +150 °C + Allowable power dissipation Po 1.48 W (CXA1016P/CXA1056P)
1.08 W (CXA1016K/CXA1056K)
+1 Heat sinking is required above 100°C (CXA1016K)/86°C (CXA1056K) Recommended Operating Conditions (CXA1016P/CXA1016K) Min. Typ. Max. Unit « Supply voltage Avec, DVee = 5.7 —5.2 -5.0 V AVee-DVee — —0.05 0 0.05 Vv AGND-DGND —0.05 0 0.05 Vv + Reference input voltage Var -01 0 or ov Vara -22 -2 -18 Vv + Analog input voltage vin Vas Vat + Clock pulse width Tpwt 25 ns Tpw0 8 ns Recommended Operating Conditions (CXA1056P/CXA1056K) Min. Typ. Max. Unit + Supply voltage Ave, DVee = 5.7 5.2 -5.0 V AVee—DVee -—0.05 0 0.05 Vv AGND—DGND —0.05 0 0.05 Vv + Reference input voltage Var -0.1 ° o1 ov Vas 22-2 -18 Vv + Analog input voltage vin Vae Var + Clock pulse width Tpw1 15 ns Tpwo 5 ns 54 —
SONY: (CKA1016° /OKA1016K /CXA1056P /CXA1056K Pin Configuration (Top View) The pin numbers without indication are empty pins. (not connected) cxA1016P/CXA1056° uinv © @ Avec veE®@ @ var pGno@) @ Aver (188) 00 @) @ acno 1 ® @ vin o © €3 AGNO 3 @ @ Van on ® @) AGND 2 @ @ Vin CnC) © Acno (sai 07 ¢ @ Avec OGNo @ ® Vas Over (3) @ cix MINv 69 @ cK CXA1016K/ CXAIO56K 2,222,2 ZocGZ5
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Aver SAIS SE S32) aver Aver |! a Aveg vat 28) VRB AVEE 28 a =! 23 cu 2 | CLK un & 2} minv Over {* OVee GN Vi ‘9 ono é tol ocn| ‘Cet 91 10) 11] sal 31 14] 154 64 "SBss888ss5e 3 B8 2 2 — 55 —~
SONYs CXAI016P/CXA1016K /CXA1056P /CXA1056K Pin Description Symbol Function Analog Vee, —5.2V (typ). Coupled with ~6 between DVer. uNV Input pin for output polarity inversion of Do (LSB)~Ds. (See the code table) Digital Vee, —5.2V (typ). DGND | Digital GND, which is separated from the Analog GND. Digital data output pin, ECL level. Do: LSB~D7: MSB. Do~0r Pull-down resistors are necessary externally. inv | !8PUt pin for output polarity inversion of D7 (MSB) (See the code table). ECL level. “0” level is held when it is released. CLK Inverse clock input pin, ECL level. Clock input pin, ECL level. Reference voltage (bottom), —2V (typ). AGND | Analog GND Analog input. input range is VatT~VaB Middle point of the reference voltage, it can be used as a linearity correction pin. Reference voltage (top), OV (typ). Empty pins (not connected), 2 and 19 are used to be grounded to DGND, the others are used to be grounded to AGND. Output Coding MINV 1 uNV 1 56 —~
SONYe CXA1016P.CXA1016K /CXA 1056P/ CXA1056K eee we AOIGPCKATONBKCXATOSEP/CXATOSEK (Ta=28°C, Vee=—5.2V, VaT=OV, Vas=—2V) [ee Spt aon an [ie [me [0 Vin=0 to —2V, [Mexmum conversion ate] Fe | fin=1 kHz, ramp 8° [| [srs Supply Current fee 5 |= 00 [ma | Analog input Capacitance Vw=—1v+0.07 vims_ | | 35 | 40 | pF | Rr(Var~Vr) | 70 | 80 [100 | a | [over fe a ew | Offset Voltage - vee | 15 | 17 | 19 | mv | Digital Input Voltage ~ | =28 | a ee c Vie=—0.9V Digital input Current ak o{ [oa ['m Digital Output Voltage ki RO=620N ~ Vee [of | pt fre [ vy | Output Data Delay Td RO=6200 ~ Vee | | 40 | 50] ns | Fe=30 MSPS, | Non-linearity Error Vin=0 to —2V, ti | LSB fin=1 kHz, ramp Differential Non-linearity | +m | ise Error i i] [peer ger fae ed [saneingbeey sf ace *1 Source impedance = 509 Without @ buffer amplifier driving A/D input
SONYse (CXA1016P,/CXA1016K /CXA1056P,/CXA1056K. (Te=28°C, Vee=—5.2V, Var=OV, Vas=—2V) [— tem symbot_conaition tin. | typ. [Max [ unit] fiat tte am [| | [ses | fin=1 kHz, ramp Supply Curent poe 95 [120] ma _| Analog Input Capacitance vin=—1v+0.07 vims |__| 38 | 40 | pF Analog Input Bias Current | tw | vwe—iv || 78 | 118 | na Re (Var~vesy | | 0 | 80 | 100 | a | [ve fo i ew | Offset Voltage re [ove =r 9 [ots [=r6[ v_ Digital Input Current wo | wenizev | =0.08| 0.35 | ma pl Digital Output Voltage on R2=6200 ~ Vee | =10 | rs Output Data Delay ne=e20n ~ve | | 40 | 50 | ns | Fe =50 MSPS, Non-linearity Error Vin=0 to —2V. tie | LsB fin=1 kHz, ramp Differential Non-linearity +m | ise Error | Diterentiat Gain | os sc aoe moa, =| | 8 | | Differential Phase [op | mn Fe=somsrs | || 08 | aes. | [avenue ser we oo *1 Source impedance = 502 Without a buffer amplifier driving A/D input — 58 —
SONY: (CKAI016/CXA1016K /CXA1O56P//CXA1056K meee CAIONCR CHAT OBGR./CXAIOSBK Electrical Characteristics Test Circuit Maximum Conversion Frequency Test Circuit Differential Gain Error Test Circuit Differential Phase Error Test Circuit ts ov -2v (©x20202) > in 8) Q, ~~ pur Le ec [8 to bit ° 20 j Latch f OVA cK Ntsc 3 Signe! 4 Source 06 | vector Oscino _ ” Nonlinearity Maximum Conversion Rate Differential Nontinearity Test Circuit Integral NonJlinearity Test Circuit g +V 4 $1: A<B:ON <I hg, 1 S2:A>B:0N ee i i i -vid A<B A>B vw Comparator OUT 8 As Be 8 A By Ao Bo. 000:--00 to ms —59
SONYe (CXA1016P/CXA1016K /CXA1056P,/CXA1 056K Power Supply Current Test Circuit Analog Input Bias Current Test Circuit nv § yom tw 3 © — or _{| a Ht | -_ i 4 [| =ev
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SONY: CXA1016P/CXA1016K/CXA 1056P /CXA1056K Description of Function (See the block diagram and timing chart.) 1. The reference voltage, which is obtained by dividing equally the voltage across Var to Vrs into 256 by the reference resistor ledder, is applied to the respective © (positive) input sides of 256 clocked comparators. An analog input is applied to the © (negative) input sides of all the 256 clocked comparators from the VIN pin. 2. When the state of CLK is in Low, the master (front stage) of the comparator compares the respective reference voltage and the analog input voltage which is ever-changing. 3. When the CLK moves from Low into Hi, each master latches the state immediately prior to the sequence from the Vt side to the Vre side. 4. The output of the master is ANDed between the respective adjacent outputs, and “1” stands only when neighboring 2 outputs become “10”, and the all other outputs become “0”. 5. The result of the AND is latched when CLK moves from Hi into Low. Output of the slave is divided into 4 blocks and each block has 32 clocked comparators, and they are coded into binary codes of 6 bits respectively by the transistor matrix circuit. 6. The 6 bit codes are further coded into 8 bit codes by the transistor matrix circuit after they are respectively latched, and they are then output into the ECL level by the output buffer after being 8 bit latched. The output data is delayed 1 clock from the data sampling point and appears at the output pin. 7. Two polarity inversion inputs such as MINV and LINV are fed externally to the output buffer, and each of them selects output polarity of MSB and other polarity than MSB respectively. —6l —
SONYe (CXA1016P /CXA1016K /CXA1056P/CXA1056K Timing Chart fl ' ig N Ne ' ne ‘Ansiog input VIN ? 1 > | Tew! eke Tewo Clock CR == porns ph ator output Master Y YYY [UX XX cmemecannm — “XM _. _XXXM XXX on oe Dots (#) in the chart demote respective latch timings, “See page 54 for Tpwi and Tpwo.
SONYe CXA1016P/CXA1016K /CXA1056P /CXA1056K See ITIP IANTOR/CHAIOSSP/CXAIOSEK Package Outline Unit: mm CXA1016P/CXA1056P 28 pin DIP (Plastic) 370° “ol a 3ST 0*t015* D S| 254. z\\s3 Fits ala EB z os. 204 FA 1.2 *048 DIP-28P-03 CKATOTEKICXATOS6K 44 pin LCC (Ceramic || Yo 127, Q —; 3 Gomme 33 5] & ANNO & Faia = E ca =e q Roz S| Z = oj} = r= i Cannnnnnnnnn? Ss = ae T yz cary 2.159 205) a 12,5202 ball ne | ay a a3 Lcc-44c-01 —6—
SONY CORP/COMPONENT PRODS 18E D MM 8382383 OOOOLOL 3 mm Sony Package Product Name 7-90-20 Package name Type Package ane P | 254mm Through . iE MY | auosns | Hele PACKAGE 2 ¢ Lead SINGLE Through sup | IN LINE rl 2st uy | Hele PACKAGE mal coo) | eg 2G ZAG 254mm Through Standard | Z1P | IN LINE Td teu Hole } PACKAGE inline _| “04 & | PIN Through PGA | GRID Hole L | ARRAY Lead = — | pack | BACK a ae (woomiy | pend i SHRINK : Through pci spip | DUAL 178mm Shrink SDIP | Wy LINE << PY) “con | Het PACKAGE Suet | QuaD a QFp | FLAT B Ae Standard flat PACKAGE iis package SMALL: atmm OUTLINE a 2direction PACKAGE ar (somtL) VERY SMALL |. vare | quan <p> 03mm ving 4-direction Shrink flat PACKAGE package VERY SMALL . j OUTLINE a 965mm E PACKAGE g PLASTIC a pioc | LEIpEP S} Jebend | ¢-direction Standard chip CARRIER carrier LEAD LESS ne 127mm Lee | cHiP & | ame ay | bead tess CARRIER SHRINK | SPLCC PLASTIC 1.27mm Max, CRADED SOMIL Max) , SMALL Standard OUTLINE 127mm 2direction | SO} | PoEAD (sent chip carrier PACKAGE *PePlastic, Con-Ceramic . —3-—