CTK24BC01-16P8

CTK24BC01-16P8 CYSTEKEC | Alldatasheet

Document overview

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Technical content

Features

• Internally organized as 128×8(1K), 256×8(2K) • 100kHz(1.8V)& 400kHz(5V) compatibility 512×8(4K), 1024×8(8K), 2048×8(16K) • Bi-directional data transfer protocol
• Low-voltage and standard-voltage operation : • Self-timed write cycle (5ms max) 1.8~5.5V • Write protect pin for hardware data protection
• 2-wire serial interface bus • 8-byte page (1K, 2K) and 16-byte page (4K, 8K, 16K)
• Date retention : 100 years write modes
• High endurance : 1,000,000 write cycles • Allows for partial page write Absolute Maximum Ratings Parameter Ratings Unit Voltage on any pin with respect to ground -0.8 to VCC+1.5 V Maximum operating voltage 6.25 V DC output current 5.0 mA Operating temperature range -55 ~ +125 ℃ Storage temperature range -65 ~ +150 ℃ Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of these specifications are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

CYStech Electronics Corp. Spec. No. : C705P8 Issued Date : 2007.08.23 Revised Date : Page No. : 2/12 CTK24BC01-16P8 CYStek Product Specification Pin Configurations Pin Name Function A0-A2 Address inputs SDA Serial data SCL Serial clock input WP Write protect Gnd Ground VCC Power supply Block Diagram

CYStech Electronics Corp. Spec. No. : C705P8 Issued Date : 2007.08.23 Revised Date : Page No. : 3/12 CTK24BC01-16P8 CYStek Product Specification Pin Descriptions Serial Data(SDA): The SDA pin used for sending and receiving data bits in serial mode. Since the SDA pin is defined as an open-drain connection, a pull-up resistor is needed. Serial Clock(SCL): The SCL input is used to synchronize data input and output with clocked out on the falling edge of SCL. Device/Page Addresses(A2, A1, A0): The A2, A1, and A0 pins are used to address multiple devices on a single bus system and should be hard-wired.

• The CTK24BC01 and CTK24BC02 use the A2, A1 and A0 pins to provide the capability for addressing up to eight 1K/2K devices on a single bus system (please see the Device Addressing section for further details)
• The CTK24BC04 uses the A2 and A1 inputs and a total of for 4K device may be addressed on a single bus system. The A0 pin is not used, but should be grounded if possible.
• The CTK24BC08 only uses the A2 input hardware addressing. On a single bus system, a total of two 8K devices may be addressed. The A0 and A1 pins are not used, but should be grounded if possible.
• The CTK24BC16 does not use the device address pins, so only one device can be connected to a single bus system. Therefore, the A0, A1, and A2 pins are not used, but should be grounded if possible. Write Protect (WP): The CTK24BC01/02/04/08/16 has a Write Protect pin that provides hardware data protection. When connected to ground, the Write Protect pin allows for normal read/write operations. If the WP pin is connected to VCC, no data can be overwritten. Memory Organization The internal memory organization for the CTK24BC family is arranged differently for each of the densities. The CTK24BC01, for instance, is internally organized as 16 pages of 8 bytes each and requires a 7-bit data word address. The CTK24BC16, on the other hand, is organized as 128 pages of 16 bytes each with an 11-bit data word address. The table below summarizes these differences. Density # of pages Bytes per page Data word address length CTK24BC01 (1K) 16 pages 8 bytes 7 bits CTK24BC02 (2K) 32 pages 8 bytes 8 bits CTK24BC04 (4K) 32 pages 16 bytes 9 bits CTK24BC08 (8K) 64 pages 16 bytes 10 bits CTK24BC16 (16K) 128 pages 16 bytes 11 bits Pin Capacitance Applicable over recommended operating range :TA=25℃, f=1MHz, VCC=+1.8V Symbol Test Condition Max Unit Condition CI/O Input/Output Capacitance (SDA) 8 pF VI/O=0V CIN Input Capacitance (A0, A1,A2, SCL) 6 pF VIN=0V Note : These parameters are characterized and not 100% tested.

CYStech Electronics Corp. Spec. No. : C705P8 Issued Date : 2007.08.23 Revised Date : Page No. : 4/12 CTK24BC01-16P8 CYStek Product Specification DC Characteristics Applicable over recommended operating range: TA=-40~+85℃, VCC=+1.8V~+5.0V(unless otherwise noted) Parameter Symbol Condition Min. Typ. Max. Unit Supply V oltage VCC 1 1.8 - 5.5 V Supply V oltage VCC 2 2.7 - 5.5 V Supply V oltage VCC 3 4.5 - 5.5 V Supply Current VCC=5.0V ICC READ at 100KHz - 0.4 1.0 mA Supply Current VCC=5.0V ICC WRITE at 100KHz - 2.0 3.0 mA Standby Current VCC=1.8V ISB 1 VIN=VCC or VSS - 0.6 3.0 μA Standby Current VCC=2.5V ISB 2 VIN=VCC or VSS - 1.4 4.0 μA Standby Current VCC=5.5V ISB 3 VIN=VCC or VSS - 5.0 18 μA Input Leakage Current ILI VIN=VCC or VSS - 0.2 5.0 μA Output Leakage Current ILO VOUT=VCC or VSS - 0.1 5.0 μA Input Low Level (Note 1) VIL -0.6 - VCC×0.3 V Input High Level (Note 1) VIH VCC×0.7 - VCC+0.5 V Output Low Level VCC=3.0V VOL 2 IOL =2.1mA - - 0.4 V Output Low Level VCC=3.0V VOL 1 IOL =0.15mA - - 0.2 V Note : VIL and VIH Max are reference only and are not tested. AC Characteristics Applicable over recommended operating range: TA=-40~+85℃, VCC=+1.8V~+5.0V , CL=1 TTL Gate & 100pF(unless otherwise noted) Parameter Symbol Condition Min. Typ. Max. Unit Clock Frequency, SCL fSCL VCC=1.8V

400 KHz

Clock Pulse Width Low tLOW VCC=1.8V VCC=2.7~5.5V 4.7 1.2 - - μs Clock Pulse Width High tHIGH VCC=1.8V VCC=2.7~5.5V 4.0 0.6 - - μs Noise Suppression Time (Note 1) tI VCC=1.8V 50 ns Clock Low to Data Out Valid tAA VCC=1.8V VCC=2.7~5.5V 0.1 0.1 - 4.5 0.9 μs Time the bus must be free before A new transmission can start (Note 1) tBUF VCC=1.8V VCC=2.7~5.5V 4.7 1.2 - - μs Start Hold Time tHD.STA VCC=1.8V VCC=2.7~5.5V 4.0 0.6 - - μs Start Setup Time tSU.STA VCC=1.8V VCC=2.7~5.5V 4.7 0.6 - - μs Data in Hold Time tHD.DAT VCC=1.8V VCC=2.7~5.5V 0 - - μs Data in Setup Time tSU.DAT VCC=1.8V VCC=2.7~5.5V 200 100 - - ns Input Rise Time (Note 1) tR VCC=1.8V 0.3 μs Input Fall Time (Note 1) tF VCC=1.8V 300 ns

CYStech Electronics Corp. Spec. No. : C705P8 Issued Date : 2007.08.23 Revised Date : Page No. : 5/12 CTK24BC01-16P8 CYStek Product Specification AC Characteristics(Cont.) Applicable over recommended operating range: TA=-40~+85℃, VCC=+1.8V~+5.0V , CL=1TTL Gate & 100pF(unless otherwise noted) Parameter Symbol Condition Min. Typ. Max. Unit Stop Setup Time tSU.STO VCC=1.8V VCC=2.7~5.5V 4.7 0.6 - - μs Data out Hold Time tDH VCC=1.8V VCC=2.7~5.5V 100 50 - - ns Write Cycle Time tWR VCC=1.8V VCC=2.7~5.5V - - 5 5 ms 5.0V , 25℃, Byte Mode Endurance (Note 1) VCC=1.8V VCC=2.7~5.5V 1M - - Write Cycles Note: 1. This parameter is characterized and not 100% tested. Device Operation Clock and Data Transitions: Transitions on the SDA pin should only occur when SCL is low(refer to the Data Validity timing diagram in Figure 3). If the SDA pin changes when SCL is high, then the transition will be interpreted as a START or STOP condition. START Condition: A START condition occurs when the SDA transitions from high to low when SCL is high. The START signal is usually used to initiate a command(refer to the START and STOP definition timing diagram in Fig 4) STOP Condition: A STOP condition occurs when the SDA transitions from low to high when SCL is high. (refer to the START and STOP definition timing diagram in Fig 4) The STOP command will put the device into standby mode after no acknowledgement is issued during the read sequence. Acknowledge: An acknowledgement is sent by pulling the SDA low to confirm that a word has been successfully received. All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words, so acknowledgements are usually issued during the 9 th clock cycle. Standby Mode: Standby mode is entered when the chip is initially powered-on or after a STOP command has been issued and any internal operations have been completed. Memory Reset: In the event of unexpected power or connection loss, a START condition can be issued to restart the input command sequence. If the device is currently in write cycle mode, this command will be ignored.

Figure 8. Page Write can be loaded. The device will send an acknowledgement after each byte to confirm the transmission. operations are supported, so the STOP condition can be issued after the 1st byte or the last byte in the page. not respond to any more commands until the write cycle is completed. Organization section for more details. acknowledgement will be sent. bytes are clocked out after a current address read or random address read occurs.

last address incremented by one. different address into the internal counter, and the data can then be accessed using the current address read. been initiated, the user should send an acknowledgement to the EEPROM chip after each data byte received. condition on the next cycle to reset back to standby mode(refer to Figure 11). condition, the sequential read operation is terminated. Figure 9. Current Address Read

CYStech Electronics Corp. Spec. No. : C705P8 Issued Date : 2007.08.23 Revised Date : Page No. : 12/12 CTK24BC01-16P8 CYStek Product Specification DIP-8P Dimension Marking: Memory: 1K: 01 24BC □□ c 0.008 0.014 0.203 0.356 Notes : 1.Controlling dimension : millimeters. 2.Maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.If there is any question with packing specification or packing method, please contact your local CYStek sales office. Material :

• Mold Compound : Epoxy resin family, flammability solid burning class:UL94V-0 Important Notice:
• All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of CYStek.
• CYStek reserves the right to make changes to its products without notice.
• CYStek semiconductor products are not warranted to be suitable for use in Life-Support Applications, or systems.
• CYStek assumes no liability for any consequence of customer product design, infringement of patents, or application assistance. DIP-8P Plastic Package CYStek Package Code : P8 2K: 02 4K: 04 8K:08 16K:16 □□□□ Date Code