CSP1027 AGERE | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 64
Technical content
CSP1027 Voice Band Codec for Cellular Handset and Modem Applications
1 Features
■ Δ-Σ (delta-sigma) A/D and D/A converters with stan- dard 16-bit serial I/O interface. ■ On-chip filters meet ITU-T G.712 voice band fre- quency response and signal to distortion plus noise specifications. Suitable for IS-54, GSM, and JDC dig- ital cellular applications. ■ Low-profile package (<1.5 mm) 48-pin thin quad flat pack (TQFP) available or 44-pin EIAJ quad flat pack (QFP). ■ Operates in systems with a 3.0 V to 5.0 V digital power supply and a 5.0 V analog supply. ■ Low-power 0.9 µm CMOS technology, fully static design, typical power of 68 mW when active and 0.05 mW in standby with a 3.3 V digital supply and a 5.0 V analog supply. ■ A low-power inactive (standby) state without stopping clock or removing power supply. ■ Sampling rates up to 24 kHz. ■ On-chip programmable sampling clock generator allows input clock to be an integer multiple of 125 times the sampling rate or an integer multiple of the sampling rate. ■ Programmable phase adjust of both codec sampling clock and baseband codec clock. ■ Two on-chip clock dividers for generating the output clock for the baseband codec and the output clock for other processors. ■ Regulated microphone power supply. ■ Microphone preamplifier, with programmable input ranges of 0.16 Vp and 0.5 Vp. ■ Output amplifier, with programmable gain settings, 0 dB to –45 dB in –3 dB steps. ■ High-pass filters selectable via control registers. ■ Power-on reset pulse generator. ■ Standard 16-bit serial I/O interface. ■ Serial I/O multiprocessor mode compatible with the Lucent Technologies Microelectronics Group’s DSP16A and DSP1610/1616/1617/1618 Digital Sig- nal Processors.
2 Description
The Lucent CSP1027 is a high-precision linear voice- band Δ-Σ (delta-sigma) codec designed for cellular handset and modem applications. The device is fabri- cated in low-power CMOS technology and designed for low-voltage (3.0 V to 5.0 V) digital systems. The CSP1027 is packaged in a 44-pin EIAJ quad flat pack (QFP) or a 48-pin EIAJ thin quad flat pack (TQFP). In the 48-pin TQFP , the CSP1027 occupies a total volume of 0.0784 cm The CSP1027 has a variety of significant programma- ble features not found in standard voice band codecs. The analog interface includes a microphone preampli- fier with programmable gain settings, an output ampli- fier with gain programmable in 3 dB steps over a 45 dB range, and a regulated microphone power supply. An inactive mode allows a low-power standby state, and a mute function provides suppression of the analog out- put. On-chip antialiasing and anti-imaging filtering includes a selectable high-pass filter. The CSP1027 meets ITU-T G.712 voice band specifications. The programmable features of the CSP1027 are set by writing four on-chip control registers through the serial I/O interface. The codec’s digital input/output uses a linear 16-bit two’s complement data format that is also transferred through the serial I/O interface. The CSP1027 interfaces easily to the 16-bit serial ports of digital signal processors and other devices. The serial interface supports the Lucent fixed-point DSP family serial multiprocessor mode. This allows up to eight compatible devices, including two CSP1027s, to inter- face to each other on a common 4-wire bus using a time-division-multiplexing scheme.
CSP1027 Voice Band Codec for Data Sheet Cellular Handset and Modem Applications December 1999 Lucent Technologies Inc.2 Table of Contents Contents Page
3 Pin Information
Figure 1. 44-Pin EIAJ Quad Flat Pack (QFP) Pin Diagram Figure 2. 48-Pin EIAJ Thin Quad Flat Pack (TQFP) Pin Diagram
32 SMODE2
25 IOCK
37 RES
3 Pin Information(continued)
Functional descriptions of the pins are found in Section 6 on page 30. Table 1. Pin Descriptions 4 4 SMODE1 I Serial Mode Select 1. 5 5 SMODE0 I Serial Mode Select 0. 11 12 CKO1 O Clock Output 1. 15 16 XOSCEN I Crystal Oscillator Enable. 16 17 CKO2 O Clock Output 2. 18 19 SADD I/O † Serial Address. 19 20 DI I Serial Input Data. 20 21 DO O † Serial Output Data. 21 22 V DD P Digital Power Supply. 22 24 SYNC I/O † Serial Input/Output Load Strobe and Synchronization. 23 25 IOCK I ‡ Serial Clock. 30 33 PORB O Power-On Reset Output. 31 34 PORCAP I § External Capacitor Connection for Power-On Reset. 32 35 SMODE2 I Serial Mode Select 2. ** External Input Gain Select. 34 38 V SSA P Analog Ground. 35 39 V REG A Regulated Output Voltage for Electrect Condenser Microphone. 36 40 V DDA P Analog 5.0 V Power Supply. 37 41 AOUTN A Inverting Analog Output of Output Amplifier. 39 43 AOUTP A Noninverting Analog Output of Output Amplifier. 41 45 MICIN A Analog Input for Microphone. 42 46 REFC A External Capacitor Connection for Internal Voltage Regulator. 43 47 AUXIN A Analog Input from Auxiliary. DDA P Analog 5.0 V Power Supply. ‡ Indicates pull-up device on input. § Indicates pull-up resistor on input. ** Indicates pull-down device on input.
4 Architectural Information
Figure 3. CSP1027 Block Diagram
1 MHz OVERSAMPLING CLOCK
CSP1027 Voice Band Codec for Data Sheet Cellular Handset and Modem Applications December 1999 Lucent Technologies Inc.6
4 Architectural Information(continued)
4.1 Overview
The CSP1027 is a complete analog-to-digital and digi- tal-to-analog acquisition and conversion system (see Figure 3 on page 5) that band limits and encodes ana- log input signals into 16-bit PCM, and takes 16-bit PCM inputs and reconstructs and filters the resultant analog output signal. The selectable A/D input circuits, pro- grammable sample rates, and digital filter options allow the user to optimize the codec configuration for either speech coding or voice band data communications. The on-chip digital filters meet the ITU-T G.712 voice band frequency response and signal to distortion plus noise specifications and are suitable for IS-54, GSM, and JDC digital cellular applications. In addition, the small supply current drain, when powered down, extends battery life in mobile communication applica- tions. The CSP1027 is intended for both voice band voice and data communication systems. As a result, this codec has a variety of features not found in standard voice band codecs: ■ 3.0 V regulated power supply for a condenser micro- phone. ■ Microphone preamplifier with programmable input ranges. ■ Mute control of D/A output. ■ Programmable output gain in 3 dB increments. ■ Output speaker driver. ■ Programmable master clock divider to set A/D and D/A conversion rate. ■ Testability loopback mode. ■ High-quality dither scheme to eliminate idle channel tones.
4.2 Description of Signal Paths
4.2.1 Sampling Frequency
The oversampling ratio of the codec is 125:1; this is the ratio of the frequency of the oversampling clock to the frequency of the sampling clock. Most speech applica- tions specify a sampling frequency of 8 kHz, yielding an oversampling frequency of 8 kHz x 125 = 1.0 MHz. The codec will operate at sampling frequencies up to 24 kHz, with the frequency response of the digital filters being changed proportionally. For this architectural description, the sampling frequency, f S, is assumed to be 8 kHz, with an oversampling frequency, fOS , of 1 MHz, unless otherwise stated.
4.2.2 Analog-to-Digital Path
The analog-to-digital (A/D) conversion signal path (see Figure 3 on page 5) begins with the analog input driving the input block. The signal from the input block is then encoded by a second-order Δ-Σ modulator A/D. The bulk of the antialiasing filtering is done in the digital domain in two stages following the Δ-Σ modulator to give a 16-bit result. The blocks will next be covered in more detail.
4.2.3 Analog Input Block
The A/D input block operates in two modes: when the external input gain select (EIGS) pin is low or left unconnected, the input goes through a preamplifier and is band limited by a second-order 30 kHz low-pass anti- aliasing filter (see Figure 4 on page 7). When EIGS is high, external resistors, Rin and Rfb, are used to set the gain of an inverting amplifier (see Figure 5 on page 7). These resistors, in combination with Cin and Cfb, cre- ate a bandpass antialiasing filter. Note that EIGS is a digital pin whose input levels are relative to digital power and ground (V DD and VSS ).
4.2.4 A/D Modulator and Digital Filters
A second-order Δ-Σ modulator quantizes the analog signal to 1 bit (see Figure 3 on page 5). At the same time, the resulting quantization noise is shaped such that most of this noise lies outside of the baseband. The modulator output is then digitally low-pass filtered to remove the out-of-band quantization noise. After this filtering, the output samples are decimated down to the output sampling frequency. In the CSP1027, the filter- ing and decimation are completed in two stages. The first-stage low-pass filter shapes the modulator output according to the sinc-cubic transfer function: The output sampling frequency of the sinc-cubic filter is reduced by a factor of 25 from 1 MHz to 40 kHz. The sinc-cubic filter places nulls in the frequency response at multiples of 40 kHz, and removes most of the quanti- zation noise above 20 kHz so that very little energy is aliased as a result of the decimation. The sinc-cubic filter output is then processed by a seventh-order IIR digital low-pass filter. This filter removes the out-of-band quantization noise between 3.4 kHz and 20 kHz, compensates for the passband droop caused by the sinc-cubic decimator, and deci- mates the sampling frequency by a factor of five from 40 kHz to 8 kHz. Hz() 1 1z 1––()
Figure 4. CSP1027 A/D Path When in the Preamplifier Mode (EIGS = 0) Figure 5. CSP1027 A/D Path in the External Gain Select Mode (EIGS = 1)
4.2.5 A/D Path Frequency Response
normalized to the sampling period 1/fS (i.e., delay x fS).
4.2.6 PCM Saturation Versus Analog Input Levels
Figure 6. A/D or D/A Path Frequency Response Over 5.0 fS Bandwidth (HPF Disabled) Figure 7. A/D or D/A Path Frequency Response Over 2.5 fS Bandwidth (HPF Disabled)
Figure 8. A/D or D/A Path Frequency Response Over fS Bandwidth (HPF Disabled) Figure 9. A/D or D/A Path Frequency Response Over 0.5 fS Bandwidth (HPF Disabled)
Figure 10. A/D or D/A Path Absolute Group Delay (HPF Disabled) Figure 11. A/D or D/A Path Group Delay Distortion (HPF Disabled)
Figure 12. A/D or D/A Path Frequency Response Over fS Bandwidth (HPF Enabled) Figure 13. A/D or D/A Path Frequency Response Over 0.5 fS Bandwidth (HPF Enabled)
Figure 14. A/D or D/A Path Absolute Group Delay (HPF Enabled) Figure 15. A/D or D/A Path Group Delay Distortion (HPF Enabled)
Lucent Technologies Inc. 13 Data Sheet CSP1027 Voice Band Codec for December 1999 Cellular Handset and Modem Applications
4.2.7 Digital-to-Analog Path
Starting at the bottom right of Figure 3 on page 5, the Δ-Σ D/A conversion process begins with a 16-bit two's complement PCM signal read from the DI serial input. The PCM is interpolated up to 1 MHz in two stages and low-pass filtered at each stage to attenuate 8 kHz images. The PCM input is latched into the cdx(D/A) register at a nominal word rate of 8 kHz. The signal is then option- ally high-pass filtered. This filter has the same transfer function as the A/D high-pass filter. A digital sample-and-hold increases the word rate by a factor of 5 from 8 kHz to 40 kHz. The seventh-order IIR digital low-pass filter then removes the spectral images between 4 kHz and 20 kHz and predistorts the pass- band to compensate for the filtering done during the interpolation up to the 1 MHz word rate. The transfer function of this low-pass filter is the same as the one employed in the A/D converter. The output of the low-pass filter feeds a programmable gain adjustment block that serves as a volume control. The gain can be changed in 3 dB increments from 0 dB to –45 dB. The attenuation level is set by writing the OGSEL field in the cioc0 register (see Table 7 on page 26). The digital modulator block further increases the word rate by a factor of 25 from 40 kHz to 1 MHz. Through quantization and noise shaping, the digital Δ-Σ modula- tor creates 1-bit output words at 1 MHz. The modulator 1-bit output drives a structure combining a 1-bit D/A converter and a second-order switched- capacitor filter having a cutoff frequency of 8 kHz (based on a 1 MHz clock). This is all shown as the D/A block in Figure 3 on page 5. This is followed by a second-order active Chebychev fil- ter having a cutoff frequency of 35 kHz. The passband ripple of the analog filters is small enough such that they have virtually no effect on the passband response. The output amplifier buffers the analog filter output. The frequency responses of the A/D and D/A paths are essentially the same. See Figures 6 through 15 for the magnitude and delay responses versus frequency.
4.3 Programmable Features
4.3.1 Active/Inactive Modes
The CSP1027 has active and inactive modes of opera- tion which are selected by the ACTIVE field in the cioc0 register (see Table 7 on page 26). The default value upon reset and powerup is ACTIVE = 0 (i.e., inactive). In the inactive mode, the codec clocks are disabled, data transfers by the codec are disabled, and analog bias currents are shut off. This state is useful in battery-powered applications when prolonged periods of inactivity are expected. It takes approximately 600 ms for the codec to reach full steady-state perfor- mance in going from inactive to active. This is primarily due to the charging of the large external capacitors, C REF and CREG . However, the codec is functionally useful after 100 ms.
4.3.2 Input Select
When the A/D preamplifier is selected (EIGS = 0), the INSEL field of cioc0 (see Table 7 on page 26) switches the preamp input between the MICIN and AUXIN inputs. When external gain select is used (EIGS = 1), the INSEL field has no effect.
4.3.3 A/D Input Ranges
When the preamplifier is used (EIGS = 0), the IRSEL field of the cioc0 register (see Table 7 on page 26) selects the 500 mVp range when IRSEL = 0 and the 160 mVp range when IRSEL = 1. IRSEL has no effect when the external gain select mode is used (EIGS = 1). When EIGS = 1, the inverting amplifier of Figure 5 on page 7 replaces the preamplifier. The input range in this mode is the following: V FULL-SCALE =
4.3.4 Output Mute Function
The D/A converter output can be selectively muted with the MUTE field in the cioc0 register (see Table 7 on page 26). The default value upon reset is muted (MUTE = 0). The mute function is implemented (Figure 3 on page 5) internally by a MUX following the D/A input. Placing the mute function here causes the signal at the analog output to gradually decay/rise over approximately 1 ms upon muting/unmuting. This effect is due to the impulse response and group delay of the digital filters. This implementation will reduce any potentially undesirable transient effects such as pops, when the D/A is muted. Rin
CSP1027 Voice Band Codec for Data Sheet Cellular Handset and Modem Applications December 1999 Lucent Technologies Inc.14
4.3.5 Output Gains
The D/A converter output can be programmed in 3 dB increments with the OGSEL field in the cioc0 register (see Table 7 on page 26) to serve as a volume control.
4.3.6 Loopback Mode
The codec has a programmable loopback mode, repre- sented by the TEST field in the cioc0 register, (see Table 7 on page 26). As shown in Figure 3 on page 5, when TEST = 0, the codec is in its normal mode of operation. When TEST = 1, the loopback mode is acti- vated. In loopback mode, the 1-bit PDM output signal from the analog modulator is received by the analog demodulator. At the same time, the 1-bit signal output from the digital modulator is received by the sinc-cubic filter in the A/D. This results in the analog input being looped back to the analog output through the A/D and D/A, and the digital input being looped back to the digi- tal output through the digital filters. The loopback mode can be useful for evaluating analog performance of the codec in the target system without going through the digital filters. This mode is also useful for evaluating the response of the digital filters or in evaluating the read/ write functions of the codec and cdx registers without having to provide an analog input to the A/D.
4.3.7 High-Pass Filter Select
The high-pass filter in the A/D and D/A can be enabled or disabled with the HPFE field in the cioc3 register (see Table 10 on page 29).
4.3.8 Dither
A dithering scheme is employed in the CSP1027 which decorrelates the periodic quantization noise of the D/A modulator to make it white noise. Δ-Σ converters are popular due to their high tolerance to component mismatch present in integrated circuit fabrication processes. However, Δ-Σ converters may suffer from periodic noise and spurious tone generation (in-band and out-of-band) due to the coarse quantiza- tion and feedback of the Δ-Σ modulator. Although this periodic noise may exist at very low levels (for example, at about –90 dBm), it may be very objectionable to the listener while having virtually no impact on the resolu- tion of the converter. The CSP1027 D/A uses a robust dithering scheme which eliminates any potential prob- lems due to this phenomenon. The DITHER field in the cioc3 register (see Table 10 on page 29) disables this feature. The default value upon reset is DITHER = 0 (i.e., enabled). When the DITHER is disabled, the signal-to-noise ratio will gener- ally be about 2 dB higher. The DITHER should be enabled if the CSP1027 is used in an audio application, i.e., where this device interfaces to an audio trans- ducer. If the CSP1027 is used in an application other than audio, such as data communications, the DITHER can be disabled if so desired.
4.4 Power-On Reset
4.4.1 Internal
The CSP1027 has a power-on reset circuit that is ORed internally with the inversion of the reset pin, RSTB, to form the internal reset (see Figure 16 on page 15). The power-on reset circuit’s inverted output is also an output pin, PORB. The PORB can be used to provide power-on reset to the system. The power-on reset circuit is composed of two pulse- generating elements, its output being the OR of the two. One element is entirely internal and generates a power-on pulse of 1.5 ms to 7.0 ms. The second ele- ment is composed of an input pin, PORCAP , a resistor connected between PORCAP and V DD , and an invert- ing input buffer. The user selects the capacitor value to connect between PORCAP and ground that will gener- ate a power-on pulse of desired width. The pin PORCAP allows the user to lengthen the power-on reset pulse to a width greater than the internal power- on element provides. The nominal value of the resistor is 155 kΩ , and the threshold of the inverting input buffer is 0.6 x V DD . The formula that relates the power-on reset pulse delay to the PORCAP capacitor is as fol- lows: T D = –R x C x loge (1 – 0.6) TD = 0.9163 x R x C Hence, to generate a 14.2 ms power-on reset pulse, one would use a 0.1 µF capacitor connected between PORCAP and V SS . An internal power-on pulse can be initiated after power- on by writing a one to the TSTPOR field in the cioc3 register (see Table 10 on page 29). This causes the internal power-on pulse of 1.5 ms to 7.0 ms to be gen- erated. The pulse resets the device and appears on the PORB output pin.
Figure 16. Power-On Reset Diagram Figure 17. Clock Generation
4.5 Clock Generation
programmable dividers with a range from 1 to 31. five programmable coefficients shown connected to it. but the period of CKS will be constant. examples of how to program the clocks.
4.5.1 Crystal Oscillator
The CSP1027 has a selectable on-chip clock oscillator. and selects the input buffer connected to the CLK pin. tion on optimizing the oscillator performance.
4.5.2 Clock Divider 2
Figure 18. Clock Divider 2 can be used to clock external logic or processors.
4.5.3 Clock Divider 0
Figure 19. Clock Divider 0 set to divide by 1, one can only retard the clocks.
4.5.4 Clock Divider 1
Figure 20. Clock Divider 1 a clock divider that generates the CKO1 output clock.
4.5.5 Sampling Clocks Generation
Figure 21. Sampling Clocks Generation providing a programmable, fractional divider, F1. such that the average period is the desired fraction.
dividers are summarized in Table 2. Table 2. Programmable Divider Summary Table 3. CDIV3 Value for Each M Table 4. CDIFS Value for Each S
Table 5. CDIF0, CDIF1, CDIF2 Values for Each N
CSP1027 Voice Band Codec for Data Sheet Cellular Handset and Modem Applications December 1999 Lucent Technologies Inc.20
4.6 Serial I/O Configurations
4.6.1 Codec Data Transfer
When the codec is active, ACTIVE = 1 (see Table 7 on page 26), it loads data into the cdx(A/D) and empties data from the cdx(D/A) register (see Figure 3 on page 5) at the sampling frequency, fS (which is 8 kHz based on a 1 MHz oversampling frequency). The codec data transfers occur independent of the serial input/output data transfers described below. The data is double buffered, allowing the codec to transfer data to or from the cdx while the serial I/O is shifting data into or out of the shift registers (isr and osr). When the codec is set to inactive, ACTIVE = 0, there are no codec data trans- fers to the cdx(A/D) or from the cdx(D/A). The internal STATUS flag is set high when cdx(A/D) is loaded and cdx(D/A) is emptied. Loading data from the cdx(A/D) into the output shift register (osr) or loading data from the input shift register (isr) into the cdx(D/A) due to a serial I/O transaction, clears the internal STA- TUS flag. The internal STATUS flag can be observed on the data output (DO) pin in the passive mode and causes data transfers in the active and multiprocessor modes.
4.6.2 Codec Control Writes
The four control registers are written through the serial port. The serial address (SADD) selects between con- trol and data transfers. Bits 15 and 14 of the control word being transferred select which control register, cioc0, cioc1, cioc2, or cioc3, is written (i.e., cioc0: Bit[15:14] = 00, cioc1: Bit[15:14] = 01, etc.).
4.6.3 Serial I/O Port Overview
The CSP1027 serial I/O unit is an asynchronous, full- duplex, double-buffered channel operating at up to
20 Mbits/s that easily interfaces with other Lucent fixed-
point DSPs (i.e., DSP16A and DSP1610/1616/1617/ 1618) in a single or multiple DSP environment. Com- mercially available codecs and time-division multi- plexed (TDM) channels can be interfaced to the CSP1027 device with little, if any, external logic. The serial interface is a subset of the standard Lucent DSP serial I/O and is comprised of eight pins: ■ A single passive serial input/output clock (IOCK). ■ A combined input load, output load, and synchroni- zation (SYNC). ■ Serial data input (DI). ■ Serial data output (DO). ■ Serial address (SADD). ■ Three serial mode select pins (SMODE[2:0]). The CSP1027's serial I/O is different from the standard Lucent serial I/O in a number of ways: ■ The SMODE[1:0] pins configure the serial I/O port into one of four possible ways: a passive SIO config- uration, an active SIO configuration, and two multi- processor SIO configurations. ■ A fixed most significant bit (MSB) first data format. ■ A fixed 16-bit data mode. ■ The serial address (SADD) is an input during the passive and active SIO configurations to select between data and control SIO transfers. It is intended to be connected to the DSP’s SADD pin, which is an output during passive and active SIO. Note that the DSP's SADD output is inverted and is composed of two 8-bit fields that are shifted out least significant bit (LSB) first. ■ The multiprocessor mode time slots and serial addresses are restricted to two sets, one of which is selected based on the state of SMODE0. ■ The SMODE2 pin should always be tied low for the serial I/O port to operate as described. ■ The frequency of the serial I/O interface clock input IOCK (F IOCK ) must be greater than the frequency of the internal oversampling clock (FIOCK ).
Figure 22. Passive Communication and Connections
4.6.4 Passive I/O Configuration (SMODE[1:0] = 00)
trol registers, cioc[0:3], or the data register, cdx(D/A).
Figure 23. Active Communication and Connections
4.6.5 Active I/O Configuration (SMODE[1:0] = 01)
supplies only a serial input/output clock (IOCK). input and the input/output load (SYNC) is an output. Figure 23. The DSP supplies the serial clock (IOCK) interface for a single DSP and a CSP1027.
Figure 24. Multiprocessor Communication and Connections
4.6.6 Multiprocessor Configuration (SMODE[1:0] = 1X)
DSPs form a clock line referred to as CK. nization line referred to as SYN. processor bus during time slot 0 also drives the SYN line. control words with the CSP1027.
CSP1027 Voice Band Codec for Data Sheet Cellular Handset and Modem Applications December 1999 Lucent Technologies Inc.24 During each time slot (see Figure 26 on page 25), the device that is assigned to that time slot drives the ADD and DATA lines. If the assigned device's output buffer is full, it loads its output shift register and shifts the 16 bits of data, MSB first, out DO onto the DATA line. The 8-bit transmit address is inverted and shifted out, LSB first, onto the ADD line at the same time as the first 8 bits of data. The inverted 8-bit protocol information is then shifted out, LSB first, on the ADD line at the same time as the last 8 bits of data. The CSP1027’s transmit address, AT[7:0], is determined by the SMODE0 pin (see Table 6 on page 25). The DSP’s transmit address is determined by the srta register. The CSP1027’s pro- tocol information is always all zeros, which is inverted to appear as all ones on the ADD line. The DSP’s pro- tocol information is determined by the saddx register. If during a time slot the assigned device's output buffer is empty, then zeros are shifted out on the DATA line and zeros are shifted and inverted to become ones on the ADD line. During each time slot, each device receives the data on the DATA line and inverts and receives the address and protocol information on the ADD line. Each device compares the transmitted 8-bit address with its receive address. If the transmitted address and the device's receive address have at least one occurrence of a one in the same bit location, the address matches and the device transfers the data from the input shift register to its input buffer. If the transmitted address and the receive address do not match, the data remains in the input shift register and is overwritten during the next time slot. The DSP's receive address is determined by its srta register. Each CSP1027 has two receive addresses, one for data and another for control, the values of these two addresses are determined by the SMODE0 pin (see Table 7 on page 26). When the data receive address matches, the input shift register is loaded into the cdx(D/A) register. When the control receive address matches, the input shift register is loaded into one of the four cioc registers, based upon the two most significant bits of the 16-bit word. The CSP1027 ignores the protocol information. Multiprocessor communication with a CSP1027 is intended to follow the sequence: ■ The DSP writes the control registers, cioc[0:3], in the CSP1027 to configure the clock dividers and codec. The codec is also activated. ■ The CSP1027’s A/D fills the output buffer, cdx(A/D), and empties the input buffer, cdx(D/A), at the same time. This causes the A/D data to be transmitted by the CSP1027 to the DSP during the next CSP1027 time slot. The DSP’s receive address is set to match the CSP1027’s transmit address. ■ When the DSP receives A/D data from the CSP1027, it responds by sending D/A data to the CSP1027 dur- ing the DSP’s next time slot. The DSP’s transmit address is set to match the CSP1027’s data receive address. The new data is loaded into the CSP1027’s cdx(D/A) register to be used as the next D/A sample. ■ If the DSP wants to send a control word to the CSP1027 to change the configuration or inactivate the codec, this can be done by setting the DSP's transmit address to match the codec's control receive address. Note that since the CSP1027 sends all zeros for the protocol information, this will have to be used to identify the A/D data from the CSP1027. If two CSP1027s are connected to the multiprocessor bus and the DSP's receive address is set to match both CSP1027's trans- mit addresses, the DSP will have to identify which A/D data came from which CSP1027 by the order in which the data arrives, since both CSP1027s will be sending the same protocol information.
Figure 25. Multiprocessor Frame Timing Figure 26. Multiprocessor Time-Slot Timing Table 6. Hardwired CSP1027 Multiprocessor Time Slot and Addresses
5 Register Information
Tables 7 through 10 describe the programmable registers of the CSP1027 device.
5.1 Codec I/O Control 0 (cioc0) Register
Table 7. Codec I/O Control 0 (cioc0) Register Reg 00 Indicates control register 0. Testability mode—analog and digital loopback. ACTIVE 0* Codec set to inactive mode (i.e., powerdown). OGSEL 1111 Output gain adjustment of 0 dB. 1110 Output gain adjustment of –3 dB. 1101 Output gain adjustment of –6 dB. 0001 Output gain adjustment of –42 dB. 0000* Output gain adjustment of –45 dB. MUTE 0* Output signal muted. IRSEL 0* Microphone preamplifier input range: 500 mVp. 1 Microphone preamplifier input range: 160 mVp. INSEL 0* Select microphone input, MICIN. 1 Select auxiliary input, AUXIN. CDIV2 0 0000 Output clock 2, CKO2, disabled. 0 0001 Output clock 2, CKO2 = ICLK ÷ 1. 0 0010 Output clock 2, CKO2 = ICLK ÷ 2. 1 1110 Output clock 2, CKO2 = ICLK ÷ 30. 1 1111 Output clock 2, CKO2 = ICLK ÷ 31.
5 Register Information(continued)
5.2 Codec I/O Control 1 (cioc1) Register
Table 8. Codec I/O Control 1 (cioc1) Register Reg 01 Indicates control register 0. Select retard mode for internal clock, ICLK0, adjustment. 1 Select advance mode for internal clock, ICLK0, adjustment. ADJ 000 0000* Internal clock, ICLK0, not adjusted. 000 0001 Internal clock, ICLK0, adjusted by one ICLK cycle for one ICLK0 cycle. 000 0010 Internal clock, ICLK0, adjusted by one ICLK cycle for two ICLK0 cycles. 111 1110 Internal clock, ICLK0, adjusted by one ICLK cycle for 126 ICLK0 cycles. 111 1111 Internal clock, ICLK0, adjusted by one ICLK cycle for 127 ICLK0 cycles. CDIV0 0 Internal clock, ICLK0 = ICLK ÷ 1. 1* Internal clock, ICLK0 = ICLK ÷ 2. CDIV1 0 0000 Output clock 1, CKO1, disabled. 0 0001 Output clock 1, CKO1 = ICLK0 ÷ 1. 0 0010 Output clock 1, CKO1 = ICLK0 ÷ 2.
5.3 Codec I/O Control 2 (cioc2) Register
Table 9. Codec I/O Control 2 (cioc2) Register Reg 10 Indicates control register 0. CDIFS 0* Sampling rate, CKS = ICLK0 ÷ (CDIV3 x 125). W Sampling rate, CKS = ICLK0 ÷ (125 x M + S x N). See Section 4.5 on page 16. CDIF0 00 0000* Sampling rate, CKS = ICLK0 ÷ (CDIV3 x 125). WW WWWW Sampling rate, CKS = ICLK0 ÷ (125 x M + S x N). See Section 4.5 on page 16. CDIV3 00 0001 Oversampling clock, CKOS = ICLK0 ÷ 1. 00 0010 Oversampling clock, CKOS = ICLK0 ÷ 2. 11 1111 Oversampling clock, CKOS = ICLK0 ÷ 63. 00 0000* Oversampling clock, CKOS = ICLK0 ÷ 64. WW WWWW Sampling rate, CKS = ICLK0 ÷ (125 x M + S x N). See Section 4.5 on page 16.
5.4 Codec I/O Control 3 (cioc3) Register
Table 10. Codec I/O Control 3 (cioc3) Register Reg 11 Indicates control register 0. Test on-chip power-on reset pulse generator. HPFE 0* Enable high-pass filter in A/D and D/A. 1 Disable high-pass filter in A/D and D/A. DITHER 0* Enable dither on D/A converter. 1 Disable dither on D/A converter. CDIF2 0 0000* Sampling rate, CKS = ICLK0 ÷ (CDIV3 x 125). W WWWW Sampling rate, CKS = ICLK0 ÷ (125 x M + S x N). See Section 4.5 on page 16. CDIF1 00 0000* Sampling rate, CKS = ICLK0 ÷ (CDIV3 x 125). WW WWWW Sampling rate, CKS = ICLK0 ÷ (125 x M + S x N). See Section 4.5 on page 16.
6 Signal Descriptions
Figure 27. CSP1027 Pinout by Interface comprise them are described below.
6.1 Clock Interface
oscillator, and clock outputs for the codec.
6.1.1 CLK
tied low or high to minimize input buffer power.
6.1.2 XLO
and the CMOS clock applied to CLK.
6.1.3 XHI
and the CMOS clock applied to CLK.
6.1.4 XOSCEN
crystal oscillator is selected for XLO and XHI pins. pin and the crystal oscillator is powered down. tied to VSS , or driven by valid logic levels.
Lucent Technologies Inc. 31 Data Sheet CSP1027 Voice Band Codec for December 1999 Cellular Handset and Modem Applications
6 Signal Descriptions(continued)
6.1.5 CKO1
Clock Out 1: ICLK ÷ CDIV1 (see Table 8 on page 27). General-purpose output clock that can be used by a baseband codec, such as the CSP1084.
6.1.6 CKO2
Clock Out 2: CLK ÷ CDIV2 (see Table 7 on page 26). General-purpose output clock that can be used by a processor, such as the DSP1616.
6.2 Reset Interface
The reset interface consists of the reset input, power- on reset input, and power-on reset output for the codec.
6.2.1 RSTB
Reset: A high-to-low transition causes entry into the reset state. The cioc[0:3] register bits are set to their default states.
6.2.2 PORB
Power-On Reset: A high-to-low transition indicates entry into the power-on reset state.
6.2.3 PORCAP
Power-On Reset Capacitor: A capacitor is to be attached to this pin for the power-on reset circuit. POR- CAP has an internal resistor (nominal value of 155 kΩ ) connected to digital power, V DD .
6.3 Serial I/O Interface
The serial I/O interface consists of the serial clock input, synchronizing signal, data input, data output, serial address, and serial modes for the codec.
6.3.1 SMODE 0
Serial Mode 0: Configures the CSP1027 serial I/O interface. When in active/passive mode (SMODE1 low), SYNC is an output when SMODE0 is high, and SYNC is an input when SMODE0 is low. In multiprocessor mode (SMODE1 high), SMODE0 selects between two possible time slots, and between two possible transmit and receive address combinations. See Table 6 on page 25 in the architectural information for the addresses.
6.3.2 SMODE1
Serial Mode 1: Configures the CSP1027 serial I/O interface to multiprocessor mode when active-high; oth- erwise, active/passive mode is selected when low.
6.3.3 SMODE2
Serial Mode 2: Must be tied low to configure the CSP1027 serial I/O interface as described. 6.3.4 DI Serial Data Input: Serial data input is latched on rising edge of IOCK, MSB first. DI and DO should be con- nected together when in multiprocessor mode. 6.3.5 DO Serial Data Output: Serial data output from the output shift register (osr), MSB first, when the data register, cdx(A/D), is selected or codec status flag when the control registers, cioc[0:3], are selected. When an out- put, DO changes on the rising edges of IOCK. DI and DO should be connected together when in multiproces- sor mode, SMODE1 high.
6.3.6 IOCK
Serial Input/Output Clock: Input clock for serial PCM input and output data. Note:The frequency of the serial I/O interface clock input IOCK (F IOCK ) must be greater than the fre- quency of the internal oversampling clock CKOS (FCKOS ).
6.3.7 SYNC
Serial Input/Output Load Strobe and Sync: When not in multiprocessor mode, the falling edge of SYNC indicates the beginning of a serial input and a serial output word. The falling edge of SYNC loads the output shift register (osr) from the codec data register (cdx(A/D)). Sixteen IOCK clock cycles after the falling edge of SYNC, the codec data (cdx(D/A)) or control register (cioc) is loaded from the input shift register (isr). SYNC is an input when the SMODE0 pin is low and an output when the SMODE0 pin is high. In multiprocessor mode, SYNC is the multiprocessor synchronization input signal. A falling edge of SYNC indicates the first word of a TDM I/O stream and causes the resynchronization of the internal input and output load generators.
CSP1027 Voice Band Codec for Data Sheet Cellular Handset and Modem Applications December 1999 Lucent Technologies Inc.32
6.3.8 SADD
Serial Address: When not in multiprocessor mode, SADD is an input that selects between the codec data registers, cdx(D/A) and cdx(A/D), and codec control registers, cioc[0:3]. SADD is inverted and latched on the rising edge of IOCK and compared against a zero for data and a one for control, to determine if input data on DI is loaded from the input shift register (isr) into cdx(D/A) or one of cioc[0:3]. Once SADD indicates a control word, the internal codec status flag appears on DO, replacing cdx(A/D). While not performing a serial transmission, SADD low causes the internal codec sta- tus flag to be output on DO. In multiprocessor mode, SADD is an output when the tdms time slot dictates a serial output transmission; oth- erwise, it is an input. While an output, SADD is the inverted 8-bit serial transmit address output, LSB first. SADD changes on the rising edges of IOCK. While an input, SADD is inverted and latched on the rising edge of IOCK and compared against the cdx(D/A) and cioc[0:3] serial receive addresses to determine if input data on DI is loaded from the input shift register (isr) into cdx(D/A) or cioc.
6.4 External Gain Control Interface
The external gain control interface consists of one input.
6.4.1 EIGS
External Input Gain Select: A logic low or no connect selects the microphone preamplifier. A logic high selects the single op amp input mode where external resistors set the A/D input range. Note that EIGS is a digital pin whose input levels are relative to digital power and ground (V DD and VSS ).
6.5 Digital Power and Ground
Digital Power Supply: 3.0 V to 5.0 V supply. VSS Digital Ground: 0 V .
6.6 Analog Interface
The analog interface consists of the two inputs, two out- puts, a regulated output voltage reference, and a capac- itor connection for the codec.
6.6.1 MICIN
Analog Input from Microphone: Low-level analog sig- nal from electret condenser microphone selected by INSEL bit in codec control register, cioc0 (see Table 7 on page 26).
6.6.2 AUXIN
Analog Input from Auxiliary: When used in preampli- fier mode (EIGS = 0), AUXIN is a low-level analog signal selected by INSEL bit in codec control register, cioc0 (see Table 7 on page 26). The characteristics of AUXIN are identical to MICIN. When used in external gain select mode (EIGS = 1), AUXIN is the output of the inverting amplifier. The INSEL bit has no effect in this mode.
6.6.3 AOUTP
Noninverting Analog Output: In conjunction with AOUTN, this output can drive a 2 kΩ load in differential mode or a 1 kΩ load ac-coupled to analog ground.
6.6.4 AOUTN
Inverting Analog Output: In conjunction with AOUTP , this output can drive a 2 kΩ load in differential mode or a 1 kΩ load ac-coupled to ground. 6.6.5 V REG Regulated Output Voltage: For electret condenser microphone. Vout = 3 V ± 10%, Iout = 250 µA max. A 1 µF and 0.1 µF ceramic type X7R capacitor to ground must be provided at this pin (see Figure 28 on page 34).
6.6.6 REFC
External Capacitor Connection: Internal voltage regu- lator bypassing. A 0.22 µF ceramic type X7R capacitor to ground must be provided at this pin.
6.7 Analog Power and Ground
Analog Power Supply: 5.0 V supply. VSSA Analog Ground: 0 V .
Lucent Technologies Inc. Data Sheet CSP1027 Voice Band Codec for December 1999 Cellular Handset and Modem Applications
7 Application Information
This section begins with application information for the analog section, followed by power distribution, crystal oscillator, and codec clock generation programming examples.
7.1 Analog Information
The A/D input block is covered first, followed by the D/A, and the microphone voltage regulator.
7.1.1 A/D in the Preamplifier Mode
Figure 28 on page 34 shows a typical telephone hand- set application. The codec is shown with the preamp mode (EIGS = V SS ) selected and connected to a micro- phone. The analog-to-digital conversion path begins with an on-chip preamplifier front end having two single-ended inputs. The preamp inputs are MICIN and AUXIN. Selection of MICIN or AUXIN is made via the INSEL field in the cioc0 register (see Table 8 on page 27) and can be dynamically changed, as desired. The electrical specifications for both inputs are the same. An off-chip ac-coupling capacitor, Cin, is required before each input. However, if either input is unused, it may be left unconnected (floating). The input resis- tance (Rin) to either MICIN or AUXIN is approximately 40 kΩ . The recommended value of Cin is 0.15 µF . This creates a high-pass filter pole at approximately 26 Hz. A larger capacitor value may be used if desired, in order to allow lower frequencies to pass to the A/D con- verter, but smaller capacitor values are not recom- mended.
7.1.2 A/D in the External Input Gain Select Mode
The external input gain select (EIGS = V DD ) is used when the input range is set by the user (see Section 4.3 on page 13). The A/D input circuitry of Figure 28 on page 34 is modified as shown in Figure 5 on page 7. When EIGS = V DD , the following notes apply. 1. The recommended range of values for the feedback resistor and capacitor are the following: 10 kΩ ≤ Rfb ≤ 45 kΩ and 150 pF ≤ Cfb ≤ 680 pF . 2. The external resistor ratio accuracy directly impacts the absolute accuracy of the A/D path. A 1% ratio error adds 86 mdB of absolute gain error. 3. The A/D input sampling switches have an effective bandwidth on the order of 15 MHz. The amplifier unity gain frequency is on the order of 3 MHz. High- frequency noise in the 1 MHz to 50 MHz range that couples to the AUXIN pin will be somewhat attenu- ated by the amplifier output impedance, but a signifi- cant portion will be sampled by the A/D and aliased down to the baseband. Special care in circuit board layout is required to keep noise sources from cou- pling into the AUXIN or MICIN pins so that the noise and distortion performance shown in Table 16 on page 52 can be achieved. The codec is not as sensitive to wideband noise when the preamplifier is used (EIGS = V SS ) because the A/D inputs are driven from an on-chip low-pass filter. 4. The external gain mode input circuitry of Figure 5 on page 7 is an integrator with a great deal of loss. The frequency response of Table 16 on page 52 assumes that the Rfb × Cfb corner frequency is 25 kHz so the 3 kHz droop is less than 65 dBm. Sim- ilarly, the Cin × Rin corner frequency is set to 7 Hz. These RC combinations create a bandpass anti- aliasing filter with corner frequencies given by: When selecting component values, verify that the A/D frequency response will still meet the application requirements.
7.1.3 D/A Analog Output
The CSP1027 D/A has two analog outputs, AOUTP and AOUTN, capable of operating as two single-ended drivers, or a single fully differential driver. The output impedance of each is no more than 6 Ω (12 Ω if config- ured as fully differential) over the dc to 4 kHz frequency range. The maximum open-circuit output levels are 2.1 Vp (4.2 Vp-p) if fully differential, and one-half of these lev- els if single-ended. These levels correspond to a full- scale 16-bit two's complement PCM input into the D/A converter, with the output gain setting (OGSEL) at 0 dB. For any given PCM input, the output levels will be reduced by a voltage division of the D/A output and the load impedance: The driver linearity is only guaranteed for the single- ended output load resistance (R L) of at least 1000 Ω and the differential output load resistance (RL) of at least 2000 Ω . Rfb fLO 1 V OUT V O R L
7 Application Information(continued)
30 Hz in order to not interfere with the voice band frequency response. coupling capacitors are required. Analog (VSSA ) and digital (VSS ) ground pins are tied together to prevent substrate currents from ground bounce. Capacitors CA2, CD2 , CREF, CREG 1, and CREG 2 should be type X7R ceramic. Capacitors CA1 and CD1 should be tantalum or low ESR aluminum. All capacitors should be located as close to the chip pins as possible. Keep analog and digital grounds separate, and then join at the VSSA pin. Keep the regulator as close to the chip as possible. C D2 go from the 3.3 V regulator to ground, and Ra goes to the 5.0 V regulator. Figure 28. Analog External Configurations in Preamplifier Mode (EIGS = 0)
Figure 29. Analog Output Configurations
CSP1027 Voice Band Codec for Data Sheet Cellular Handset and Modem Applications December 1999 Lucent Technologies Inc.36
7.1.4 Microphone Regulator
VREG is a 3.0 V regulated supply that provides up to 250 µA to an external microphone or other device (see Figure 28 on page 34). The regulator uses the external capacitors C REG 1 and CREG 2 to band limit its noise and for frequency compensation. The CREG 1 off-chip capacitor (1 µF) is required in order to meet the noise specification of 100 µV on V REG . CREG 2 (0.1 µF) should be placed in parallel with CREG 1 to improve high-frequency noise filtering. The minimum value of the C REG 1 and CREG 2 combination is 0.1 µF for VREG to be stable. If VREG is not used, this pin should be either connected through a 0.1 µF capacitor to analog ground (V SSA ) or tied directly to ground. Connecting VREG to ground will produce a dc current of 250 µA to 400 µA out the VREG pin, but will not change the total supply current. Do not leave the VREG pin unconnected because it will oscillate.
7.2 Power Supply Configuration
Figure 28 on page 34 illustrates the recommended configuration for the analog and digital power and grounds. An external supply feeds an off-chip voltage regulator. Capacitor C D1 (10 µF) and CD2 (0.1 µF) are used for decoupling the noise on the VDD digital power bus. Capacitors CA1 (10 µF) and CA2 (0.1 µF) are for de- coupling the noise on the analog power bus (VDDA ). The Ra resistor (3 Ω ) decouples the analog and digital power buses when a common 5.0 V power supply is used. The analog and digital circuits share the same substrate since this codec is a monolithic device. In the technology used to fabricate the device, the substrate is connected to ground. To avoid large substrate cur- rents caused by digital ground-bounce, it is recom- mended that the analog and digital grounds be tied together at the package, as shown in Figure 28 on page 34. It is recommended that the analog and digital ground planes also meet at this point. In a typical appli- cation where the CSP1027 is interfaced to a DSP , it is advisable to place the DSP as close to the codec as possible, with the DSP's digital ground plane extending to the points where the SIO lines meet the CSP1027.
7.2.1 REFC Capacitor
An off-chip capacitor, C REF (0.22 µF), is required on pin REFC in order to meet the noise requirements for the internal signal paths.
7.2.2 Capacitor Proximity to Pins
In all cases, the external capacitors should be placed as closely as possible to the CSP1027 pins, in order to meet the noise specifications.
7.3 The Need for Fully Synchronous
7.3.1 Introduction to Sampled Data Systems
The analog circuits in the A/D and D/A converters are sampled data circuits. This means that there are switches that close to sample the signal and then open to hold the signal. An example of this kind of discrete time analog circuit is the well-known switched capacitor technique used to implement A/D and D/A converter circuits as well as filters. A fundamental property of any sampled data system is that any noise or signal that is in the signal path when the sampling switches open is sampled. The sampling process modulates the noise and signal about multi- ples of the sample clock rate. For a sample rate of f S and a noise tone at a frequency of fn, this modulation process produces new tones at (k x fS) ± fn, where k = 1, 2, 3 . . . . For noise near a multiple of fS, the difference term can modulate all the way down to baseband and be heard as a tone. A typical source of noise is that generated by the nor- mal operation of the digital circuits. The digital circuits tend to have fast edge transitions (large dv/dt and di/dt). The dv/dt changes couple into the analog signal path through parasitic capacitance on-chip and in the circuit board. The di/dt changes cause voltages to be generated across parasitic inductance and cause ground-bounce on-chip. The ground-bounce can turn on intrinsic parasitic diodes to the substrate of the CSP1027, and the subsequent substrate currents can couple the noise into the analog circuits. The di/dt tran- sients are also inductively coupled into the off-chip analog routing and thus added to the analog signals. Layout techniques help reduce the dv/dt and di/dt cou- pling, but it is very difficult to eliminate it. To gauge the magnitude of the problem, consider the numbers from the CSP1027. The digital logic swing is ground to V DD , which can be as large as 5.5 V. The full-scale preamplifier input level (when IRSEL = 1) is 160 mVp, and the A/D path has a noise floor that is guaranteed to be 70 dB below full scale. For the digital noise to raise the noise floor by less than 3 dB, the
Lucent Technologies Inc. Data Sheet CSP1027 Voice Band Codec for December 1999 Cellular Handset and Modem Applications noise must be less than 36 µVrms referred to the preamplifier input. As a worst-case analysis, assume that all the digital noise is in the baseband (noise source of 2.5 Vrms for a 5.0 V digital signal). The atten- uation (isolation) between the digital signal and the preamplifier for this case must be isolation Usually, only a small portion of a particular digital signal ac-couples into the signal path, but this is tempered by having many digital signals. It is the sum of these noise sources that must be held to less than 36 µVrms. In audio applications, the needed isolation is actually greater than calculated above because the human ear can detect tones that are 10 dB below the noise floor.
7.3.2 Typical Ways Digital Noise Couples into
- Digital signals have overshoot or undershoot because of circuit board impedance mismatches. These reflections can turn on internal I/O protection diodes. The diodes then inject the noise current into the substrate as well as the chip power rails, and the noise is distributed throughout the chip. 2. Fine-line CMOS (like that used to fabricate the CSP1027) generates hot electron currents when the logic gates change state. This current is injected into the substrate and adds to the supply current. The substrate current can couple directly into the analog circuits, and the supply current transients can couple through common supply impedance and by inductive coupling. 3. Coupling off-chip, such as the package bond wires and package pins, and coupling into the analog sig- nals on the circuit board. 4. The classic coupling method: common power and ground impedance.
7.3.3 The Problem with an Asynchronous Codec
When the I/O and sample clocks are not derived from the same time base, their edges will drift with time. Even if the I/O and sample time bases use master oscillators that are stated to be the same frequency (or one being a multiple of the other), they will differ by some amount from their intended values. This differ- ence in frequency will cause the digital circuit clock edges to slide past the analog sample clock edges in a periodic way, causing the sampled digital noise to also vary in the same periodic way (noise tones in the base- band).
7.3.4 The Advantage of Fully Synchronous
When all the clocks that are used in or connected to the codec are generated from the same master time base, the sampling switches sample in the quiet time before the digital circuits change state, or at least sample the same portion of the ground bounce transient. The por- tion of the noise that does not change from one sample to the next will alias to the signal path as a dc offset. The portion that is signal dependent (like a data line coupling into the analog signal path) can show up as a tone even though its transitions occur synchronously with the sample clock unless care is taken to ensure that the analog sampling switches only open during a quiet time (usually before the digital circuits change state). 2.5 V
7.4 Crystal Oscillator
If the option for using the external crystal is chosen, the following electrical characteristics and requirements apply.
7.4.1 External Components
half the absolute value of the negative resistance shown in Figures 31 or 32 on page 39 for the crystal frequency. The frequency of the internal clock will be equal to the crystal frequency. Figure 30. Fundamental Crystal Configuration
7.4.2 Power Dissipation
Figure 31. Negative Resistance of Crystal Oscillator Circuit, VDD = 4.75 V Figure 32. Negative Resistance of Crystal Oscillator Circuit, VDD = 3.0 V
Figure 33. Typical Supply Current of Crystal Oscillator Circuit, VDD = 5.0 V, 25 °C Figure 34. Typical Supply Current of Crystal Oscillator Circuit, VDD = 3.3 V, 25 °C
7.4.3 Printed-Circuit Board Layout Considerations
- Keep crystal and external capacitors as close to XLO and XHI pins as possible to minimize board stray capaci-
- Keep high-frequency digital signals such as CKO1 and CKO2 away from XLO and XHI traces to avoid coupling
7.4.4 LC Network Design for Third Overtone Crystal Circuits
that will accomplish this; one of these is described below. Figure 35 shows the basic setup for third overtone operation. Figure 35. Third Overtone Crystal Configuration should be chosen to be large compared to C1. For example, suppose it is desired to operate with a 40 MHz, third overtone, crystal.
CSP1027 Voice Band Codec for Data Sheet Cellular Handset and Modem Applications December 1999 Lucent Technologies Inc.42 Arbitrarily set trap resonance to geometric mean of f1 and f3. Since f1 = f3/3, the geometric mean would be: At the third overtone frequency, f3, it is desirable to have the net impedance of the trap circuit (XT) equal to the impedance of C2 (XC2 ), i.e., Selecting C3 so that XC3 << XL1 yields, For a capacitor, where ω = 2πf. For an inductor, Solving for C1, and realizing that L1C 1 = 3/ω 3 yields, Hence, for C2 = 10 pF , C1 = 15 pF . Since the impedance of the trap circuit in this example would be equal to the impedance of a 10 pF capacitor, the negative resistance and supply current curves for C1 = C2 = 10 pF at 40 MHz would apply to this example. Finally, solving for the inductor value, L1, For the above example, L1 would be 3.2 µH. fT f3 X T X C2 X C1 ||X C3 X L1+()== X T X C2 X C1 ||X L1== X C j– X L jω L= C 1 3 2---C 2= L1 1 4π2f2 TC 2
7.4.5 Frequency Accuracy Considerations
dor should be consulted prior to specifying a crystal for a given application. quency of the oscillator. Figure 36 illustrates some of the sources of this variation. C EXT = External load capacitor (one each required for XLO and XHI). C D = Parasitic capacitance of the CSP1027 itself. C B = Parasitic capacitance of the printed-wiring board. C 0 = Parasitic capacitance of crystal (not part of CL, but still a source of frequency variation). Figure 36. Components of Load Capacitance for Crystal Oscillator external capacitors or the presence of strays, then the frequency will also deviate.
CSP1027 Voice Band Codec for Data Sheet Cellular Handset and Modem Applications December 1999 Lucent Technologies Inc.44 This change in frequency as function of load capacitance is known as pullability and is expressed in units of ppm/ pF . For small deviations of a few pF , pullability can be determined by the equation below. pullability (ppm/pF) = where C 0 = parasitic capacitance of crystal. C 1 = motional capacitance of crystal (usually around 1 fF—25 fF , value can be obtained from crystal vendor). C L = total load capacitance seen by crystal. Note that for a given crystal, the pullability can be reduced, and hence, the frequency stability improved, by making C L as large as possible while still maintaining sufficient negative resistance to ensure start-up per the curves shown in Figures 31 and 32 on page 39. Since it is not possible to know the exact values of the parasitic capacitance in a crystal-based oscillator system, the external capacitors are usually selected empirically to null out the frequency offset on a typical prototype board. Thus, if a crystal is specified to operate with a load capacitance of 10 pF , the external capacitors would have to be made slightly less than 20 pF each in order to account for strays. Suppose, for instance, that a crystal for which C L = 10 pF is specified is plugged into the system and it is determined empirically that the best frequency accuracy occurs with CEXT = 18 pF . This would mean that the equivalent board and device strays from each lead to ground would be 2 pF . As an example, suppose it is desired to design a 26 MHz, 3.3 V system with ±100 ppm frequency accuracy. The parameters for a typical high-accuracy, custom, 26 MHz fundamental mode crystal are as follows: Initial Tolerance 10 ppm Temperature Tolerance 25 ppm Aging Tolerance 6 ppm Series Resistance 20 Ω max Motional Capacitance (C 1) 15 pF max Parasitic Capacitance (C0) 7 pF max In order to ensure oscillator start-up, the negative resistance of the oscillator with load and parasitic capacitance must be at least twice the series resistance of the crystal, or 40 Ω . Interpolating from Figure 32 on page 39, exter- nal capacitors plus strays can be made as large as 30 pF while still achieving 40 Ω of negative resistance. Assume for this example that external capacitors are chosen so that the total load capacitance including strays is 30 pF per lead, or 15 pF total. Thus, a load capacitance, C L = 15 pF would be specified to the crystal manufacturer. From the above equation, the pullability would be calculated as follows: pullability = = = 15.5 ppm/pF If 2% external capacitors are used, the frequency deviation due to this variation is equal to (0.02)(15 pF)(15.5 ppm/pF) = 4.7 ppm. Note:To simplify analysis, CEXT is considered to be 30 pF . In practice, it would be slightly less than this value to account for strays. Also, temperature and aging tolerance on the capacitors have been neglected. Typical capacitance variation of oscillator circuit in the CSP1027 itself across process, temperature, and supply voltage is ±1 pF . Thus, the expected frequency variation due to the CSP1027 is as follows: (1 pF)(15.5 ppm/pF) = 15.5 ppm. Approximate variation in parasitic capacitance of crystal = ±0.5 pF . Frequency shift due to variation in C 0 = (0.5 pF)(15.5 ppm/pF) = 7.75 ppm. Approximate variation in parasitic capacitance of printed-circuit board = ±1.5 pF . Frequency shift due to variation in board capacitance = (1.5 pF)(15.5 ppm/pF) = 23.25 ppm. C 1() 106() C 1() 106()
Lucent Technologies Inc. Data Sheet CSP1027 Voice Band Codec for December 1999 Cellular Handset and Modem Applications Thus, the contributions to frequency variation add up as follows: Initial Tolerance of Crystal 10.0 ppm Temperature Tolerance of Crystal 25.0 ppm Aging Tolerance of Crystal 6.0 ppm Load Capacitor Variation 4.7 ppm CSP1027 Circuit Variation 15.5 ppm C 0 Variation 7.8 ppm Board Variation 23.3 ppm Total 92.3 ppm This type of detailed analysis should be performed for any crystal-based application where frequency accu- racy is critical.
7.5 Programmable Clock Generation
Refer to Figure 17 on page 15 for the following discus- sion. The programmable clock divider is set by writing the 6-bit CDIV3 field of the cioc2 register (see Table 9 on page 28). The user can select an appropriate integer value which sets the ratio of the CLK input clock to the oversampling rate of the codec. The following examples illustrate this feature.
7.5.1 Application Example 1
■ GSM application. ■ Input clock, CLK, rate: 26 MHz (38.46 ns). ■ Codec PCM rate required: 8 kHz (oversampling rate = 1 MHz). Solution: ■ CLK/CK OS = 26, so set CLK/ICLK0 = 1 and ICLK0/ CK OS to 26. ■ Set CDIV0 = 0 and CDIV3 = 26 (011010).
7.5.2 Application Example 2
■ IS-54 application. ■ Input clock, CLK, rate: 40 MHz (25.0 ns). ■ Codec PCM rate required: 8 kHz (oversampling rate = 1 MHz). Solution: ■ CLK/CK OS = 40, so set CLK/ICLK0 = 1 and ICLK0/ CK OS to 40. ■ Set CDIV0 = 0 and CDIV3 = 40 (101000).
7.5.3 Application Example 3
■ Modem data pump. ■ Codec sampling frequency required = 9.6 kHz (instead of 8 kHz). ■ Need highest possible input clock, CLK, rate (allow- able by the DSP). Solution: ■ Codec oversampling rate = 9.6 kHz * 125 = 1.2 MHz. ■ Assuming a DSP16A or DSP1616 with maximum rate of 40 MHz, CLK = 39.6 MHz = 1.2 MHz x 33, so CLK/ICLK0 = 1 and ICLK0/CK OS = 33. ■ Set CDIV0 = 0 and CDIV3 = 33 (100001). ■ Disable the high-pass filters (HPFE = 1) because the –3 dB corner frequency is now too high (270 Hz x 1.2 = 324 Hz). ■ Low-pass filter –3 dB corner frequency is now 4.08 kHz (= 3.4 kHz x 1.2). (Note that external DSP software can provide additional postfiltering, if desired.)
CSP1027 Voice Band Codec for Data Sheet Cellular Handset and Modem Applications December 1999 Lucent Technologies Inc.46
7.5.4 Enhanced Oversampling Clock Generation
If system constraints make the requirement of integer multiples of 125 x the sampling rate (typically integer multiples of 1.0 MHz) difficult to provide, the CSP1027 can also operate with the ICLK0 internal clock rate at integer multiples of the sampling rate (typically integer multiples of 8 kHz). See Section 4.5 on page 16 for more information. The following two examples illustrate the usage: Application Example 4 ■ Standard codec application. ■ CLK input clock rate: 2.048 MHz. ■ Codec sampling rate, fS: 8 kHz. Solution: ■ CK OS = 125 x 8 kHz = 1.0 MHz, so CLK/CKOS = 2.048 or CLK/CKS = 2.048 x 125 = 256. Values of M and N must be found to satisfy this requirement, as shown below. ■ Set CDIV0 for ÷1 (CDIV0 = 0); hence, fICLK = fCLK. ■ Using the equations from Section 4.5 on page 16, Hence, M = 2, S = 1, and N = 6. (Note that if CDIV0 set for ÷ 2, then M = 1, S = +1, and N = 3, which is not allowed.) ■ Using Tables 2 through 4 on page 18: CDIV3 = 00 0010. CDIFS = 0. CDIF0 = 01 0101. CDIF1 = 10 0110. CDIF2 = 0 0000. Application Example 5 ■ IS-54 application. ■ Codec sampling rate, fS: 8 kHz. ■ CLK needs to be a common multiple of 8 kHz and 48 x 48.6 kHz. ■ Need phase adjustment. Solution: ■ 48 x 48.6 = 2.3328E6 2.3328E6 ÷ 8E3 = 291.6 To get a common multiple, 291.6 must be multiplied by a factor to become an integer: 291.6 x 10 = 2916 (an integer). So, CLK/CK S = 2916 and CLK/ICLK0 = 2 CLK = 2916 x 8E3 = 23.328E6. ■ CLK input clock rate: 23.328 MHz. ■ Set CDIV0 for ÷2 (CDIV0 = 1) to allow advance/ retard for phase adjustment. ■ ICLK0 internal clock rate is 11.664 MHz. ■ Using the equations from Section 4.5 on page 16, Hence, M = 12, S = –1, and N = 42. ■ Using Tables 2 through 4 on page 18: CDIV3 = 00 1100. CDIFS = 1. CDIF0 = 00 0011. CDIF1 = 11 0110. CDIF2 = 0 0000. F ICLK0 FS FICLK0 FS FICLK0 FS
8 Device Characteristics
8.1 Absolute Maximum Ratings
periods can adversely affect device reliability. External leads can be bonded and soldered safely at temperatures of up to 300 °C.
8.2 Handling Precautions
100 pF and 1500 Ω are the most common and are the values used in the Lucent human-body model test circuit. The breakdown voltage for the CSP1027 is greater than 1000 V.
8.3 Recommended Operating Conditions
8.3.1 Package Thermal Considerations
the maximum ambient temperature allowed. Table 11. Recommended Operating Conditions
9 Electrical Characteristics and Requirements
Table 12. Digital Electrical Characteristics and Requirements
9 Electrical Characteristics and Requirements(continued)
Figure 37. Plot of VOH vs. IOH Under Typical Operating Conditions Figure 38. Plot of VOL vs. IOL Under Typical Operating Conditions
9.1 Power Dissipation
selected application. The following electrical characteristics are preliminary and are subject to change. the effective output frequency. Table 13. Power Dissipation
25 MHz crystal,
10 Analog Characteristics and Requirements
■ Sampling frequency = 8 kHz, oversampling clock (CKOS ) = 1.0 MHz, input clock (CLK) = 25 MHz. ■ 0.22 µF capacitors connected to the REFC pin. ■ 0.15 µF coupling capacitors connected to the MICIN and AUXIN pins when EIGS = 0. ■ Rfb = Rin = 24 kΩ , Cfb = 270 pF , and Cin = 1 µF when in the external input gain select mode (EIGS = 1). ■ 2 kΩ differential output load connected between AOUTP and AOUTN pins. ■ 1 µF and 0.1 µF bypass capacitors connected between the VREG and VSSA . put of the A/D or input to the D/A. ■ All noise and distortion measurements are flat weighted and integrated over the 300 Hz to 4 kHz frequency band.
10.1 Analog Input and Microphone Regulator
Note: The input clipping level corresponds to an A/D path output of 3.14 dBm0. itance for stable VREG operation is 0.1 µF , with a maximum noise of 200 µVrms. Table 14. Analog Input Characteristics and Requirements Table 15. Microphone Regulator Characteristics
10 Analog Characteristics and Requirements(continued)
10.2 Analog-to-Digital Path
7) to PCM output when EIGS = 1. to distortion plus noise ratio is no better than 60 dB.
- Gain is relative to the 0 dBm0 signal level with EIGS = 0 and IRSEL = 0.
Table 16. A/D Signal to Distortion Plus Noise Ratio
0.5 Vp Range
0.16 Vp Range
1.578 Vp Range
Table 17. A/D Relative Gain Accuracy* Table 18. A/D Frequency Response Relative to 1 kHz Output Level (fOS = 1 MHz and fS = 8 kHz)
4000 Hz — –6 — –6 dB
4600 Hz — –35 — –35 dB
8000 Hz — –45 — –45 dB
10.3 Digital-to-Analog Path
load. For a single-ended load, the D/A SDNR is degraded by about 6 dB. to distortion plus noise ratio is no better than 60 dB. Table 19. D/A Signal to Distortion Plus Noise Ratio (0 dB Output Setting) Table 20. D/A Relative Gain Accuracy* ified with a differential load; a single-ended load adds ±0.1 dB to absolute gain. Table 21. D/A Output Gain Adjustment
10.4 Miscellaneous
VDD or VSS (ground) through the load. Table 22. D/A Frequency Response Relative to 1 kHz Output Level (fOS = 1 MHz and fS = 8 kHz) Table 23. Other Analog Characteristics and Requirements*
Lucent Technologies Inc. Data Sheet CSP1027 Voice Band Codec for December 1999 Cellular Handset and Modem Applications
11 Timing Characteristics and Requirements
The following timing characteristics and requirements are preliminary information and are subject to change. Tim- ing characteristics refer to the behavior of the device under specified conditions. Timing requirements refer to con- ditions imposed on the user for proper operation of the device. All timing data is valid for the following conditions: T A = –40 °C to +85 °C or 0 °C to 70 °C (See Section 8.2 on page 47.) Capacitance load on outputs (CL) = 50 pF Output characteristics can be derated as a function of load capacitance (CL). All outputs: dt/dCL ≤ 0.06 ns/pF for 0 ≤ CL ≤ 100 pF at VIH for rising edge dt/dCL ≤ 0.05 ns/pF for 0 ≤ CL ≤ 100 pF at VIL for falling edge For example, if the actual load capacitance is 30 pF instead of 50 pF , the derating for a rising edge is (30 pF – 50 pF) x 0.06 ns/pF = 1.2 ns less than the specified rise time or delay which includes a rise time. Test conditions for inputs: ■ Rise and fall times of 4 ns or less ■ Timing reference levels for delays = VIH, VIL Test conditions for outputs: ■ C LOAD = 50 pF ■ Timing reference levels for delays = VIH, VIL ■ 3-state delays measured to the high-impedance state of the output driver
11 Timing Characteristics and Requirements(continued)
11.1 Clock Generation
† CDIV0 = 2, CDIV1 = 1 configuration shown (see Table 8 on page 27). ‡ CDIV2 = 4 option shown (see Table 8 on page 27). Figure 39. Clock Timing Diagram
- Device is fully static, t1 is tested at 500 ns.
Table 24. Timing Requirements for Input Clock Table 25. Timing Characteristics for Output Clocks
11.2 Power-On Reset
on and a power-on following a drop in the power supply. Figure 40. Power-On Reset Timing Diagram Note: The device needs to be clocked for at least six CLK cycles during reset after power-on. Otherwise, high and unstable current may flow. Table 26. Timing Requirement for Power-On Reset Table 27. Timing Characteristic for Power-On Reset
11.3 Reset
Note: CKO1 and CKO2 are active during reset and synchronized by the rising edge of reset. Figure 41. Reset Timing Table 28. Timing Requirements for Reset Timing
11.4 Serial I/O Communication
Figure 42. Serial Input/Output Timing Diagram Table 29. Timing Requirements for Serial Input/Output Table 30. Timing Characteristics for Serial Input/Output
Figure 43. Serial I/O Active Mode Timing Diagram Table 31. Timing Characteristics for Active Mode
11.5 Serial Multiprocessor Communication
Figure 44. SIO Multiprocessor Timing Diagram Note: Capacitance load on DO, SYNC, and SADD = 100 pF . Table 32. Timing Requirements for Multiprocessor Communication Table 33. Timing Characteristics for Multiprocessor Communication
CSP1027 Voice Band Codec for Data Sheet Cellular Handset and Modem Applications December 1999 Lucent Technologies Inc.62
12 Outline Diagrams
12.1 44-Pin EIAJ Quad Flat Pack (QFP) Controlling dimensions are in millimeters. Note: The production line has been qualified at Lucent-SGP for this outline; also second-source (Shinko) tolerances have been accommodated on the above diagram. 10.00 ± 0.20 13.20 ± 0.20 10.00 ± 0.20 13.20 ± 0.20 PIN #1 IDENTIFIER ZONE 12 22
0.80 TYP
2.35 MAX 0.10 SEATING PLANE 1.95/2.10DETAIL B
0.25 MAX
0.30/0.45 0.20 M 0.130/0.230 DETAIL B 0.25 0.73/1.03
1.60 REF
5-2111 (F) r.12
Lucent Technologies Inc. Data Sheet CSP1027 Voice Band Codec for December 1999 Cellular Handset and Modem Applications
12 Outline Diagrams(continued)
12.2 48-Pin EIAJ Thin Quad Flat Pack (TQFP) Controlling dimensions are in millimeters. Note: The above outline fully meets JEDEC Standard MO-136 dated April 1993. PIN #1 IDENTIFIER ZONE 7.00 ± 0.20 48 37 9.00 ± 0.20 7.00 ± 0.20
1.60 MAX
0.08 1.40 ± 0.05 0.50 TYP 0.05/0.15 DETAIL B 9.00 ± 0.20 DETAIL B 0.19/0.27 0.08 M 0.106/0.200 DETAIL A 0.45/0.75 GAGE PLANE SEATING PLANE
1.00 REF
0.25 5-2363 (F) r.8
Lucent T echnologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Copyright © 1999 Lucent Technologies Inc. All Rights Reserved December 1999 DS00-063AUTO (Replaces DS99-081WDSP) For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro E-MAIL: docmaster@micro.lucent.com N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent T echnologies (China) Co., Ltd., A-F2, 23/F , Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P . R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 JAPAN: Microelectronics Group, Lucent T echnologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, T okyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries:GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), IT AL Y: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)