CS82C88

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Document overview

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Technical content

Features

• Compatible with Bipolar 8288
• Performance Compatible with: -8 0 8 9
• Provides Advanced Commands for Multi-Master Busses
• Three-State Command Outputs
• Bipolar Drive Capability
• Scaled SAJI IV CMOS Process
• Single 5V Power Supply
• Low Power Operation
• Operating Temperature Ranges
• Pb-Free Plus Anneal Available (RoHS Compliant) 1IOB CLK ALE GND DT/ R AEN MRDC AMWC MWTC VCC MCE/PDEN DEN CEN IORC AIOWC IOWC INTA 91 0 1 1 1 213 321 2 0 1 9 ALE DT/ R AEN MRDC AMWC GND IORC AIOWC IOWC MWTC VCC IOB CLK DEN CEN MCE/PDEN INTA

Ordering Information

(°C) PKG. DWG. # CP82C88Z (Note) (No longer available or supported) CP82C88Z 20 Ld PDIP (Pb-free) 0 to +70 E20.3 CS82C88 (No longer available or supported) CS82C88 20 Ld PLCC 0 to +70 N20.35 MR82C88/B No longer available or supported) MR82C88/B 20 Pad CLCC -55 to +125 J20.A MD82C88/B MD82C88/B 20 Ld CERDIP -55 to +125 F20.3 8406901RA 8406901RA SMD# F20.3 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

FN2979 Rev 3.00 Page 2 of 12 August 13, 2015 Functional Diagram Pin Description PIN SYMBOL NUMBER TYPE DESCRIPTION VCC 20 V CC: The +5V power supply pin. A 0.1F capacitor between pins 10 and 20 is recommended for decoupling. GND 10 GROUND. S0, S1, S2 19, 3, 18 I STATUS INPUT PINS: These pins are the input pins from the 80C86, 80C88,8086/88, 8089 processors. The 82C88 decodes these inputs to generate command and control signals at the appropriate time. When Status pins are not in use (passive), command outputs are held HIGH (See Table1). CLK 2 I CLOCK: This is a CMOS compat ible input which receives a clock signal from the 82C84A or 82C85 clock generator and serves to establish when command/control signals are generated. ALE 5 O ADDRESS LATCH ENABLE: This signal serves to strobe an address into the address latches. This signal is active HIGH and latching occurs on the falling (HIGH to LOW) transition. ALE is intended for use with transparent D type latches, such as the 82C82 and 82C83H. DEN 16 O DATA ENABLE: This signal s erves to enable data transceivers onto either the local or system data bus. This signal is active HIGH. DT/R 4 O DATA TRANSMIT/RECEIVE: This signal establishes the direction of data flow through the transceivers. A HIGH on this line indicates Transmit (write to I/O or memory) and a LOW indicates Receive (read from I/O or memory). AEN 6 I ADDRESS ENABLE: AEN enables command outputs of the 82C88 Bus Controller a minimum of 110ns (250ns maximum) after it becomes active (LOW). AEN going inactive immediately three-states the command output drivers. AEN does not affect the I/O command lines if the 82C88 is in the I/O Bus mode (IOB tied HIGH). CEN 15 I COMMAND ENABLE: When this signal is LOW all 82C88 command outputs and the DEN and PDEN control outputs are forced to their Inactive state. When this signal is HIGH, these same outputs are enabled. IOB 1 I INPUT/OUTPUT BUS MODE: When the IOB pin is strapped HIGH, the 82C88 functions in the I/O Bus mode. When it is strapped LOW, the 82C88 functions in the System Bus mode (See I/O Bus and System Bus sections). AIOWC 12 O ADVANCED I/O WRITE COMMAND: The AIOWC issues an I/O Write Command earlier in the machine cycle to give I/O devices an early indication of a write instruction. Its timing is the same as a read command signal. AIOWC is active LOW. IOWC 11 O I/O WRITE COMMAND: This comm and line instructs an I/O device to read the data on the data bus. The signal is active LOW. IORC 13 O I/O READ COMMAND: This command line instructs an I/O device to drive its data onto the data bus. This signal is active LOW. VCC GND COMMAND SIGNALS MULTIBUSTM CONTROL INPUT IOB CEN CLK AEN CONTROL SIGNAL GENERATOR DEN ALE DT/R MCE/PDEN COMMAND SIGNAL GENERATOR AIOWC IOWC AMWC MWTC MRDC IORCS2 INTA ADDRESS LATCH, DATA TRANSCEIVER, AND INTERRUPT CONTROL SIGNALS CONTROL LOGIC STATUS DECODER

determine what command is to be issued (see Table 1). involved when the CPU wants to gain access to the I/O bus. exist in a multi-processor system. controller (on the AEN line) when the bus is free for use. Both memory and I/O commands wait for bus arbitration. and memory are shared by more than one processor. place vectoring information onto the data bus. bus. This signal is active LOW. acknowledged and that it should drive vectoring information onto the data bus. This signal is active LOW. for the I/O bus that DEN performs for the system bus. PDEN is active LOW. TABLE 1. COMMAND DECODE DEFINITION

111 P a s s i v e N o n e

FN2979 Rev 3.00 Page 4 of 12 August 13, 2015 transfer. These two signals usually go to the chip select and direction pins of a transceiver. The MCE/PDEN pin changes function with the two modes of the 82C88. When the 82C88 is in the IOB mode (IOB HIGH), the PDEN signal serves as a dedicated data enable signal for the I/O or Peripheral System bus. Interrupt Acknowledge and MCE The MCE signal is used during an interrupt acknowledge cycle if the 82C88 is in the System Bus mode (IOB LOW). During any interrupt sequence, there are two interrupt acknowledge cycles that occur back to back. During the first interrupt cycle no data or address transfers take place. Logic should be provided to mask off MCE during this cycle. Just before the second cycle begins the MCE signal gates a master Priority Interrupt Controller’s (PIC) cascade address onto the processor’s local bus where ALE (Address Latch Enable) strobes it into the address latches. On the leading edge of the second interrupt cycle, the addressed slave PIC gates an interrupt vector onto the system data bus where it is read by the processor. If the system contains only one PIC, the MCE signal is not used. In this case, the second Interrupt Acknowledge signal gates the interrupt vector onto the processor bus. Address Latch Enable and Halt Address Latch Enable (ALE) occurs during each machine cycle and serves to strobe the current address into the 82C82/82C83H address latches. ALE also serves to strobe the status (S0 , S1, S2) into a latch for halt state decoding. Command Enable The Command Enable (CEN) input acts as a command qualifier for the 82C88. If the CEN pin is high, the 82C88 functions normally. If the CEN pin is pulled LOW, all command lines are held in their inactive state (not three- state). This feature can be used to implement memory partitioning and to eliminate address conflicts between system bus devices and resident bus devices.

FN2979 Rev 3.00 Page 5 of 12 August 13, 2015 Absolute Maximum Ratings Thermal Information Operating Conditions Operating Temperature Range Thermal Resistance (Typical)  JA (°C/W) JC (°C/W) Maximum Junction Temperature (PLCC - Lead Tips Only) Die Characteristics CAUTION: Stresses above those listed in “Abs olute Maximum Ratings” may cause permanent dam age to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TA = 0°C to +70°C (C82C88); TA = -40°C to +85°C (I82C88); TA = -55°C to +125°C (M82C88) SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS VIH Logical One Input Voltage 2.0 2.2 V V C82C88, I82C88 M82C88 VIL Logical Zero Input Voltage - 0.8 V VIHC CLK Logical One Input Voltage V CC -0.8 - V VILC CLK Logical Zero Input Voltage - 0.8 V VOH Output High Voltage Command Outputs 3.0 VCC -0.4 V IOH = -8.0mA IOH = -2.5mA Output High Voltage Control Outputs 3.0 VCC -0.4 V IOH = -4.0mA IOH = -2.5mA VOL Output Low Voltage Command Outputs -0 . 5 V I OL= +12.0mA Output Low Voltage Control Outputs -0 . 4 V I OL = +8.0mA II Input Leakage Current -1.0 1.0 AV IN = GND or VCC, except S0, S1, S2, DIP Pins 1-2, 6, 15 IBHH Input Leakage Current-Status Bus -50 -300 AV IN = 2.0V, S0, S1, S2 (See Note 1) IO Output Leakage Current -10.0 10.0 AV O = GND or VCC, IOB = GND, AEN = VCC, DIP Pins 7-9, 11-14 ICCSB Standby Power Supply - 10 AV CC = 5.5V, VIN = VCC or GND, Outputs Open ICCOP Operating Power Supply Current - 1 mA/MHz V CC = 5.5V, Outputs Open (See Note 2) NOTES: 1. IBHH should be measured after raising the VIN on S0, S1, S2 to VCC and then lowering to valid input high level of 2.0V. 2. ICCOP = 1mA/MHz of CLK cycle time (TCLCL) Capacitance TA = +25°C SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS CIN Input Capacitance 10 pF FREQ = 1MHz, all measurements are referenced to device GNDCOUT Output Capacitance 17 pF

FN2979 Rev 3.00 Page 6 of 12 August 13, 2015 TA = 0°C to +70°C (C82C88); TA = -40°C to +85°C (I82C88); TA = -55°C to +125°C (M82C88) SYMBOL PARAMETER 8MHz 10MHz 12MHz UNITS TEST CONDITIONSMIN MAX MIN MAX MIN MAX TIMING REQUIREMENTS (1) TCLCL CLK Cycle Period 125 - 100 - 83 - ns (2) TCLCH CLK Low Time 55 - 50 - 34 - ns (3) TCHCL CLK High Time 40 - 37 - 34 - ns (4) TSVCH Status Active Setup Time 35 - 35 - 35 - ns (5) TCHSV Status Inactive Hold Time 10 - 10 - 5 - ns (6) TSHCL Status Inactive Setup Time 35 - 35 - 35 - ns (7) TCLSH Status Active Hold Time 10 - 10 - 5 - ns TIMING RESPONSES (8) TCVNV Control Active Delay 5 45 5 45 5 45 ns 1 (9) TCVNX Control Inactive Delay 10 45 10 45 10 35 ns 1 (10) TCLLH ALE Active Delay (from CLK) - 20 - 20 - 20 ns 1 (11) TCLMCH MCE Active Delay (from CLK) - 25 - 23 - 23 ns 1 (12) TSVLH ALE Active Delay (from Status) - 20 - 20 - 20 ns 1 (13) TSVMCH MCE Active Delay (from Status) - 30 - 23 - 23 ns 1 (14) TCHLL ALE Inactive Delay 4 18 4 18 4 18 ns 1 (15) TCLML Command Active Delay 5 35 5 35 5 35 ns 2 (16) TCLMH Command Inactive Delay 5 35 5 35 5 35 ns 2 (17) TCHDTL Direction Control Active Delay - 50 - 50 - 50 ns 1 (18) TCHDTH Direction Control Inactive Delay - 30 - 30 - 30 ns 1 (19) TAELCH Command Enable Time (Note 1) - 40 - 40 - 40 ns 3 (20) TAEHCZ Command Disable Time (Note 2) -4 0-4 0-4 0 n s 4 (21) TAELCV Enable Delay Time 110 250 110 250 110 250 ns 2 (22) TAEVNV AEN to DEN - 25 - 25 - 25 ns 1 (23) TCEVNV CEN to DEN, PDEN -2 5-2 5-2 5 n s 1 (24) TCELRH CEN to Command - TCLML +10 -T C L M L-T C L M L n s 2 (25) TLHLL ALE High Time TCLCH - - TCLCH - - TCLCH - nn s 1 NOTES: 1. TAELCH measurement is between 1.5V and 2.5V. 2. TAEHCZ measured at 0.5V change in VOUT.

and VCC -0.4V. Input rise and fall times are driven at 1ns/V. TABLE 2. TEST CONDITION DEFINITION TABLE

FN2979 Rev 3.00 Page 8 of 12 August 13, 2015 Timing Waveforms (Note 3) NOTES: 1. Address/Data Bus is shown only for reference purposes. 2. Leading edge of ALE and MCE is determined by the falling edge of CLK or status going active. Whichever occurs last. 3. All timing measurements are made at 1.5V unless otherwise specified. FIGURE 1. STATE CLK S2, S1, S0 ADDRESS/DATA ALE MRDC, IORC, INTA, AMWC, AIOWC MWTC, IOWC DEN (READ) (INTA) PDEN (READ) (INTA) DEN (WRITE) PDEN (WRITE) DT/R (READ) (INTA) MCE T4 T1 T2 T3 T4 TCLCL (1) TCLCH (2) TCHCL (3) TCLSH (7) TSHCL (6)TSVCH (4) TCHSV (5) TCLLH (10) TSVLH (12) TCHLL (14) TCLML (15) TCLML (15) TCLMH (16) TCVNX (9) TCVNV (8) TCVNV (8) TCVNX (9) TCHDTH (18) TCHDTL (17) TCHDTH (18) TCLMCH (11) TSVMCH (13) TCVNX (9) 1WRITE DATA VALID ADDRESS VALID

FN2979 Rev 3.00 Page 10 of 12 August 13, 2015 Burn-In Circuits MD82C88 CERDIP MR82C88 CLCC NOTES: 1. VCC = 5.5V  0.5V GND = 0V VIL = -0.2V to +0.4V 3. Component Values: C1 = 0.01F (Min) F0 = 100kHz  10% F1 = F0/2 VCC A A A VCC A A A VCC A A A A A A 91 0 1 1 1 213 3 2 1 20 19 VCC/ 2 VCC/ 2 VCC/ 2 R4 R4 R4R4 VCC/ 2VCC/ 2 R1R4 R1 R4 VCCF0 F7F3 F4 VCC/ 2 VCC/ 2 VCC/ 2 VCC/ 2 VCC

FN2979 Rev 3.00 Page 11 of 12 August 13, 2015 Die Characteristics Die Dimensions: 103.5 x 116.5 x 19  1mils Metallization: Type: Si - Al Thickness: 11kÅ 2kÅ Glassivation: Type: Nitrox Thickness: 10kÅ Worst Case Current Density: 1.9 x 105 A/cm2 Metallization Mask Layout 82C88 S1 CLK IOB V CC S0 S2 MCE/ DEN CEN INTA IORCAIOWCIOWCGNDMWTCAMWC MRDC AEN ALE DT/R PDEN

FN2979 Rev 3.00 Page 12 of 12 August 13, 2015 82C88 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2002-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE August 13, 2015 FN2979.3 Updated Ordering Information Table on pa ge 1. Added Revision History and About Intersil sections.