CS5920

CS5920 AMCC | Alldatasheet

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Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 1 S5920 PCI Product Data Sheet S5920 PCI PRODUCT

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 2 Data Book

FEATURES

• Full 132 Mbytes/sec Transfer Rate
• PCI Bus Operation to 33 MHz
• PCI Purposed 2.2 Co mpliant Target/Slave Device
• Add-On Bus up to 40 MHz
• Programmable Prefetch and Wait States
• 8/16/32-Bit Add-On Bus
• Four Definable Pass-Thru Regions
• Two 32-Byte Burstable FIFOs
• Active/Passive Add-On Bus Operation
• Mailbox Registers/w Byte Level Status
• Direct Mailbox Data Strobe/Int Pin
• Mailbox Read/Write Interrupts
• Direct PCI and Add-On Interrupt Pins
• Plug-N-Play Compatible
• Two-wire Serial Bus nvRAM Support
• Optional External BIOS capability
• 160-Pin PQFP with Gr een/RoHS compliant lead free option

APPLICATIONS

• ISA Conversions
• Multimedia
• I/O Ports
• Data Storage
• C O D E C 5
• General Purpose PCI Bus Interfacing ARCHITECTURAL OVERVIEW The AMCC S5920 was developed to provide the designer with a single mult i-function device offering a flexible and easy way to connect to the PCI bus. By using the S5920, the designer eliminates the task of assuring PCI bus specific ation compliance and the necessity of understanding PCI bus timing require ments when interfacing a new application. The complex 33 MHz PCI bus signals are converted through the S5920 into an easy-to-use 8/16/32-bit user bus referred to as the user Add-On bus. The Add- On bus allows user add-on designs bus clock speed independent operation to 40 MHz.

Figure 1. S5920 Block Diagram

2.1 PCI

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 3 Data Book

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 4 Data Book

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 5 Data Book

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 6 Data Book

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 8 Data Book

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 9 Data Book Functional Operation Range Add-On Timings, Functional Operation Range Add-On Timings Functional Operation Range (VCC = 5.0 V ± 5%, 0°C to 70°C, 50 pF load on outputs for MAX, 0 pF load for Mailbox Timings

wide networking infrastructure. communications, ATE, computer and military markets. ologies to develop the original products. Figure 2. AMCC Product Development Strategy

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 11 Data Book AMCC interface circuits, transceiver chips and switches are designed to implement emerging network technologies such as t he ANSI Fibre Channel and High Performance Interfac e (HIPPI) standards, the ITU SONET telecommunicat ions standard, the ATM Forum LAN standard and IEEE Gigabit Ethernet stan dard. Jitter, speed, power and size are critical design issues for all these circuits. AMCC’s devices are based on its unique Bipolar process which has noise isolation characteristics that enable best-in-class jitter performances. The inherent physical structure of the company’s process makes 1 to 3 GigaHertz (GHz) data rates possible at low power. Consequently, the low device power consumption of AMCC’s products helps to minimize the cost and size of packaging. Peripheral Component Interconnect (PCI) Bus Controllers Increasing bandwidth of high speed networks creates a bottleneck at the desktop. One of the causes of this problem is the latency associated with connection to high speed peripheral equipment over LANs and WANs. The 132 Megabyte per second backplane PCI bus helps break the bottleneck. AMCC has developed the industry’s first line of gen - eral purpose master/slave controllers for the PCI bus. These circuits provide a high performance single-chip interface for add-on boards and adapter cards for industrial, graphics, video and communications markets. Precision Clock and Timing Products AMCC provides a line of high precision clock and tim - ing standard products for exacting system designs. AMCC has also tailored clock and timing devices to specific customer needs for high performance clock generation and distribution, clock synchronization and de-skewing, frequency synthesis, and pulse shaping applications. Offerings incl ude low EMI, low skew clock drivers and low jitter clock generators for high performance server, work-station and RAMBUS™- based applications. Manufacturing Excellence AMCC manufactures its own Bipolar and BiCMOS wafers using proven proc esses and utilizes foundry relationships for access to CMOS capability in its world class fab located in San Diego. AMCC is proud of its best-in-class status for lowest defect densities for like sized fabs. This allows AMCC to provide a continuous, predictable supply of product to its customers. The Company follows a “semi-fabbed” manufacturing strategy and has CMOS and BiCMOS foundry rela tionships in place with major domestic and international semiconductor partners that provide for significant additional production capacity. Wafer pur chases from strategic foundry partners both expand capacity and provide alternate sources. Additional high-volume assembly and test facilities are located offshore. AMCC’s “quick turn, semi-fabbed” manufacturing approach blends together the strengths of both the “fabbed” and “fabless” semiconductor strategies. Fabbed advantages include the security of total in- house control and time to market. Fabless advantages include multiple sourcing and allows the company to focus investment on new high performance products.

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 12 Data Book AMCC COMMITMENT TO QUALITY AMCC is committed to achieving the highest quality and reliability level in the integrated circuit products we provide. Every year for over a decade we have estab - lished industry-leading reliability and outgoing quality targets and then exceeded them. The quality and reliability philosophy at AMCC starts with the premise that for AMCC to continue to excel and be the premier supplier to our customers, the quality expectations of customers must be consistently met or exceeded. Our team operating philosophy is to: 1. design in manufacturab ility and reliability during the new product development phase (plan); 2. build in quality at all manufacturing steps (do); 3. execute thorough produc t inspections, internal audits and reliability confirmation (check); 4. incorporate feedback from internal and external sources into continuous quality improvement pro - grams (act). Reliability and Manufacturability—Designed In From The Start Reliability and manufacturability is designed in up front through a team infrastructure which focuses on active participation by Design, Manufacturing and Reliability Engineering throughout all phases of the design pro cess. This includes ext ensive design verification through computer modeling and design validation by product characterization and application simulation. Final team design revi ew and production readiness approval is required prior to release of products to production. Quality Built In During Wafer Fabrication and Man- ufacturing AMCC’s manufacturing and quality teams employ doc- umented operating procedures, work instructions, in- process inspections and SP C methodology to provide assurance of continued process control and compli - ance to specification. QA gates and subsequent feedback ensures quality confirmation of AMCC’s final product in a continuous improvement program. Inspection, Audit and Reliability Confirmation AMCC has strategically placed In-Process Quality Control (IPQC) gates, internal process/area audits and lot/time specific reliability monitors to verify perfor mance against customer requirements and internal design/manufacturing proces s capabilities. Metrics generated by these activities are intended to provide continuous improvement feedback data for review and action as driven by senior management.

• Die visual and precap gate
• Final outgoing inspection gate
• Modified MIL-STD-105D sampling program
• Lot specific group A and B testing
• Ongoing reliability monitors
• SPC/Data metric review of key subcontractors
• Visual/mechanical and electrical outgoing indi - ces and PPM goals
• Cost-of-quality pareto analysis Documentation Customer Design/Manufacturing

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 13 Data Book Continuous Quality Improvement Program

• Corporate-wide commitment driven by the Executive Staff
• A program plan that is flexible enough to com - prehend dynamic customer inputs
• Statistical tools in place for analysis and action planning
• Weekly and monthly review meetings to share performance data
• Self examination consistent with elements in ISO9001 and the Malcolm Baldridge National Quality Award AMCC QUALITY SYSTEM The Quality System had been modeled after the strin - gent military requirements of MIL-I-45208, MIL-Q-9858 and MIL-I-38535 Appendix A. Heading into the 21st century, AMCC has now modified its Quality System to also align with ISO9001. This has strengthened the closed loop improvement cycle by tying internal audits with corrective/preventat ive action though continuous management review. AMCC’s Quality System has the following components integrated throughout the factory to meet or exceed the above requirements.
• Quality Organization
• Quality Planning
• Management Review
• Contract Review
• Design Control
• Document and Data Control
• Purchasing
• Supplier Select ion and Control
• Control of Customer Supplied Materials
• Product Identificat ion and Traceability
• Operating Procedures
• Work Instructions
• Inspection and Test
• Inspection, Measurement and Test Equipment Calibration
• Inspection Status System
• Control of Nonconforming Material
• Corrective and Pr eventive Action
• ESD Safe Handling, Storage, Packaging, Pres - ervation and Delivery Methods
• Records Retention and Maintenance
• Internal Process/Ar ea Auditing System
• Training/Certification
• SPC and Statistical Techniques
• Failure Analysis ISO9001 REGISTRATION Based on the restructure of the Quality System to ISO9001 requirements and successful completion of internal and third-party audits, AMCC was ISO regis tered on July 29, 1996. Bi-yearly surveillance audits have been successfully passed as well. Please con tact the factory for further details and schedule updates. AMCC Quality Philosophy ISO9001 AMCC Quality Manual AMCC QA Practices Manufac- turing Materials Inspection and Test Design Customer Conform- ance Rqmts Superior Product Quality

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 14 Data Book PRODUCT QUALIFICATIONS A qualification is a sequence of tests in which all parameters, including the reliability of the device are tested. It is this sequence of tests which initially qual- ifies the part to be released for production. Thorough reliability testi ng is performed on new prod - uct and package families in order to ensure the expectations of our customers are met. These tests include environmental, mechanical and life testing per formed in accordance with Military Standards, industrial accepted methods and AMCC Test Proce dures. Contact the factory for specific details regarding your selected product/package combination. AMCC provides MIL-STD-883 Methods 5005 and 5010 testing for our military customers on contract as well as MIL-H-38534 quality conformance screening for hybrid customers. MIL-STD-883 Method 5005 “Qualification And Quality Conformance Proce- dures” Method 5005 establishes qualification and quality-con- formance inspection procedu res for semi-conductors to ensure that the quality of devices and lot conform with the requirements of the applicable procurement document. The full requirements of Group A, B, C, D, and E test and inspections are intended for use in ini tial device qualification—or requalification in the event of product or process change—and in periodic testing for retaining qualification. Group A consists of electrical tests performed on an inspection lot which has already passed the 100% screening requirements. After a lot has passed the 100% screen tests, a random sample of parts is selected from the total population of devices to form the inspection lot. The inspec tion lot is then subjected to these Group A electrical tests. Group B inspection tests are used to monitor the fabri- cation and assembly processes performed on each inspection lot. Group C consists of a 1000-hour life test conducted to verify die integrity. Group D verifies the material integrity and the reliabil - ity of the package. Group E demonstrates the radiation hardness capa - bility of the device. Perfor med on a generic basis by device type or as required for an application. MIL-STD-883 Method 5010 “Test Procedures For Custom Monolithic Microcir- cuits” This method establishes screening and quality con - formance procedures for the testing of custom and semicustom monolithic semiconductors to verify Class B or Class S quality and reli ability levels. Testing is performed in conjunction with other documentation such as MIL-I-38535 and an applicable detail specification. It establishes the design, material, performance, con - trol, and documentation requirements needed to achieve prescribed levels of device quality and reliabil ity. AMCC can support qualification using this method. Until August of 1983, the qualification most commonly used was Method 5005. Since that time, the newer revision of MIL-STD-883 includes Method 5010, which is better suited for semicu stom devices (logic arrays included). Either qualification is adequate, but it is desirable to use the 5010 qu alification procedure in qualifying custom or semicustom devices. Qualification Method 5005 VS. 5010 The primary difference between the two methods is in the Group D test. Method 5005 uses electrically-good devices, where method 5010 uses electrical rejects and package-only parts for environmental tests. In addition, Method 5010 is designed for smaller produc tion releases (i.e., 2000 devices/year) while Method 5005 is designed for large production releases. Generic Data Under the provision of MI L-I-38535, a customer can elect to qualify using generic data (similar device/fam - ily). However, the provisions of the applicable contract should be reviewed. In most cases generic data will satisfy full qualification requirements. Since many of the qualifications at AMCC are ongoing, generic data may be available for this purpose.

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 15 Data Book AMCC Product Assurance Product Flow Detail

• Component Selection
• Definition — Specification
• Supplier: Selection — Qualification — Approval
• Qualified Vendors List (QVL)
• Acceptance Documents and Operating Proce - dures
• Purchase Order
• Component/Material Specifications
• Product Assurance and General Procedures
• QVL
• Sample Inspection of All Direct Materials
• Class 10 Clean Room — FED-STD-209
• Measurements in Adherence with MIL-STD- 977
• SPC:
• In-process Monitors
• PCM Electricals
• SEM Inspection on All Military Lots
• QA Audits
• CV Plots —Weekly (minimum)
• DI Water —Weekly
• Particle Counts
• Bacteria Count
• Airborne Particle Count —Weekly Design For Manufacturability And Reliability Incoming Inspection Wafer Fabrication Wafer Electrical Test Wafer Stores

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 16 Data Book 1. MIL-H-38534 or MIL-STD-883 method 5010 also available. AMCC Product Assurance Product Flow Detail

• IPQC Audit
• Manufacturing Procedures
• Method 5004 1
• I P Q C
• Customer Source Inspection (CSI)
• Assembly Final Inspection
• Method 5004 (No Centrifuge)
• I P Q C
• Assembly Final Inspection
• Precap Visual
• Die Shear SPC
• Wire Bond SPC
• Mold/External Visual
• Lead Trim and Copla - natary Inspection
• Methods 5004 & 5005 1
• Methods 5004 & 5005 1
• I P Q C
• Group A
• 25°C — 100%
• 0°C & 70°C — AQL=0.25% Sample
• Method 5005 1
• I P Q C
• Final Inspection •I P Q C
• Final Inspection
• Coplanatary Check
• Method 5005 1
• Per Order
• I P Q C
• Outgoing Inspec - tion
• I P Q C
• Outgoing Inspec - tion Assembly Issue Assembly and Environmental Screening Pre-Electrical and Burn-In Final Electrical Test Group B Group C & D CSI Packaging for Shipment Ship Hermetic Commercial Flow Hermetic Military Flow Plastic Flow

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 17 Data Book AMCC’S RELIABILITY VIGIL AMCC’s internal reliability vigil consists of three phases:

• New/changed processes and material qualifi - cations
• In-process Quality monitors
• Periodic operating life and environmental test - ing New/Changed Wafer Processes and Material Quali- fications In order to initially release a device to production a standard set of MIL-STD-883 tests must be completed successfully. These tests include: Wafer Process and Design
• Operating Life Method 1005
• ESD Characterization Method 3015
• Wire Bond Pull Method 2011
• Thermal Shock or Method 1011 or 1010 Tem - perature Cycling Package and Related Materials
• Selected Subgroups of MIL-STD-883, Method 5005, Group B and D AMCC adheres to MIL-I-38535 with regards to changes. If changes to production released devices are deter - mined to be major, the appropriate qualification testing must be successfully completed prior to change approval. In-Process Quality Monitors
• C V p l o t s
• Airborne particle count
• Bacteria, particle count, and resistivity on DI water
• ESD work stations and procedures
• In-line testing of process gases
• Temperature and humidity control
• SPC in wafe r fabrication
• SEM of all military lots Periodic Operating Life and Environmental Testing
• Performed on a product from each process family quarterly.
• 1000 hour operating life test (minimum), Method 5005, Group C.
• Temperature cycling per Method 1010, 100 cycles, condition C: –65°C/150°C
• Environmental testing per AMCC standard test procedures. Consult factory for further details. Final Measure and Assurance of Quality The cost of defects depends on when the failure occurs. For example, costs rise significantly as unde tected defective ICs are integrated into systems. High quality parts cut costs substantially, and the extra qual- ity built into every AMCC device means added value to our customers. To achieve maximum quality, AMCC employs 100% testing of all devices, fo llowed by stringent QA sampling. AMCC performs QA sampling measurements at full specification temperature, both DC and AC, to achieve the tightest AQLs in the industry. RADIATION HARDNESS High energy radiation can cause structural changes in the silicon and silicon dioxide crystal lattice by displac- ing atoms from their normal crystal sites. These changes can be responsible for increased junction leakage, degraded transistor current gain (b), and increased parasitic Si/SiO2 interface leakage currents. The damage is generally induced by neutrons, X-rays, and gamma rays. The effects of the damage induced by this radiation can change both AC and DC parame ters, affect functional performance, and, in severe cases, destroy the device. Certain of AMCC’s high performance products are inherently radiation resistant. The radiation resistance of AMCC IC’s is the result of the small geometries, the structure of the fabricatio n process itself, and the use of ECL logic within the device. Contact your AMCC representative regarding radiation resistance charac teristics associated with a specific product.

Table 1. ATM LAN and 100VG AnyLAN Products See Network Products data book or http://www.amcc.com. Table 2. Fibre Channel/Gigabit Ethernet Products

See Network Products data book or http://www.amcc.com. See Network Products data book or http://www.amcc.com. Table 3. HIPPI Products Table 4. PCI Products Table 5. SONET/SDH/ATM Products

See Network Products data book or http://www.amcc.com. See Network Products data book or http://www.amcc.com. See Network Products data book or http://www.amcc.com. Table 6. SONET/SDH/ATM Products (continued) Table 7. Crosspoint Switch Products Table 8. Precision Clocking Products

See Network Products data book or http://www.amcc.com. See Network Products data book or http://www.amcc.com. Table 9. Clock Generator and Synthesizer Products

4403 Multiphase Clock

4405 Multiphase Clock

4503 Clock Synthesizer XTAL 2 1 TTL PECL 80 300 N/A Multiply 2-32

Table 10. ASIC Standard Cell Products

• 1 GHz Timing Vernier
• Custom Analog
• + 5 V
• + 5 V / - 5 V
• - 5 V
• + 3 . 3 V

See Network Products data book or http://www.amcc.com. Table 11. ASIC Logic Array Products

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 23 Data Book ARCHITECTURAL OVERVIEW S5920 Since the S5920 is a PCI Target or Slave device only, its cost is significantly less than PCI Bus Master solu - tions. The S5920 is PCI purposed 2.2 compliant and can support data transfer rates up to 132 Mbytes/sec. Burst transfers and single data transfers are both sup ported. Figure 1 shows the block diagram for the S5920. Many additional S5920 features offer the user easier hardware and software implementation. Up to four memory or I/O size definab le blocks, referred to as Pass-Thru‘ regions, are pr ovided for multiple device configurations. Data transfers via a Pass-Thru region can be performed either direct to the Add-On bus or through two 32-Byte burstable FIFOs. Added read prefetch and programmable FI FO wait state features allow the user to tune system performance. The Pass- Thru data channel also supports an active/passive mode bus interface. Passive mode requires the designer to transfer data by externally driving the Add- On bus. Active mode minimizes design components by enabling internal logic to drive or acquire the Add- On bus to read or write data independently. Active mode provides programmabl e wait state generation for slower Add-On designs. Two 32-bit mailbox registers are implemented for addi- tional data or user-defined status/command transfers. Each mailbox may be examined for empty or full, at the byte level, through a mailbox status register. Mail box transfers can be either register style or hardware direct. Dedicated exter nal mailbox data and strobe pins are provided for direct hardware read/writes and allow Add-On to PCI interrupt capabilities. A direct Add-On to a PCI bus interrupt pin is incorporated, add- ing design flexibility. The S5920 supports a two-wire serial nvRAM. This allows the designer to customize the device configura tion to be loaded during power-up initialization. An expansion BIOS may also be contained in the nvRAM. S5920 REGISTER ARCHITECTURE S5920 communications, control and configuration is performed through three prim ary groups of registers: PCI Configuration Registers, PCI Operation Registers and Add-On Operation Registers. All of these registers are user configurable through their associated buses and from the external nvRAM. The following sections provide a brief overview of each register group and the nvRAM interface. PCI Configuration Registers All PCI compliant devices are required to provide a group of PCI config uration registers. These registers are polled by the host BIOS system during power-up initialization. They contain specific device and product information such as Vendor ID, Device ID, Subsystem Vendor ID, memory requirements, etc. These registers are located in the S5920 and are either initialized with predefined default values or user customized defini tions contained in the external nvRAM. PCI Bus Accessible Registers The second group of registers are the PCI Operation Registers. This group of registers is accessible to the PCI Bus. These are the primary registers through which the PCI Host configures the S5920 operation and communicates with the Add-On Bus. These regis ters encompass the PCI bu s mailboxes, Pass-Thru/ FIFO data channel and Status/ Control registers. Add-On Bus Accessible Registers The last register group consists of the Add-On Opera - tion Registers. This group of registers is accessible via the Add-On Bus. These ar e the primary registers through which the Add-On application configures S5920 operation and communicates with the PCI Bus. These registers encompass the Add-On bus mail boxes, Pass-Thru/FIFO Registers and Status/Control Registers. SERIAL NON-VOLATILE INTERFACE Previously indicated, the S5920 contains the required set of PCI Configuration Re gisters. These registers can be initialized with default values or with custom ized values contained in an external nvRAM. The nvRAM allows Add-On card manufacturers to initialize the S5920 with their specific Vendor ID values, along with other desired S5920 operation characteristics.

Figure 3. S5920 Pinout

The mailbox registers are divided into two 4-byte sets. assembly or disassembly of 32-bit data. requested transfer is completed. Figure 4. Mailbox Block Diagram

speed. Figure 4 illustrates the Pass-Thru block. improve performance of sl ow Add-On bus designs. states since data has been prefetched into the FIFO. enabled to tune system performance. tion mimics that of the S5933 Add-On bus operation. incorporates programmable wait states from 0 to 7. Figure 5. Pass-Thru Block Diagram

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 27 Data Book Signal Type Definitions Note: Tri-State® is a Registered Trademark of National Semiconductor. The following signal types are taken from the PCI Bus Specification. in Input is a standard input-only signal. out Totem Pole Output is a standard active driver. t/s Tri-State ®is a bi-directional, tri-state input/output pin. s/t/s Sustained Tri-State is an active low tri-state signal owned and driven by one and only one agent at a time. The agent that drives an s/t/s pin low must drive it high for at least one clock before letting it float. A new agent cannot start driving an s/t/s signal any sooner than one clock after the previous owner tri-states it. A pull-up is required to sustain the inactive state until another agent drives it, and must be provided by the central source. o/d Open Drain allows multiple devices to share as a wire-OR. Each signal that assumes the logic low state when asserted is followed by the pound sign (#). Example: TRDY# signal is asserted low when the target is ready to complete a data transfer. Signals that are not followed by the pound sign are asserted when they assume the logic high state. The following designations are used throughout this book when referring to the size of data objects: A BYTE is an 8-bit object. A WORD is a 16-bit, or 2-byte object. A DWORD is a double word and is a 32-bit or 4-byte object. All hex numbers are followed by an “h”. Examples: 9A4Fh 0110h All binary numbers are followed by an “b”. Examples: 1010b 0110b All decimal numbers are followed by an “d”. Examples: 4356d 1101d

Figure 6. S5920 Pin Assignment

The following sets of signals represent the interface pins available for the S5920 to PCI bus. Table 12. PCI Bus Address and Data Signal and TRDY# are both asserted. used as Byte Enables, with C/BE[0]# enabling byte 0 (LSB) and C/BE[3]# enabling byte 3 (MSB).

0000 Interrupt Acknowledge

0001 Special Cycle

0010 I/O Read

0011 I/O Write

0100 Reserved

0101 Reserved

0110 Memory Read

0111 Memory Write

1000 Reserved

1001 Reserved

1010 Configuration Read

1011 Configuration Write

1100 Memory Read Multiple

1101 Dual Address Cycle

1110 Memory Read Line

1111 Memory Write and Invalidate

TRDY# active. The PAR signal has the same timing as AD[31:0], delayed by one clock.

Table 13. PCI Bus System Signals RST# and INTA#. The maximum PCLK frequency for the S5920 is 33 MHz and the minimum is DC (0 Hz).

• All PCI bus output signals tri-stated.
• All open drain signals (i.e., SERR#) floated.
• All registers set to their factory defaults.
• Pass-Thru is returned to an idle state.

Table 14. PCI Bus Data Transfer Control Signals rent data phase. During write transactions, it indicates AD[31:0] contains valid data. occur until both TRDY# and IRDY# are asserted together. informs a bus master whether an agent has decoded a current bus cycle. INTA# o/d Interrupt A. This signal is defined as optional and level sensitive. Driving it low will interrupt to the host. The INTA# interrupt is to be used for any single function device requiring an interrupt capability. Table 15. PCI Bus Error Reporting Signals driven inactive (high) for one clock cycle prior to returning to the tri-state condition.

The following sets of signals represent the interface signals available for the user Add-On bus and S5920 control. Table 16. Serial nvRAM Interface Signals speed and enters the high Z state when FLT# is asserted or the serial bus is inactive. nvRAMs and the S5920. This pin enters high Z state when FLT# is asserted or the serial bus is inactive. Pin 135 in Reserved. Must be left open. Table 17. Direct Mailbox Access Signals nal low. This signal is connected to an internal pull-up. connected to an internal pull-up. mailbox is output to these pins. All MD[7:0] signals have an internal pull-up.

signal groups: S5920 register access signals, Pass-Thru channel signals, and general Add-On bus signals. Table 18. Pass-Thru Data Channel Pins Active mode. This mode allows the S5920 to actively drive signals and data onto the data bus. This signal is connected to an internal pull-up. ated to signal that Add-On logic Pass-Thru data must be read from or written to the S5920. Base Address Register 2, 10 = Base Address Register 3, 11 = Base Address Register 4. of a DWORD are valid to read. PTBE[3:0]# are only valid while PTATN# is asserted. affect DQ bus width while the Pass-Thru address is driven. read or write cycle. Valid only when PTATN# is active. 16- or 32-bit data transfer cycle. This signal is not used in Passive mode.

Table 19. S5920 Add-On Bus Register Access Pins either 32 or 16 bits. All DQ[31:0] signals have an internal pull-up. as zeros. Example: The Add-On incoming mailbox register is referenced as 0Ch. transactions, they serve as an input enable to perform the write to each byte lane. register defined by SELECT# and ADR[6:2]. defined by SELECT# and ADR[6:2] onto the DQ bus. assigned to the ADR1 signal and only DQ[15:0] is active. 32 bits of the Pass-Thru address are provided.

Table 20. Add-On Bus General Pins nous and can be asserted through software from the PCI host interface. behavioral characteristics of the PCI clock (i.e., DC-to-33 MHz capability). is asynchronous to the PCI bus logic unless connected to the BPCLK signal. as a result of activity within the S5920. signal is connected to an internal pull-up. Pin 149 X For factory use only. Must be left open. Pin 136 X For factory use only. Must be left open. Pin 135 X For factory use only. Must be left open. Pin 113 X For factory use only. Must be left open. Pin 29 X For factory use only. Must be left open.

definitions—and also provides an explanation of its intended usage.

1. BADR 5 is not implemented in the S5920.

Table 21. Configuration Registers

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 36 Data Book DEVICE ID 24 23 16 15 8 7 VENDOR ID RESERVED = 0's REV ID CACHE LINE SIZELATENCY TIMER BASE ADDRESS REGISTER #0 BASE ADDRESS REGISTER #1 BASE ADDRESS REGISTER #2 BASE ADDRESS REGISTER #3 BASE ADDRESS REGISTER #4 BASE ADDRESS REGISTER #5 HEADER TYPEBIST INTERRUPT LINEINTERRUPT PINMIN_GNTMAX_LAT STATUS SUBSYSTEM ID EXPANSION ROM BASE ADDRESS RESERVED = 0's RESERVED = 0's SUBSYSTEM VENDOR ID CLASS CODE COMMAND LEGEND Note: Some registers are a combination of the above. See individual sections for full description. EPROM IS DATA SOURCE (READ ONLY) CONTROL FUNCTION EPROM INITIALIZED RAM (CAN BE ALTERED FROM PCI PORT) EPROM INITIALIZED RAM (CAN BE ALTERED FROM ADD-ON PORT) HARD-WIRED TO ZEROES PCI Configuration Space Header

Figure 7. Vendor Identification Register

15.0 Vendor Identification Number: AMCC’s 16-bit value is 10E8h

defaults to AMCC's DID duri ng power-on initialization. Figure 8. Device Identification Register

15.0 Device Identification Number: AMCC’s temporary end user value 5920h

device’s ability to respond to or perform PCI accesses. Figure 9. PCI Command Register

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 40 Data Book Bit Description 15:10 Reserved. Hardwired to 0. 9 Fast Back-to-Back Enable. This bit enables fast back-to-back capability for bus master transaction. The S5920 is a target-only device and hardwires this bit to a 0. 8 System Error Enable. Setting this bit to a 1 allows the S5920 to drive the SERR# signal. Setting to a 0 will dis- able the output driver. The assertion of RESET# will set this bit to a 0. The SERR# pin driven active normally signifies a parity error occurred during a PCI address phase. 7 Wait Cycle Enable. Controls whether a device implements address/data stepping. This bit is hardwired to 0 as the S5920 does not uses stepping. 6 Parity Error Enable. This bit allows the S5920 to drive the PERR# and to generate a SERR# signal. A one allows the parity generation and a 0 will disable generation of a parity error indication. This bit is set to 0 when RESET# is asserted. 5 Palette Snoop Enable. Enables VGA compatible devices to perform palette snooping. This bit is hardwired to a 0 as the S5920 is not a PCI-based VGA device. 4 Memory Write and Invalidate Enable. This bit enables bus masters to generate Memory Write and Invalidate PCI bus commands when set to a 1. When set to 0, bus masters generate memory write commands instead. The S5920 is a PCI target only and therefore hardwires this bit to 0. 3 Special Cycle Enable. Setting this bit to one enables devices monitoring of PCI special cycles. The S5920 does not monitor (or generate) special cycles and hardwires this bit to 0. 2 Bus Master Enable. This bit allows a PCI device to function as a Bus Master. The S5920 is a PCI target device only and hardwires his bit to 0. 1 Memory Space Enable. This bit enables S5920 memory region decodes to any of the five defined base address register memory regions and the Expansion ROM Base Address Register. This bit is cleared to 0 when RESET# is asserted. 0 I/O Space Enable. This bit enables S5920 I/O region decodes to any of the five defined base address register I/ O regions. This bit is cleared to 0 when RESET# is asserted.

PCI STATUS REGISTER (PCISTS) This register contains PCI device status information. are Read Only are shown as (RO). Figure 10. PCI Status Register

66 Mhz Capable

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 42 Data Book Bit Description 15 Detected Parity Error. This bit is set whenever the S5920 detects a parity error. It is set independent of the state of Command Register Bit 6. The bit is cleared by writing a 1. 14 Signaled System Error. This bit is set whenever the S5920 generates the SERR# signal. This bit can be reset by writing a 1. 13 Received Master Abort. Bus master devices set this bit to indicate a bus master transaction has been termi- nated due to a master abort. The S5920 is a target device and hardwires this to 0. 12 Received Target Abort. This bit is set by a bus master when its transaction is terminated by a target abort from the currently addressed target device. This bit is required for bus masters and is hardwired to 0 in the S5920. 11 Signaled Target Abort. This bit is set the target device whenever it terminates a transaction with a target abort. The S5920 does not issue target aborts and hardwires this bit to 0. 10:9 Device Select Timing. These bits are read-only and define the DEVSEL# timing for a target device. The S5920 is a medium PCI device. 8 Data Parity Reported. Only implemented by bus mastering devices to notify a parity error has been detected. This is not applicable to the S5920 and is hardwired to 0. 7 Fast Back-to-back Capable. This read-only bit indicates if a target device supports fast back-to-back transac- tions. The S5920 supports this feature and hardwires the bit to 1. 6 UDF Supported. 1 = device supports user-definable features. 0 = device does not support user- definable fea- tures. The S5920 implements definable memory regions and hardwires this bit to 0. 5 66 MHz Capable. 1 = device is capable of running at 66 MHz. 0 = device is capable of running at 33 MHz. This bit is hardwired to 0. 4:0 Reserved. Hardwired to zero.

Figure 11. Revision Identification Register 7:0 Revision Identificaiton Number: Initialized to the S5920 silicon revision.

this register. Refer to the PCI specification for details. Figure 12. Class Code Register

Table 22. Defined Base Class Codes Table 23. Base Class Code 00h: Early, Pre-2.0 Specification Devices Table 24. Base Class Code 01h: Mass Storage Controllers Table 25. Base Class Code 02h: Network Controllers

Table 26. Base Class Code 03h: Display Controllers Table 27. Base Class Code 04h: Multimedia Devices Table 28. Base Class Code 05h: Memory Controllers

Table 29. Base Class Code 06h: Bridge Devices Table 30. Base Class Code 07h: Simple Communications Controllers Table 31. Base Class Code 08h: Base System Peripherals

Table 32. Base Class Code 09h: Input Devices Table 33. Base Class Code 0Ah: Docking Stations Table 34. Base Class Code 0Bh: Processors Table 35. Base Class Code 0Ch: Serial Bus Controllers

Figure 13. Cache Line Size Register

that a bus master can retain ownership of the PCI bus. ership time. The register is hardwired to zero. Figure 14. Latency Timer Register

is a single function or a multi-function PCI bus agent. The S5920 is defined as a single function PCI device. Figure 15. Header Type Register

implementation of custom, user-specific diagnostics. non-zero value for the completion code (bits 3:0). Figure 16. Built-In Self-Test Register be returned if this self-test feature is not required. This field is read only from the PCI interface. bit be cleared within 2 seconds after being set, or the device will be failed. This bit is read/write set (R/WS). 5:4 Reserved. These bits are reserved and are hardwired to 0.

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 53 Data Book BASE ADDRESS REGISTER (BADR) Base address registers are used by the system BIOS to determine how much memory or I/O address space a region requires in host space. The actual memory or I/O location(s) of the space is determined by interro gating these register s after BIOS power-up initialization. Bit zero of ea ch field is used to select whether the space required is to be decoded as mem- ory (bit 0 = 0) or I/O (bit 0 = 1). Since this PCI device has internal operating registers, the Base Address Register at offset 10h is assigned to them. The remaining four base address registers can only be used by boot-loading them fr om the external nvRAM interface. Determining Base Address Size The address space defined by a given base address register is determined by writing all 1s to a given base address register from the PCI bus and then reading that register back. The number of 0s returned starting from D4 for memory space and D2 for I/O space toward the high-order bits reveals the amount of address space desired. Tables 17 and 18 list the pos sible returned values and their corresponding size for both memory and I/O, respectively. Included in the tables are the nvRAM/EPROM boot values which correspond to a given assigned size. A register returning all 0s indicates the region is disabled. Assigning the Base Address After a base address has been sized, the BIOS can physically locate it in memory (or I/O) space. The base address value must be on a natural binary boundary for the required size. For example, the first base address register returns FFFFFF81h indicating an I/O space (D0=1) of size 80h. This means that the 5920’s internal registers can be selected for I/O addresses between 00000300h through 0000037Fh, in this example. (example 300h, 380h etc.; 338h, 340h would not be allowable). Register Name: Base Address Address Offset: 10h, 14h, 18h, 1Ch, 20h Power-up value: FFFFFF81h for offset 10h; 00000000h for all others Boot-load: External nvRAM offset 050h, 54h, 58h, 5Ch, 60h (BADR0-4) Attribute: high bits Read/Write; low bits Read Only Size: 32 bits

1. The two most significant bits define bus width for BADR1:4 in Pass-Thru operation. (See S5920 Base Address Register Definition.)
2. Bits D3, D2 and D1 may be set to indica te other attributes for the memory space.

Table 36. Base Address Register Response (Memory Assigned) to All-Ones Write Operation

1. Base Address Register 0, at offset 10h, powers up as FFFFFF81h. This default assignment allows usage without an external boot memory.

Should an nvRAM be used, the base address can be boot loaded to become a memory space (FFFFFF80h or FFFFFF82h). Table 37. Read Response (I/O Assigned) to an All-Ones Write Operation to a Base Address Register

by the S5920 from the external nvRAM at power up. Figure 19. Subsystem Vendor Identification Register 15:0 Subsystem Vendor Identification Number.

Figure 20. Subsystem Identification Register 15:0 Subsystem Identification Number.

cycles should be performed to this location. Figure 21. Expansion ROM Base Address Register 31:11 Expansion ROM Base Address Location. These bits are used to position the decoded region in memory space. controller limits the expansion ROM area to 2K bytes (due to the serial nvRAMÕs limit of 11 bits of address). The allowable returned values after all ones are written to this register are shown in Table 18. not enable/disable this Address Decode bit.

1. The Expansion ROM Base Address Register nvRAM boot value is internally hardwired to FFFFF80Xh, where X = 000xb (i.e., only the least-

Configuration read of this region will always respond with 00000000h. Table 38. Read Response to Expansion ROM Base Address Register (after all ones written)

Figure 22. Interrupt Line Register

Figure 23. Interrupt Pin Register

000 None

001 INTA#

010 INTB#

011 INTC#

100 INTD#

101 Reserved

Figure 24. Minimum Grant Register

mentation within this device. Figure 25. Maximum Latency Register

07 Bit

mended to read or write from an undefined address. teed. Table 1 lists the PCI Bus Operation Registers. Note: Absolute register address locations are acquired by adding BADR0 to the “address offset” listed above. Table 39. Operation Registers - PCI Bus

Figure 26. Outgoing Mailbox

Figure 27. Incoming Mailbox

Figure 28. Mailbox Empty/Full Status Register (MBEF) Table 40. Mailbox Empty/Full Status Register

acknowledging (removing) the interrupt’s assertion.

• The Outgoing mailbox becomes empty.
• The Incoming mailbox becomes full.
• Add-On interrupt pin enable and flag.

Figure 29. Interrupt Control Status Register

Table 41. Interrupt Control Status Register 31:24 Reserved. Always zero. generated, nor is this bit ever set, for an Add-On Interrupt without the Add-On Interrupt Enable set. its interrupt handler routine. 21:18 Reserved. Always zero. 15:14 Reserved. Always zero. has no effect on the assertion of the Add-On Interrupt Bit 22. bits 9 and 8 to produce a PCI interface interrupt. This bit is read/write. 11:10 Hardwired to 1. Reserved. identified by bits 1 and 0 to produce a PCI interface interrupt. This bit is read/write. 3:2 Hardwired to 1. Reserved.

• Assert reset to Add-On
• Reset mailbox empty full status flags
• Write/Read external non-volatile memory
• Reset Pass-Thru Read FIFO

Figure 30. FIFO Control/Status Register

Table 42. Reset Control Register 31:29 nvRAM Access Control. This field provides a method for access to the optional external non-volatile memory. loaded in order. Bit 31 of this field acts as a combined enable and ready for the access to the external memory.

0 X X W Inactive

0 X X R Ready

1 X X R Busy

the next read/write operation. this bit will always return a 0, this bit is write only. several PCI idle cycles are inserted following the assertion of this command. this bit is necessary in order to remove the assertion of reset. This bit is read/write. proper read sequence for bits 31 through 29 is performed.

ever side wrote last will update its value. Figure 31. Pass-Thru Configuration Register

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 75 Data Book Table 5 describes one of the four configuration registers. All four region configuration registers are exactly the same. Table 43. Bit Description 7 PTADR# mode. This bit is only valid in Active mode. If this bit is 0 , PTADR# is not driven at the beginning of an active cycle. If this bit is set to 1 (default state), the S5920 will assert PTADR# for one clock cycle after PTATN# is asserted. The Pass-Thru address is also driven while PTADR# is low. This bit is a donÕt care if the device is operating in Passive mode. 6 Endian conversion. If this bit is set to one, the S5920 will convert the Add-On bus from the default little endian format to a big endian format. Reference Chapter 9 for more details. 5 Write FIFO disabled. If this bit is set to 1, the S5920 will not accept the next piece of data (on a PCI write) until the Add-On has accepted the previous piece of data. If this bit is set to 0, the S5920 will accept data from the PCI until the Pass-Thru write FIFO is full. 4:3 Prefetch. These bits control the number of DWORDs the S5920 will prefetch after the current PCI Pass-Thru read completes. The actual amount of data prefetched depends upon any number of different scenarios. The prefetch values of ÒsmallÓ, ÒmediumÓ and ÒlargeÓ are available to tune the system to achieve best overall performance (i.e., optimize PCI bus transfers or optimize Add-On bus transfers). The Pass-Thru read FIFO can be enabled to prefetch in either Active mode or Passive mode. 2:0 Wait states. In Active mode, the user can program the number of wait states required by the Add-On bus to complete a transaction. Up to 7 wait states can be programmed (per region). The S5920 will count the number of clocks programmed into this register before finishing the current data transaction if PTWAIT# is high. If PTWAIT# is driven low, additional wait states may be inserted. Bits 2, 1 and 0 are donÕt care if operating in Passive mode.

Add-On Bus Operation Registers. Table 44. Operation Registers - Add-On Interface

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 77 Data Book ADD-ON INCOMING MAILBOX REGISTER (AIMB) ADD-ON OUTGOING MAILBOX REGISTER (AOMB) ADD-ON PASS-THRU ADDRESS REGISTER (APTA) ADD-ON PASS-THRU DATA REGISTER (APTD) Register Names: Incoming Mailbox This DWORD register provides a method for receiv-ing user-defined status or parameter data from the PCI system. Add-On bus read operations to this register may be of any width (byte, word, or DWORD). Only read operations are sup- ported. Reading from this register can optionally cause a PCI bus interrupt (if desired) by enabling interrupt generation through the use of the PCI’s Interrupt Control/Status Register. This register is also referred to as the PCI Outgoing Mail- box Register. Add-On Address: 0Ch Power-up value: XXXXXXXXh Add-On Attribute: Read Only Size: 32 bits Register Names: Outgoing Mailbox This DWORD register provides a method for sending command or parameter data to the PCI interface. Add-On bus operations to this register may be of any width (byte, word, or DWORD). Writing to this register can be a source for PCI bus interrupts (if desired) by enabling interrupt generation through the use of the PCI’s Interrupt Control/Status Register. This is also called the PCI Incoming Mail box Register (IMB). Byte 3 of this mailbox can also be controlled via the external mailbox port. Reading from this register will not affect interrupts or the AMBEF Status Register. (OMB). Add-On Address: 1Ch Power-up value: XXXXXXXXh Add-On Attribute: Read/Write Size: 32 bits Register Name: Add-On Pass-Thru Address This register stores the address of any active Pass-Thru PCI bus cycle that has been accepted by the S5920. When one of the base address decode registers 1-4 encounters a PCI bus cycle which selects the region defined by it, this register stores that current cycle’s active address. This address is incremented after every 32-bit Pass-Thru data transfer. Add-On Address: 28h Power-up value: XXXXXXXXh Add-On Attribute: Read Only Size: 32 bits Register Name: Add-On Pass-Thru Data This register, along with APTA register, is used to perform Pass-Thru transfers. When one of the base address decode registers 1-4 encounters a PCI bus cycle which selects the region defined by it, the APTA register will contain that current cycle’s active address and the APTD will contain the data (PCI bus writes) or must be written with data (PCI bus reads). Wait states are generated on the PCI bus until this register is read (PCI bus writes) or this register is written (PCI bus reads) when in Passive mode. Add-On Address: 2Ch Power-up value: XXXXXXXXh Add-On Attribute: Read/Write Size: 32 bits

box Empty/Full Status Register (MBEF). Figure 32. Mailbox Empty/Full Status Register

Table 45. Mailbox Empty/Full Status Register

• Incoming mailbox becomes full
• Outgoing mailbox becomes empty
• Built-in self test issued

Figure 33. Add-On Interrupt Control Status Register

Table 46. Interrupt Control Status Register 31:24 Reserved. Always zero. is the OR of the interrupt sources described by bits 20, 17 and 16 of this register. 22:21 Reserved. Always zero. completion codes may be passed to the PCI BIST register by writing to the ARCR register. 19:18 Reserved. Always zero. change the state of this bit. will not change the state of this bit. 15:13 Reserved. Always zero. Add-On interrupt. This bit is read/write. 9:8 Outgoing Mailbox Byte Interrupt Select. This field selects which byte of the mailbox is to cause the interrupt. [00]b selects byte 0, [01]b selects byte 1, [10]b selects byte 2, and [11]b selects byte 3. This field is read/write. produce an Add-On interrupt. This bit is read/write. selects byte 0, 01b selects byte 2, and 11b selects byte 3. This field is read/write.

• Reset mailbox empty full status flags
• Reset Pass-Thru read FIFO
• Read/Write external non-volatile memory

Figure 34. Add-On General Control/Status Register

Table 47. Reset General Control/Status Register 31:29 nvRAM Access Control. This field provides a method for access to the optional external non-volatile memory. loaded in order. Bit 31 of this field acts as a combined enable and ready for the access to the external memory. upon the start of the next read/write operation. this bit will always return a 0, this bit is write only. not performing any Pass-Thru accesses. proper read sequence for bits 31 through 29 is performed. maps with the BIST register bits 3 through 0, respectively.

Figure 35. Pass-Thru Configuration Register

Table 48. Pass-thru Configuration Register format to a big endian format. PCI until the Pass-Thru write FIFO is full. Thru read completes. The actual amount of data prefetched depends upon any number of different scenarios. be enabled to prefetch in either Active mode or Passive mode.

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 86 Data Book INTRODUCTION All PCI bus agents and bridges are required to imple - ment PCI Configuration Regi sters. When multiple PCI devices are present, these registers must be unique to each device in the system. The specified PCI proce - dure for uniquely selecting a device’s configuration space involves a dedicated signal, called IDSEL, con nected to each motherboard PCI bus device and PCI slot. After reset, the host executes configuration cycles to each device on the PCI bus. The configuration regis ters provide information on PCI agent operation and memory or I/O space requirements. These allow the PCI BIOS to enable the device and locate it within sys tem memory or I/O space. After a PCI reset, the S5920 can be configured for a specific application by downloading device setup infor mation from an external non-volatile memory into the device Configuration Registers. In order to use the Pass-Thru regions, the S5920 must be used with an external nvRAM boot device If no nvRAM is used, the Base-Address Regions are disabled. However, the mailboxes and other PCI/Add-on Operation Registers can still be used (as Base -Address Region #0 comes up in its default state, defining a 128-byte I/O region). To configure the S5920, 64 bytes of setup information are required. The rest of the boot device can be used to implement an expansion BIOS, if desired. Some of the setup information is used to initialize the S5920 PCI Configuration Registers, while other information is used to define S5920 special operating modes. PCI RESET Immediately following the as sertion of the PCI RST# signal, the Add-On reset output SYSRST# is asserted. The Add-On reset output (SYSRST#) can be used to initialize external state machines, reset Add-On micro processors, or other Add-On logic devices. All S5920 Operation Registers and Configuration Reg- isters are initialized to their default states at reset. The default values for the Confi guration Registers will be overwritten by the contents of the external nv boot memory during device initia lization. Configuration accesses by the host CPU while the S5920 is loading configuration will produce PCI bus retries until one of the following events occurs:

• The S5920 identifies that there is no valid boot memory (and default Configuration Register values are used).
• The S5920 finishes downloading all configura - tion information from a valid boot memory. LOADING THE SERIAL NV MEMORY Serial nv memory data transfers are performed through a two-wire, bi-directional data transfer protocol as defined by co mmercial serial EEPROM offerings. These devices have the advantages of low pin counts, small package size, and economical price. A serial nv memory is initia lly considered valid if the first serial accesses contain the correct per-byte acknowledgments (see Figure 5). If the serial per-byte acknowledgment is not observed, the S5920 deter mines that no external serial nv memory is present and the AMCC default Config uration Register values specified in the PCI Configuration Register Chapter are used. Please note that the Pass-Thru interface will not operate unless a valid nv memory has been read. The serial nvRAM is first accessed at location 0040h followed by a read to location 0041h. If either of these accesses contain anything other than FFh, the next four accesses are to locations 0050h, 0051h, 0052h and 0053h. At these locations, the data must be 80h (or 81h or 82h), FFh, E8h, and 10h, respectively, for the external nv memory to be considered valid. Once a valid external nv memory has been recognized, it is read, sequentially from location 040h to 07Fh. The data is loaded into the appropriate PCI configuration register. Some of the boot device data is not down loaded into the Configuration Registers, but is used instead to initialize some S5920 modes of operation (location 0045h, for instance). Upon completion of this sequence, the boot load terminates and PCI configu ration accesses to the S5920 are acknowledged with the PCI Target Ready (TRDY#) output. Table 1 lists the required nv memory contents for a valid configuration nv memory device. Two pins are used to transfer data between the S5920 PCI controller and the external serial memory: a serial clock pin, SCL, and a serial data pin, SDA. The serial clock pin is an open drain output from the S5920, and the serial data pin is open drain bi-directional. The serial clock is derived by dividing the PCI bus clock by 293. This means the frequency of the serial clock is approximately 114 KHz for a 33 MHz PCI bus clock. Note in Figure 1, a 4.7k pull-up is required on the SDA and SCL lines. During boot -up, the S5920 will only communicate with an EEPROM that has its address pins set to 0 (A[2:0] = “000). When not accessing the external nvRAM, the S5920 will tri-state the SCL and SDA signals so other two-wi re serial devices can use the bus. The system designer must guarantee that the two-wire serial bus is id le whenever the S5920 wants to start an access. The S5920 does NOT perform two-

respect to the serial clock. transferred approximately every 0.25 milliseconds. Read accesses can be either random or sequential. begin at the 64-byte address offset (40h through 7Fh). Table 49. Valid External Boot Memory Contents

1 Mbytes

value of 82h defines memory space below 1 Mbytes.

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 90 Data Book NON-VOLATILE MEMORY INTERFACE The nv memory, can be accessed through the PCI interface or the Add-On inte rface. Accesses to the nv memory from the PCI interf ace are through the Reset Control Register (RCR). Ac cesses to the nv memory from the Add-On interface are through the Add-On Reset Control Register (ARCR). Some nv memories can contain Expansion ROM BIOS code for use by the host CPU. During initialization, the Expansion BIOS is located within system memory. The starting location of the nv memory is stored in the Expansion ROM Base Address Register in the S5920 PCI Configuration Registers. A PCI read from this region results in the S5920 performing four consecu tive byte-wide access to t he nv memory device, thus assembling a complete DWO RD. Writes to the nv memory are not allowed through the expansion ROM base address region. Any attempt to do so will result in data being accepted by the S5920, but simply discarded. In the RCR and ARCR registers, bits D31:29 are com- mand/status bits and bits D23:16 are address/data bits. These operation registers occupy the same offset (3Ch-3Fh) on their respective interfaces (Add-On or PCI). The sequence used to ac cess the nv memory is the same in either case. nvRAM READ/WRITE DESCRIPTION There are four different mechanisms to access the external nvRAM: 1. During boot-up (RST# deasserted), the S5920 will automatically read out the nvRAM addresses 40h - 7Fh. 2. Via the PCI Configuration Expansion ROM Base Address Register (EXROM). This is READ-ONLY. 3. Via the PCI Reset Control Register (RCR). This is READ/WRITE. 4. Via the Add-On Reset Control Register (ARCR). This is READ/WRITE. The boot-up sequence is a built-in function, and is affected by the contents of the nvRAM. The Expansion ROM Base Address Register is used if expansion BIOS is stored in the external nvRAM. This register can be enabled for a 2K memory size, and is mapped to access the contents of the nvRAM. When a read is performed to an address in the range of the EXROM base address, a read sequence is started to the nvRAM. As this sequence is extremely slow, the PCI will be greeted with a Retry. Mean-while, the nvRAM interface circuitry will be performing four sequential byte accesses to the nvRAM at the offset indicated by the PCI address. For example, if the EXROM Base Address is programmed with 100000h, and the PCI performs a read to address 100040h, this will initiate a read from address 40h of the nvRAM. Once addresses 40h, 41h, 42h and 43h have been read and stored in the nvRAM interface, the S5 920 is ready to provide the data to the original PCI device requesting the data. Once the original master comes back to read the data (which it should, as it rece ived a Retry to its initial read), it will get a TRDY# along with the 4 bytes of data that were read from the nvRAM. If the master comes back to retry the read, but the nvRAM interface is not finished with its a ccesses, the master will again be greeted with a Retry. If a master attempts to read from a different EXROM address, it will also be greeted with a Retry. Only a read with the original address (in our example, a read to address 100040h) will allow the transaction to complete. As a result, if the original master never come s back to Retry the read, the EXROM interface will be hung. Only other EXROM accesses will be hung, as the nvRAM interface will still be operational via the PCI’s RCR and the Add-On’s ARCR. Accesses to the nvRAM via the PCI’s Reset Control Register (RCR) are a bit mo re involved for the pro grammer. There are 12 bits of this register that perform both reads and writes. Bits 23-16 to provide Address/ Data information, bits 31-29 are used to provide con trol information, and bit 28 indicates whether the nvRAM access was successful or not. The control bits 31-29 are assigned as follows (where W/R indicates the type of PCI access to the RCR): These control bits are used along with the Address/ Data bits 23-16 to configure the type of nvRAM opera tion (read or write), the address being accessed, and a place to store the write data or the data read from the nvRAM. One can interface with this register in either byte-wide or word-wide fashion. For a word-wide access, the command (bits 31-29) and Address/Data (bits 23-16) are written to the RCR with one PCI write. For a byte-wide access, the command (bits 31-29) is written first, followed by the Address/Data (bits 23-16). This takes two PCI transfers. D31 D30 D29 W/R nvRAM Interface Function 1 0 0 W Load low address byte 1 0 1 W Load high address byte 1 1 0 W Begin write 1 1 1 W Begin read

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 91 Data Book When performing a byte-wide RCR access, users need to write the command indicating how the data is to be used, followed by the data. These commands will assert the internal signals LOAD_LOW_ADDR, LOAD_HIGH_ADDR or LOAD_WR_DATA. Only one signal is asserted at any ti me: once one is asserted, the others are deasserted. The final read/write interface to the external nvRAM is via the Add-On Reset and Control Register (ARCR). This mechanism is identical to that used for the PCI’s RCR, except that the Add-On interface is used to access the nvRAM via the ARCR. The latency is a bit longer as well, due to the synchronization that must be performed between the Add-On clock and the PCI clock. While on-chip arbitration logic allows simultaneous accesses to the nvRAM via the PCI’s RCR and Add- On’s ARCR (by queuing up the commands), there is no logic to prevent each interface from overwriting nvRAM contents. If an interface writes to a memory location that the other interface has already has writ ten to, the value at that location will be overwritten. What follows are the sequence of steps required to access the nvRAM via the RCR. All the scenarios assume that the RCR is being controlled via PCI bus transactions. By replacing RCR with ARCR in the examples below, the operations are identical for an Add-On device. The following sequence is used to perform nvRAM writes when accessing the RCR/ARCR in a byte- wide fashion: 1. Verify that busy bit, RCR(31), is not set by read - ing RCR(31). If set, hold off starting the write sequence (repeat step 1 until this bit clears). 2. Write to RCR(31:29) = “100”, the command to load the low address byte. This will assert the internal signal LOAD_LOW_ADDR, which is used to enable the loading of the low-address register (NVRAM_LOW_ADDR). 3. Write to RCR(23:16) wi th the low address byte. Since signal LOAD_LOW_ADDR is asserted, the data will be written to register NVRAM_LOW_ADDR. As long as LOAD_LOW_ADDR is asserted, a write to RCR(23:16) will continue to overwrite register NVRAM_LOW_ADDR. 4. Write to RCR(31:29) = “101”, the command to load the high ad dress byte. This will assert the internal signal LOAD_HIGH_ADDR, which is used to enable the loading of the high-address register (NVRAM_HIGH_ADDR). 5. Write to RCR(23:16) with the high address byte. Since signal LOAD_HIGH_ADDR is asserted, the data will be written to register NVRAM_HIGH_ADDR. Note that as the nvRAM address is limited to 11 bits, only the 3 lsbs of this write data is actually used. As long as LOAD_HIGH_ADDR is asserted, a write to RCR(23:16) will continue to ov erwrite register NVRAM_HIGH_ADDR. 6. Write to RCR(31:29) = “000”, a dummy command to deassert either LOAD_LOW_ADDR or LOAD_HIGH_ADDR (whichever occurred last), and to assert internal signal LOAD_WR_DATA. This signal is used to enable the loading of the write data register. LO AD_WR_DATA will remain asserted until another co mmand is issued (load low/high address, begin read/write). As long as LOAD_WR_DATA is asserted, a write to RCR(23:16) will continue to overwrite the write data register. 7. Write to RCR(23:16) the byte to be written. Since the signal LOAD_WR_DATA is asserted, the data will be written to the write data register. 8. Write to RCR(31:29) = “110”, the command to start the nvRAM write operat ion. This will lead to the deassertion of LOAD_WR_DATA and will set the busy bit, RCR(31). The nvRAM interface con- troller will now initiate a write operation with the external nvRAM. 9. Poll the busy bit until it is no longer set. Once cleared, it is now safe to perform another write/ read operation to the external nvRAM. The XFER_FAIL flag (bit 28) can be used to deter mine whether the transfer was successful or not. If XFER_FAIL is asserted, this indicates that a transfer to the nvRAM did not receive an ACKNOWLEDGE, and the write transfer should not be considered successful. This flag remains set until the start of the next read/write operation. The busy bit will remain set until the nvRAM interface has completed writing the da ta byte to the external nvRAM, and has verified that the write sequence is fin- ished. The nvRAM “shuts down” during a write and will not accept any new commands (does not generate an ACKNOWLEDGE) until it finishes the write operation. The S5920 will continue to send commands to the nvRAM until it responds with an ACKNOWLEDGE, after which it clears the busy bit, indicating that the write operation is truly complete. If the busy bit were to be cleared after the nvRAM interface finished the write, but before the external nvRAM was actually fin ished, a scenario exists where a successive write would be ignored. In this case, the software driver

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 92 Data Book could not use the busy bit to determine when to start a new write, but would need to insert a delay (deter - mined by the “shut down” time of the nvRAM, between 5-10 ms). Fortunately, the S5920 implements the Acknowledge Polling scheme described above, which will not take away the busy bit until the write is truly fin ished, and the external nvRAM is available for accesses. The following sequence is used to perform nvRAM writes when accessing the RCR/ARCR in a byte- wide fashion: 1. Verify that busy bit, RCR(31), is not set by read - ing RCR(31). If set, hold off starting the read sequence (repeat step 1 until this bit clears). 2. Write to RCR(31:29) = “100”, the command to load the low address byte. This will assert the internal signal LOAD_LOW_ADDR, which is used to enable the loading of the low-address register (NVRAM_LOW_ADDR). 3. Write to RCR(23:16) wi th the low address byte. Since signal LOAD_LOW_ADDR is asserted, the data will be written to the register NVRAM_LOW_ADDR. As long as LOAD_LOW_ADDR is asserted, a write to RCR(23:16) will continue to overwrite register NVRAM_LOW_ADDR. 4. Write to RCR(31:29) = “101”, the command to load the high ad dress byte. This will assert the internal signal LOAD_HIGH_ADDR, which is used to enable the loading of the high-address register (NVRAM_HIGH_ADDR). 5. Write to RCR(23:16) with the high address byte. Since signal LOAD_HIGH_ADDR is asserted, the data will be written to the register NVRAM_HIGH_ADDR. Note that as the nvRAM address is limited to 11-bits, only the 3-lsb’s of this write data is act ually used. As long as LOAD_HIGH_ADDR is asserted, a write to RCR(23:16) will continue to overwrite register NVRAM_HIGH_ADDR. 6. Write to RCR(31:29) = “111”, the command to start the nvRAM read operation. This will set the busy bit, RCR(31). The nvRAM interface control ler will now initiate a read operation to the external nvRAM. 7. Poll the busy bit until it is no longer set. Once cleared, the read data will be located in RCR(23:16). In addition, evaluate the XFER_FAIL flag (bit 28) to determine whether the transfer was successful or not. If XFER_FAIL is asserted, this indicates that a transfer to the nvRAM did not receive an ACKNOWLEDGE, and the read data in RCR(32:16) may not be valid. This flag remains set until the start of the next read/write operation. When performing a word/double-word RCR access, you can combine the data and control in the same command. The following is the sequence for a write: 1. Verify that busy bit, RCR(31), is not set by read - ing RCR(31). If set, hold off starting the write sequence (repeat step 1 until the bit clears). 2. Write to RCR(31:29) = “100” and RCR(23:16) with the low address byte. This will directly load NVRAM_LOW_ADDR with RCR(23:16). 3. Write to RCR(31:29) = “101” and RCR(23:16) with the high address byte . This will directly load NVRAM_HIGH_ADDR with RCR(23:16). 4. Write to RCR(31:29) = “110” and RCR(23:16) with the write data. This will directly load the write data register with RCR(23:16). This will also set the busy bit, RCR(31). The nvRAM interface con troller will now initiate a write operation to the external nvRAM. 5. Poll the busy bit until it is no longer set. Once cleared, it is now safe to perform another write/ read operation to the external nvRAM. In addi tion, evaluate the XFER_FAIL flag (bit 28) to determine whether the transfer was successful or not. If XFER_FAIL is asserted, this indicates that a transfer to the nvRAM did not receive an ACKNOWLEDGE. The write should not be con sidered successful. This flag remains set until the start of the next read/write operation. The following sequence is used for a read: 1. Verify that the busy bit, RCR(31), is not set by reading RCR(31). If set, hold off starting the read sequence (repeat step 1 until the bit clears). 2. Write to RCR(31:29) = “100” and RCR(23:16) with the low address byte. This will directly load NVRAM_LOW_ADDR with RCR(23:16). 3. Write to RCR(31:29) = “101” and RCR(23:16) with the high address byte . This will directly load NVRAM_HIGH_ADDR with RCR(23:16). 4. Write to RCR(31:29) = “111”. This will set the busy bit, RCR(31). The nvRAM interface control - ler will now initiate a read operation with the external nvRAM. 5. Poll the busy bit until it is no longer set. Once cleared, the read data will be located in RCR(23:16). In addition, evaluate the XFER_FAIL flag (bit 28) to determine whether the

the next read/write operation. equal to 0 and are used to access PCI bus agents. and responds only to a Type 0 configuration accesses. Figure 42. PCI AD Bus Definition Type 0 Configuration Access

• IDSEL high (PCI slot unique signal which iden - tifies access to configuration registers) along with FRAME# low.
• Address bits A0 and A1 are 0 (Identifies a Type 0 configuration access).
• Address bits A8, A9, and A10 are 0 (Function number field of 0 supported).
• Command bits, C/BE[3:0]# must identify a con - figuration cycle command (101X). Figure 8 describes the signal timing relationships for configuration read cycles. Figure 9 describes configu ration write cycles.

Figure 43. Type 0 Configuration Read Cycles

1010 BYTE EN

Figure 44. Type 0 Configuration Write Cycles EXPANSION BIOS ROMS memory used to boot-load the S5920 controller.

1011 BYTE EN

Table 50. PC Compatible Expansion ROM 3h 4 variable Entry point for INIT function.

value for length field at offset 0002h. Table 50. PC Compatible Expansion ROM (Continued)

specification for complete details. Table 51. PCI Data Structure

details are given for target transactions only. case, the initiator is resp onsible for ending the cycle. Table 52. PCI Bus Commands

0000 Interrupt Acknowledge No

0001 Special Cycle No

0010 I/O Read Yes

0011 I/O Write Yes

0100 Reserved No

0101 Reserved No

0110 Memory Read Yes

0111 Memory Write Yes

1000 Reserved No

1001 Reserved No

1010 Configuration Read Yes

1011 Configuration Write Yes

1100 Memory Read Multiple Yes 1

1. Memory Read Multiple and Memory Read Line are executed as a Memory Read.
2. Memory Write and Invalidate is executed as a Memory Write.

menting and 80486 cache line fill sequencing. The S5920 supports only li near burst ordering. disconnect on the PCI bus, as described above. Registers 1-4 may be bursts, if desired. transfers when it is selected as a target. the target can provide valid data for the PCI read. necessarily attempting a burst. Figure 45. Single Data Phase PCI Bus Read of S5920 read attempt is made to an empty Pass-Thru FIFO. interface has not finished reading 4 bytes.

1101 Reserved No

1110 Memory Read Line Yes 1

1111 Memory Write and Invalidate Yes 2

Table 52. PCI Bus Commands (Continued)

request, as shown in Figure 8. Table 53. Target Termination Type Disconnect on on on Data is transferred. Transaction needs to be re-initiated to complete. Retry on on off Data was not transferred. Transaction should be tried later. Abort off on off Data was not transferred. Fatal error.

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 103 Data Book PCI BUS INTERRUPTS The S5920 controller is able to generate PCI bus inter- rupts by asserting the PCI bus interrupt signal (INTA#). INTA# is a multi-sourced, wire-ORed signal on the PCI bus and is driven by an open drain output on the S5920. The assertion and deassertion of INTA# have no fixed timing relationship with respect to the PCI bus clock. Once the S5920 asserts INTA#, it remains asserted until the interrupt source is cleared by a write to the Interrupt Control/Stat us Register (INTCSR). In the case of the external Add-On Interrupt, INTA# will remain set as long as the ADDINT# pin is driven low by an Add-On device(s). Th e source(s) driving ADD INT# must deassert this input before the PCI interrupt (INTA#) is driven to the false state. It is the responsibil- ity host software to clear the Add-On interrupt source before exiting its interrupt handler routine. PCI BUS PARITY ERRORS The PCI specification defines two error-reporting sig - nals, PERR# and SERR#. These signals indicate a parity error condition on th e signals AD[31:0], C/ BE[3:0]#, and PAR. The validity of the PAR signal is delayed one clock period from its corresponding AD[31:0] and C/BE[3:0]# si gnals. Even parity is sup ported by PCI: when the total number of ones in the group of signals AD[31:0] and C/BE[3:0]# is equal to an even number the parity bit will be deasserted. If an odd number of ones is s een, the parity bit will be asserted. PERR# is the error-reporting mechanism for parity errors that occur during the data phase for all but PCI Special Cycle commands. SER R# is the error-report ing mechanism for parity erro rs that occur during the address phase. The timing diagram in Figure 9 shows the timing rela - tionships between the signal s AD[31:0], C/BE[3:0]#, PAR, PERR# and SERR#. The S5920 asserts SERR# if it detects odd parity dur - ing an address phase, if enabled. The SERR# enable bit is bit 8 in the S5920 PCI Command Register (PCICMD). The odd parity error condition involves the state of signals AD[31:0] and C/BE[3:0]# when FRAME# is first asserted and the PAR signal during the following clock. If an erro r is detected, the S5920 asserts SERR# on the following (after PAR valid) clock. Since many targets may observe an error on an address phase, the SERR# signal is an open-drain multi-sourced, wire-ORed signal on the PCI bus. The S5920 drives SERR# low fo r one clock period when an address phase error is detected. Once an SERR# error is detected by the S5920, the PCI Status register bit 14, System Error, is set and remains set until cleared through software or a hardware reset. The PERR# signal is simila r to the SERR# with two differences: it reports errors for the data phase and is only asserted by the device receiving the data. The S5920 drives this signal (removed from tri-state) when it is the selected target for write transactions. The par ity error conditions are only reflected by the PERR# pin if the Parity Error Enable bit (bit 6) of the PCI Com mand Register is set. Upon the detection of a data parity error, the Detected Parity Error bit (bit 15) of the PCI Status Register is set (PCISTS). Unlike the PERR# signal pin, this Status bit is set regardless of the state of the PCI Comm and Register's Parity Error Enable bit. The assertion of PERR# occurs two clock periods fol - lowing the data transfer. This two-clock delay occurs because the PAR signal doe s not become valid until the clock following the transfer, and an additional clock is provided to generate and assert PERR# once an error is detected. PERR# is only asserted for one clock cycle for each error sensed. The S5920 only qualifies the parity error det ection during the actual data transfer portion of a data phase (when both IRDY# and TRDY# are asserted).

Figure 56. Add-On to PCI Mailbox Register become full (and which status bits are set). bits for the incoming mailbox on the other interface. specific mailbox is selecte d to generate the interrupt. tions defined for the Add-On interface.

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 107 Data Book PCI incoming mailbox inte rrupts, the S5920 asserts the PCI interrupt, INTA#. For Add-On incoming mail - box interrupts, the S5920 asserts the Add-On interrupt, IRQ#. For the outgoing mailbox interrupts, when the speci - fied byte becomes empty, an interrupt is generated. The interrupt might be used to indicate that the other interface has received the last information sent and more may be written. For PCI outgoing mailbox inter rupts, the S5920 asserts the PCI interrupt, INTA#. For Add-On outgoing mailbox interrupts, the S5920 asserts the Add-On interrupt, IRQ#. Add-On Outgoing Mailbox, Byte 3 Access PCI incoming mailbox byte 3 (Add-On outgoing mail - box, byte 3, or AOMB[3]) has been further enhanced by the addition of a separate 8-bit interface (MD[7:0]) on the Add-On side. This interface can be used to write to AOMB[3] instead of/or in addition to the nor mal method (via an Add-On Operation Register write to AOMB[3]). The MD[7:0] bus can be configured in one of two modes: Input mode or I/O mode. If the configuration pin MDMODE is strapped high, the MD[7:0] bus is set to be in input mode only. If MDMODE is strapped low, the MD[7:0] bus will operate in a bi-directional mode. If the MD[7:0] bus is set up for input-only mode, data will be latched into AOMB[3] when the LOAD# input is sampled low by the Add-On clock. The LOAD# input pin may also be used to generate a PCI interrupt if the appropriate interrupt is enabled in the Interrupt Con trol/Status Register (INTCSR). These functions are identical to the Add-On device writing to its byte 3 out going mailbox via the DQ bus. As a matter of fact, Add-On mailbox byte 3 is accessible by either the external mailbox port or the Add-On interface. Which ever interface writes to it last will determine the data that resides in that register. When the MD[7:0] bus is set up for I/O mode and LOAD# is high (deasserted), the MD[7:0] bus is an active output, driving the contents of the PCI outgoing mailbox, byte 3 (OMB[3]). In this case, the MD[7:0] bus will be updated anytime the PCI writes to mailbox OMB[3]. As a result, the MD [7:0] bus will be synchro nous to the PCI clock. When LOAD# is driven low, the MD[7:0] bus is tri-stated, allo wing external data to be latched into Add-On outgoing mailbox byte 3. This is a similar function that exists for input-only. Figures 3 and 4 show the interaction between the MD[7:0] bus and the LOAD# input pin. Note that a turnaround cycle is utilized when writing data to the mailbox byte in I/O mode. This is to prevent contention on the MD[7:0] drivers. BUS INTERFACE The mailboxes appear on the Add-On and PCI bus interfaces as two operation registers. One is the out going mailbox, and the other is the incoming mailbox. These mailboxes may be used to generate interrupts to each of the interface s. The following sections describe the Add-On and PCI bus interfaces for the mailbox registers. PCI Bus Interface The mailbox operation registers do not support burst accesses by an initiator. A PCI initiator attempting to burst to the mailbox regi sters causes the S5920 to respond with a target disconnect with data. PCI writes to a full outgoing mailbox overwrite data currently in that mailbox. PCI reads from an empty incoming mail box return the data that was previously contained in the mailbox. In this case, the data cannot be guaran - teed. It is intended for the user to verify that a mailbox is full before it is read. PCI incoming and outgoing mailbox interrupts are enabled/disabled in the INTCSR. The mailboxes can generate a PCI interrupt (INTA#) under two conditions (individually enabled). For an incoming mailbox full interrupt, INTA# is asserted on the rising edge of the PCI clock after the Add-On mailbox write completes. For an outgoing mailbox empty interrupt, INTA# is asserted on the rising edge of the PCI clock after the Add-On mailbox read completes. INTA# is deasserted one PCI clock cycle after th e mailbox interrupt is ser viced (by writing a 1 to the proper interrupt source bit). Add-On Bus Interface The Add-On mailbox interface behaves similarly to the PCI bus interface. Add-On writes to a full outgoing mailbox overwrite data currently in that mailbox. PCI reads from an empty incoming mailbox return the data that was previously contained in the mailbox. Signal Pin Add-On Outgoing Mailbox MD0 Mailbox,Bit 24 MD1 Mailbox, Bit 25 MD2 Mailbox, Bit 26 MD3 Mailbox, Bit 27 MD4 Mailbox, Bit 28 MD5 Mailbox,Bit 29 MD6 Mailbox, Bit 30 MD7 Mailbox, Bit 31

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 109 Data Book Reading the PCI Incoming Mailbox: 1. Check Mailbox Status. Read the mailbox status register to determine if any information has been passed from the Add-On interface. 2. Read Mailbox. Read the mailbox bytes which MBEF indicate s are full. This automatically resets the status bits in the MBEF and AMBEF registers. Writing the PCI Outgoing Mailbox: 1. Check Mailbox Status. Read the mailbox status register to determine if information previously written to the mailbox has been read by the Add-On interface. Writes to full mailbox bytes overwrite data currently in the mailbox (if not already read by the Add-On interface). Repeat until the byte(s) to be written are empty. 2. Write Mailbox. Write to th e outgoing mailbox byte(s). Mailbox operations for the Add-On in terface are functionally identical. The following sequences are suggested for Add-On mailbox operations using status polling (interrupts disabled): Reading an Add-On Incoming Mailbox: 1. Check Mailbox Status. Read the mailbox status register to determine if any information has been passed from the PCI interface. 2. Read Mailbox. Read the mailbox bytes which AMBEF indi cates are full. This automat ically resets the status bits in the AMBEF and MBEF registers. Writing an Add-On Outgoing Mailbox: 1. Check Mailbox Status. Read the mailbox status register to determine if information previously written to the mailbox has been read by the PCI interface. Writes to full mailbox bytes overwrite data currently in the mailbox (if not already read by the PCI interface). Repeat until the byte(s) to be written are empty. 2. Write Mailbox. Write to th e outgoing mailbox byte(s). MBEF Bits 31:28 If a bit is set, valid data is contained in the corresponding mailbox byte. IMB Bits 31:0 Mailbox data. MBEF Bits 15:12 If a bit is set, valid data is contained in the corresponding mailbox byte and has not been read by the Add-On. OMB Bits 31:0 Mailbox data. AMBEF Bits 15:12 If a bit is set, valid data is contained in the corresponding mailbox byte. AIMB Bits 31:0 Mailbox data. AMBEF Bits 31:28 If a bit is set, valid data is contained in corresponding mailbox byte and has not been read by the PCI bus. AOMB Bits 31:0 Mailbox data.

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 110 Data Book Mailbox Interrupts Although polling status is useful in some cases, polling requires continuous actions by the processor. Mailbox inter- rupt capabilities are provided to avoid much of the processor overhead required by continuously polling status bits. The Add-On and PCI interface can each generate interrupts on the incoming mailbox condition and/or the outgoing mailbox condition. These can be individual enabled/disabled. A specific byte in the incoming mailbox and outgoing mailbox is identified to generate the interrupt(s). The tasks required to setup the mailbox interrupts are as follows: Enabling PCI mailbox interrupts: 1. Enable PCI outgoing mailbox interrupts. A specific byte within the outgoing mailboxes is identified to assert INTA# when read by the Add-On interface. 2. Enable PCI incoming mailbox interrupts. A specific byte within the incoming mailboxes is identified to assert INTA# when written by the Add-On interface. Enabling Add-On mailbox interrupts: 1. Enable Add-On outgoing mailbox interrupts. A specific byte within the outgoing mailboxes is identified to assert IRQ# when read by the PCI interface. 2. Enable Add-On incoming ma ilbox interrupts. A specific b yte within the incoming ma ilboxes is identified to assert IRQ# when written by the PCI interface. With either the Add-On or PCI interface, these two steps can be performed with a single access to the appropriate register. They are shown separately here for clarity. Once interrupts are enabled, the interrupt service rout ine must access the mailboxes and clear the interrupt source. A particular application may not require all of th e steps shown. For instance, a design may only use the incoming mailbox interrupts and not require support for the outgoing mailbox interrupts. The interrupt service rou - tine tasks are as follows: INTCSR Bit 4 Enable outgoing mailbox interrupts INTCSR Bits 1:0 Identify mailbox byte to generate interrupt INTCSR Bit 12 Enable incoming mailbox interrupts INTCSR Bits 9:8 Identify mailbox byte to generate interrupt AINT Bit 12 Enable outgoing mailbox interrupts AINT Bits 9:8 Identify mailbox byte to generate interrupt AINT Bit 4 Enable incoming mailbox interrupts AINT Bits 1:0 Identify mailbox byte to generate interrupt

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 111 Data Book Servicing a PCI Mailbox Interrupt (INTA# asserted): 1. Identify the interrupt source(s). Multiple interrupt so urces are available on the S5920. The interrupt service routine must verify that a mailbox generated the interrupt (and not some other interrupt source). 2. Check mailbox status. The mailbox status bits indi cate which mailbox bytes must be read or written. 3. Access the mailbox. Based on the contents of MBEF, mailboxes are read or written. Reading an incoming mailbox byte clears the corresponding status bit in MBEF. 4. Clear the interrupt source. The PCI INTA# signal is dea sserted by clearing the interrupt request. The request is cleared by writing a 1 to the appropriate bit. Servicing the Add-On mailbox interrupt (IRQ# asserted): 1. Identify the interrupt source(s). Multiple interrupt so urces are available on the S5920. The interrupt service routine must verify that a mailbox generated the interrupt (and not some other interrupt source). 2. Check mailbox status. The mailbox status bits indi cate which mailbox bytes must be read or written. 3. Access the mailbox. Based on the contents of AMBEF, ma ilboxes are read or written. Reading the incoming mailbox byte clears the corresponding status bit in AMBEF. INTCSR Bit 23 PCI interrupt asserted INTCSR Bit 17 PCI incoming mailbox interrupt indicator INTCSR Bit 16 PCI outgoing mailbox interrupt indicator MBEF Bits 31:28 Full PCI incoming mailbox bytes MBEF Bits 15:12 Empty PCI outgoing mailbox bytes OMB Bits 31:0 PCI outgoing mailboxes IMB Bits 31:0 PCI incoming mailboxes INTCSR Bit 17 Clear PCI incoming mailbox interrupt INTCSR Bit 16 Clear PCI outgoing mailbox interrupt AINT Bit 23 Add-On interrupt asserted AINT Bit 17 Add-On outgoing mailbox interrupt indicator AINT Bit 16 Add-On incoming mailbox interrupt indicator AMBEF Bits 31:28 Empty Add-On outgoing mailbox bytes AMBEF Bits 15:12 Full Add-On incoming mailbox bytes AIMB Bits 31:0 Add-On incoming mailbox AOMB Bits 31:0 Add-On outgoing mailbox

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 112 Data Book 4. Clear the interrupt source. The Add-On IRQ# signal is deasserted by clearing the interrupt request. The request is cleared by writing a 1 to the appropriate bit. NOTE: For an incoming mailbox interrupt, step 3 involves accessing the mail box. To allow the incoming mailbox interrupt logic to be cleared, the mailbox status bit mu st also be cleared. Reading an incoming mailbox clears the status bits. Another option for cleari ng the status bits is to use the Ma ilbox Flag Reset bit in the RCR and ARCR registers, but this clears all status bits, not just a single mailbox byte. For outgoing mailbox interrupts, the status bit was already cleared prior to the generation of the interrupt. As a result, the mailbox does not need to be read. AINT Bit 17 Clear Add-On outgoing mailbox interrupt AINT Bit 16 Clear Add-On incoming mailbox interrupt

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 113 Data Book ADD-ON LOCAL BUS INTERFACE This chapter describes the Add-On Local bus interface of the S5920. The S5920 is designed to support con - nection to a variety of mi croprocessor buses and/or peripheral devices. The Add-On interface controls S5920 operation through the Add-On Operation Reg isters accessed through the 32 bit local bus. The Add-On local bus interface is synchronous to ADCLK. ADCLK is a 0-40 MH z clock input which can be configured as asynchrono us to the PCI clock or synchronous when connected to the S5920 BPCLK output. The following secti ons describe the various interfaces to the PCI bus and how they are accessed from the Add-On bus. ADD-ON INTERFACE SIGNALS The Add-On bus provides a number of system signals to allow Add-On logic to mo nitor PCI bus activity, to indicate status conditions (interrupts), and to configure the S5920 Add-On bus. SYSTEM SIGNALS BPCLK is a buffered version of the PCI clock. The PCI clock can operate from 0 MHz to 33 MHz. SYSRST# is a buffered version of the PCI reset signal, and may also be toggled by host application software through bit 24 of the Reset Control Register (RCR). IRQ# is the PCI interrupt request output to the Add-On bus. This signal is active low and can indicate multiple conditions. Add-On interrupts can be generated from the mailbox interface or to indicate start of BIST. The conditions which will generate an IRQ# due to mailbox activity are discussed in the mailbox chapter. The IRQ# output is deasserted when acknowledged by writing a 1 to the corresponding interrupt bit in the Add-On Interrupt Control/St atus Register (AINT). See Table 3. The PTMODE signal (Pass-Thru Mode) controls the Pass-Thru interface only. Asserting it will configure the Pass-Thru in Passive mode and low will configure the Pass-Thru in Active mode. ADDINT# is an Add-On in terrupt input pin. When asserted, it will cause the PCI interrupt output pin (INTA#) to assert. The ADDINT# is a level-sensitive input. Any number of Add-On peripheral interrupt sources can drive this inpu t. There must be a pull-up resistor on the board to pull it high when inactive. This interrupt has to be enabled by Bit 13 of the INTCSR. It is the responsibility of the PCI host to clear the inter rupt source of ADDINT# in order to have the pending interrupt deasserted. The DQMODE signal configures the data path width for all Add-On Operation register accesses, except for the Pass-Thru Data and Address registers. When DQMODE is low, DQ is configured as a 32-bit data bus. When DQMODE is high, DQ is configured as a 16-bit data bus. For 16-bit operation, BE3# is rede fined as ADR1, providing an extra address input, and BE2# is unused. ADR1 selects the low or high words of the 32-bit S5920 Add-On Operation Registers. ADD-ON S5920 REGISTER ACCESSES The S5920 Add-On bus is very similar to that of a memory or peripheral device found in a microproces sor-based system. A 32-bit data bus with individual read and write strobes, a chip select and byte enables are provided. Register Access Signals Register accesses to the S5920 Add-On Operation Registers are synchronous to the Add-On input clock (ADCLK). The following signals are required to com plete a register access to the S5920. BE[3:0]# Byte Enable Inputs. These signals identify which bytes of the DQ bu s are valid during Add- On bus transactions. BE0# indicates valid DQ[7:0], BE1# a valid DQ[15:8], etc. When DQ is configured for 16-bit operation, BE2# is not defined and BE3# becomes ADR1. ADR[6:2] Address Register Inputs. These pins address a specific Add-On Operation Register within the S5920. When DQ is configured for 16- bit operation, an additional input, ADR1 is avail able to allow the 32-bit operation registers to be accessed in two 16-bit cycles. RD# Read Enable Input. WR# Write Enable Input. SELECT# Chip Select Input. This input indicates RD#, WR#, ADR[6:2] and BE[3:0] are valid. DQ[31:0] Bi-directional Data Bus. These I/O pins are the Add-On data bus. S5920 General Register Accesses For many Add-On applications, Add-On logic does not operate at the PCI bus frequency. This is especially true for Add-On designs implementing a microproces sor, which may be operating at a lower or higher frequency. The RD# and WR# inputs become enables, using ADCLK to clock data into and out of registers. All inputs are sampled on the rising edge of ADCLK.

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 116 Data Book MAILBOX OVERVIEW For a detailed description of the Mailbox interface, ref- erence Chapter 8. PASS-THRU OVERVIEW The S5920 provides data transfers between the PCI bus and the user local bus through the Pass-Thru data channel. Using a handshaking protocol with Add-On device(s), the PCI bus can directly access data on the Add-On bus and internal S5920 Operation registers. The Pass-Thru data channel is very flexible for user memory access or accessing registers within peripher als on the Add-On bus. Pass-Thru operation in Active or Passive mode requires an external non-volatile memory device to define and configure the Pass-Thru channel region sizes and bus widths. Four user-configurable Pass-Thru regions are avail - able in the S5920. Each region is defined by a PCI Configuration Base Address Register (BADR1-4). A Pass-Thru region defines a block of predefined user space address in either host memory or I/O areas. Memory mapped regions can be requested below 1 Mbyte (Real Mode address space for a PC). Each region is configurable for bus widths of 8, 16 or 32 bits for the Add-On bus interface. The S5920 Pass-Thru channel supports single data transfers as well as burst transfers. When accessed with burst transfers, the S5920 supports data transfers at the full PCI bandwidth. The data transfer rate is only limited by the PCI initiator performing the access and the speed of the Add-On bus logic. WRITE FIFO OVERVIEW For PCI write cycles, the S5920 has an 8x32-bit Write FIFO to increase performance for slow Add-On devices. When the FIFO is enabled, the S5920 will accept data transfers from the PCI bus at zero wait states until the FIFO is full. The device continues to fill the FIFO as long as the transfers are sequential. The S5920 can continue accept ing sequential write PCI transfers as long as the FIFO is not full and the bound ary of the Pass-Thru r egion defined by the Base Address Register is not crossed. If the next data access is for a non-sequential address, the FIFO must first be emptied by the Add-On peripheral in order for the next transfer to occur. The Write FIFO can be disabled, thus configuring the FIFO to act as a single DWORD data buffer. In this case, PCI Write Posting is not possible. READ FIFO OVERVIEW The S5920 has an 8x32-bit Read FIFO, which allows data to be prefetched from the add on bus. The user can program the device to prefetch 2,4 or 8 DWORDs for each region or disable prefetching completely. For the first PCI read cycle, the device will request data from the Add-On bus. As the PCI bus reads the FIFO, and until after the PCI transfer has finished, the S5920 will prefetch the next N (2, 4 or 8) DWORDs from the Add-On. The prefetched data is valid as long as the PCI read addresses are sequential. If the current PCI read address is not the previous address plus four, or if a PCI write access occu rs, the S5920 will flush the FIFO and start a new transfer at this address. Flushing the FIFO will incur a minimu m loss of one PCI clock cycle or possibly more if t he Add-On logic has not fin ished its current prefetching transfer. Note that prefetching is not performed past the upper limit of the base address region. In fact, prefetching is disabled when the PCI address is eight DWORDs from the end of the region. Prefetch cycles are always 32 bits regardless of Add- On bus width or the byte enables requested by the PCI. FUNCTIONAL DESCRIPTION The S5920 Pass-Thru interface supports both single cycle (one data phase) and burst accesses (multiple data phases). Pass-Thru Transfers The Pass-Thru interface offers two different modes of operation: Passive mode and Active mode. Passive mode is configured by strapping the pin PTMODE high, while Active mode is configured by strapping the pin PTMODE Low. PTMODE = 1 - Passive Operation PTMODE = 0 - Active Operation Passive operation allows external Add-On bus periph- erals to provide read and wr ite control signals to the S5920. The user drives SELECT#, RD#, WR#. ADR[6:2] and PTRDY#. The Add-On bus logic has the flexibility of determining when it wants to perform reads/writes. Some applications may requi re that a PCI address be passed for Pass-Thru acce sses. For example, a 4- Kbyte Pass-Thru region on the PCI bus may corre - spond to a 4-Kbyte block of SRAM on the Add-On card. If a PCI initiator accesses this region, the Add- On would need to know th e offset within the memory device to access. The Pa ss-Thru Address Register (APTA) allows Add-On logi c to access address infor

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 117 Data Book mation for the current PCI cycle. When the PCI bus performs burst accesses, the APTA register is incre - mented by the S5920 to reflect the address of the current data phase. PTNUM[1 :0] is used to determine what region owns the current data access. For PCI writes to the Ad d-On, the S5920 transfers data from the PCI bus into the Pass-Thru Write FIFO. When the Pass-Thru write FIFO becomes not empty, the S5920 asserts the Pass-Thru status signals to indi cate to the Add-On that data is present. The Add-On logic will then read data from the FIFO. The S5920 continues accepting write data from the PCI initiator as long as the 8x32 FIFO is not full. For PCI reads from the Add-On, the S5920 asserts the Pass-Thru status signals to indicate to the Add-On that data is required. The Add-On logic should write the requested data into the Pass-Thru Read FIFO. The S5920 will assert TRDY# to the PCI bus after the Add- On logic has transferred data into the FIFO. As long as data is in the FIFO, a nd PCI read data is still requested, TRDY# will continue to be asserted. If the Add-On cannot provide data quickly enough, the S5920 signals a disconnect to the PCI bus. This allows the PCI bus to perform other tasks, rather than waiting for a slow target. T he S5920 will prefetch data if enabled. Pass-Thru Status/Control Signals The S5920 Pass-Thru regi sters are accessed using the Add-On register access pins. The Pass-Thru Address Register (APTA) can, optionally, be accessed using a single, direct access input, PTADR#. Pass- Thru cycle status indicators are provided to control Add-On logic based on the typ e of Pass-Thru access occurring (single cycle, burst, etc.). The signals in the table above are provided for Pass-Thru operation: BUS INTERFACE The Pass-Thru data channel allows PCI initiators to read or write to resources on the Add-On bus. A PCI initiator may access the Ad d-On with single data phase cycles or multiple da ta phase bursts. The Add- On interface implements Pass-Thru status and control signals used by logic to complete data transfers initi ated by the PCI bus. The Pass-Thru interface is designed to allow Add-On lo gic to function without knowledge of PCI bus activity. Add-On logic only needs to react to the Pass-Thru status signals. The S5920 PCI device independently interacts with the PCI initiator to control data flow between the devices. The following sections describe the PCI and Add-On bus interfaces. The PCI inte rface description provides a basic overview of how the S5920 interacts with the PCI bus, and may be useful in system debugging. The Add-On interface descripti on indicates functions required by Add-On logic and details the Pass-Thru handshaking protocol. PCI Bus Interface The S5920 device examines all PCI bus cycle addresses. If the address as sociated with the current Signal Function PTATN# This output indicates a Pass-Thru access needs servicing. PTBURST# This output indicates that the current Pass-Thru access is a PCI burst transfer or a single cycle transfer. PTBURST# is deasserted immediately after the second to last burst data has been transferred on the PCI side. PTBURST# is also active during prefetch cycles. PTNUM[1:0] These outputs indicate which Pass-Thru region decoded the PCI address. PTBE[3:0]# These outputs indicate which data bytes are valid (PCI writes), or requested (PCI reads). See timing dia- grams for further details. PTBE0# = 0 Byte 0 is valid, PTBE1# = 0 Byte 1 is valid, PTBE# = 0 Byte 2 is valid, PTBE3# = 0 Byte 3 is valid. PTWR This output indicates if the Pass-Thru access is a PCI read or a write. PTADR# When asserted, this pin drives the Pass-Thru Address Register contents onto the Add-On data bus. This input enables the DQ[31:0] data bus to become active immediately. There is NO pipeline delay from PTADR# to DQ, as there is from RD# to DQ. As result, this is an asychronous input. PTRDY# In Passive mode, this input indicates the current Pass-Thru transfer has been has been completed by the Add-On. In Active mode, this input indicates that wait states are to be inserted for the next transfer. ADCLK Input Add-On clock (to synchronize Pass-Thru data register accesses).

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 118 Data Book cycle decodes to one of the S5920 Pass-Thru regions, DEVSEL# is asserted. If t he Pass-Thru logic is cur - rently idle (not busy finishing a previous Pass-Thru operation), the bus cycle type is decoded and the Add- On Pass-Thru status outputs are set to initiate a trans- fer on the Add-On bus. The following sections describe the behavior of the PCI interface for Pass- Thru accesses to the S5920. Single cycle accesses, burst accesses, and target-initiated retries are detailed. PCI Pass-Thru Single Cycle Accesses A single cycle transfer is the simplest of PCI bus trans- actions. Single cycle transfers have an address phase and a single data phase. The PCI bus transaction starts when an initiator drives address and command information onto the PCI bus and asserts FRAME#. The initiator always deasserts FRAME# before the last data phase. For single cycle transfers, FRAME# is only asserted during the address phase (indicating the first data phase is also the last). When the S5920 sees FRAM E# asserted, it samples the address and command information to determine if the bus transaction is intend ed for it. If the address is within one of the defined Pass-Thru regions or internal PCI Operation Register, the S5920 accepts the trans fer (asserts DEVSEL#), and stores the PCI address in the Pass-Thru Address Register (APTA). For Pass-Thru writes, the S5920 responds immedi - ately (asserting TRDY#) and transfers the data from the PCI bus into the write FIFO as long as the write FIFO is not full. The S5920 then indicates to the Add- On interface that a Pass-Thru write is taking place and waits for Add-On logic to complete the transfer. Once the S5920 has captured the data from the PCI bus, the transfer is finished from the PCI bus perspective, and the PCI bus becomes available for other transfers. For Pass-Thru reads, the S5920 indicates to the Add- On interface that a Pass-Thru read is taking place and waits for Add-On logic to complete the cycle. If the Add-On cannot complete the cycle quickly enough, the S5920 requests a retry from the initiator. The S5920 will fetch one DWORD from the Add-On side, and store it in the Read FIFO. PCI Pass-Thru Burst Accesses For PCI Pass-Thru burst accesses, the S5920 cap - tures the PCI address and determines if it falls into one of the defined Pass-Thru r egions. Accesses that fall into a Pass-Thru region or internal PCI Operation Reg ister are accepted by asserting DEVSEL#. The S5920 monitors FRAME# and IRDY# on the PCI bus to iden - tify burst accesses. If the PC I initiator is performing a burst access, the Pass-Thru status indicators notify the Add-On logic. For Pass-Thru burst writes, the S5920 responds immediately (asserting TRDY#). The S5920 transfers the first data phase of the burst into the FIFO, and stores the PCI address in the Pass-Thru Address Reg ister (APTA). The S5920 can accept up to 8 DWORDs from the PCI bus before tr ansferring one DWORD on the Add-On side. If the Add-On bus is slow, the device will keep the FIFO full until the data is ready to be transferred by the slow Add-On bus. If the Add-On bus is fast at accepting the da ta, then the FIFO will con tinue an indefinite burst, or until the PCI master is forced to relinquish the bus for arbitration reasons, or the PCI bus master has gone beyond the Pass-Thru region address space. For burst accesses, the APTA is automatically incremente d by the S5920 for each data phase. For Pass-Thru burst reads, the S5920 claims the PCI cycle (asserting DEVSEL#). The request for data is passed on to Add-On logic and the PCI address is stored in the APTA register. The device will prefetch data if the feature is enabled. The S5920 then drives the requested data on the PCI bus and asserts TRDY# to begin the next data phase. The APTA register is automatically incremented by the S5920 after each data phase. PCI Disconnect Conditions Before discussing what causes the S5920 to issue a disconnect on the PCI bus, it might be useful to distin guish between a disconnect an d retry. A retry occurs when a PCI initiator does not receive a single TRDY#, but is issued a STOP# instead. In this case, no data is transferred. The PCI 2.1 spec states that the initiator is required to come back and complete this transfer. A disconnect occurs after at least one data phase was completed (TRDY# and IRDY# asserted simulta neously). This occurs when a STOP# is asserted either with a TRDY# or after a TRDY#/IRDY# transfer. In this case, the initiator is not required to return to complete the transfer. In some applications, Add-On logic may not be able to respond to Pass-Thru accesse s quickly. In this situa - tion, the S5920 will Retry t he cycle on the PCI side. For PCI write cycle s, the S5920 will accept up to 8 DWORDs without a disconnect or until the FIFO is full. For a PCI read cycle, the fi rst access needs to take less than 16 PCI clocks, ot herwise the device will issue a Retry. A subsequent read transfer must take less than 8 PCI clocks, otherwise the device will issue a disconnect.

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 119 Data Book With many devices, particul arly memories, the first access takes longer than subsequent accesses (assuming they are sequential and not random). For this reason, the PCI specif ication allows 16 clocks to respond to the first data phase of a PCI cycle and 8 clocks for subsequent data phases (in the case of a burst) before a retry/disc onnect is issued by the S5920. The S5920 also requests a disconnect if an initiator attempts to burst past the end of a Pass-Thru region. The S5920 updates the Pass-Thru Address Register (APTA) for each data phase during bursts, and if the updated address is not with in the current Pass-Thru region, a disconnect is iss ued. Accesses to undefined addresses will cause the PCI host to receive a Master Abort cycle (no DEVSEL# is asserted by the S5920). For example, a PCI system may map a 512 byte Pass- Thru memory region to 0DC000h to 0DC1FFh. A PCI initiator attempts a four DW ORD burst with a starting address of 0DC1F8h. The first and second data phases complete (filling the DWORDs at 0DC1F8h and 0DC1FCh), but the third data phase causes the S5920 to issue a disconnect. This forces the initiator to present the address 0DC200h on the PCI bus. If this address is part of another S5920 Pass-Thru region, the device accepts the acce ss, but if not, a Master Abort cycle occurs. PCI Write Disconnect When the S5920 issues a disconnect for a PCI Pass- Thru write, it indicates that the Add-On is still complet ing a previous non-sequential Pass-Thru access or the FIFO is full. If the incoming access is a continuation of a previous one, no disconnect is issued and the trans action can continue where it left off (perhaps due to a previous disconnect or master time-out). PCI Opera tion Registers may be accessed while the Add-On is still completing a Pass-Thru access. Only Pass-Thru region accesses receive disconnect requests. PCI Read Disconnect If the S5920 issues a disconnect for a PCI Pass-Thru read, this indicates that the Add-On could not com - plete the read in th e required time (16 clocks for the first data phase, 8 PCI clocks for the 2nd or later data phases). When the PCI performs a re ad to a Pass-Thru region, the Add-On device must complete a Pass-Thru data transfer by writing the appropriate data into the Pass- Thru Data FIFO (APTD). If the Add-On can perform this before the required time (see above), the S5920 asserts TRDY# to complete a PCI read transfer. If the Add-On cannot complete th e access within 16 clocks, a retry is requested (STOP# asserted without data transfer). If the Add-On manages to complete the data transfer into the PT Read FIFO, but after a retry was issued, the data is held in the FIFO until the original master comes back to read it. All subsequent PCI accesses to a Pass-Thru ad dress other than the one corresponding to the data in the FIFO will be termi nated with a PCI retry. On ly a PCI access with a matching address can access the data in the PT Read FIFO, and thus release the Pass-Thru region for other accesses. If the Add-On is busy performing a Pass-Thru write operation when a PCI read occurs, the S5920 requests an immediate retry. If the Add-On is busy per forming a Pass-Thru read operation when another PCI read occurs, the S5920 determines whether the read is a retry from a previous access, and if so, attempts to continue the read where it left off. If the address is non-sequential, the new access is issued a retry. This allows the PCI bus to perform other operations. S5920 PCI Operation Registers ma y be accessed while the Add-On is still completing a Pass-Thru access. Only other Pass-Thru region accesses receive retry requests. If the prefetch feature is enabled, the Pass-Thru inter - face will prefetch data, which should improve the performance on subsequent cycles to the same region. In the event that the Add-On cannot prefetch the first data before the S 5920 issues a PCI retry, the prefetched data will be held in the read FIFO until the original master co mes back to request it. Other PCI read requests to the Pass-Thru region will be termi nated with immediate Retries. If the prefetch feature is di sabled, a PCI read cycle is not completed until the data is first transferred from the Add-On bus into the PT Read FIFO. The device will not prefetch, but will only request data from the Add- On bus after the PCI bus has requested the data. Pass-Thru bursts will not be performed in this case. In the event that a non-prefetchable Add-On cannot pro vide the second (or third, or fourth...) data to the PCI read request within the PCI Target Subsequent Latency period (eight PCI clocks), the S5920 will issue a PCI disconnect (STOP# asserted with data transfer). If the Add-On manages to transfer the second (or third, or fourth...) data to the PT Read FIFO, but after the disconnect, the data may be held in the FIFO until the original master comes back to read it. Depending upon the setting of the Retry Flush Enb bit, the data is held in the FIFO, and all other PCI read requests will be terminated with immediate Retries.

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 124 Data Book Clock 3: The Add-On latches the address. Data 1 is driven on the DQ bus as a re sult of the previous read. As PTRDY# is sampled asserted, the PTBE# outputs are updated to indicate which bytes are valid for the second transfer. The BE[3:0]#, ADR[6:2], and SELECT# inputs remain driven along with RD# to read out the next data. PTRDY# remains asserted, indicat ing that the second transfer is complete. Clock 4: Add-On logic uses the rising edge of this clock to store DATA1. DATA2 is driven on the DQ bus as a result of the previous read. As PTRDY# is sam pled asserted, the PTBE# outputs are updated to indicate which bytes are va lid for the third transfer. PTRDY# remains asserted, in dicating that the third transfer is complete. Clock 5: Add-On logic uses the rising edge of this clock to store DATA2. PTBURST# is deasserted indi - cating that only a single data phase remains. DATA3 is driven on the Add-On bus . The PTBE# outputs are updated to indicate which bytes are valid for the last transfer. PTRDY# remains asserted, indicating that the current transfer is complete. Clock 6: Add-on logic uses t he rising edge of this clock to store DATA3 from the S5920. PTRDY# sam - pled completes the last data phase. As a result, the S5920 deasserts PTATN#, and drives DATA4 onto the DQ bus. As the Add-on sampled PTBURST# deas serted and PTATN# asserted, it recognizes that the previous read was the last one. As a result, the Add- On deasserts SELECT#, ADR[6:2], BE[3:0]#, RD# and PTRDY#. Clock 7: The Add-on logic stores DATA4 on the rising edge of this clock. As PTATN# is deasserted, the Pass-Thru access is comp lete, and the S5920 can accept new Pass-Thru access es starting on the next clock. The other Pass-Thru signals can also change state (in anticipation of a new transfer). Figure 8 illustrates a Passive mode transfer with a burst of five DWORDs in a PCI to Pass-Thru burst write with PTRDY# used to insert wait states. In some applications, Add-On logic may not be required to transfer data on every ADCLK and can use PTRDY# to control the data rate tran sfer. In this example, Add- On logic latches data every other clock cycle. RD# is shown deasserted when PTRDY# is deasserted, but could remain active during the entire Add-On burst. In this case, the DQ would not go to tri-state between reads, and the PTBE# outputs would lose some of their significance (as they would transition one cycle early as a result of the “unused” read). Clock 0: The address is recognized as a PCI write to Pass-Thru region 0. The PCI bus write address is stored in the Pass-Thru Address Register. The PCI bus write data is stored in the S5920 write FIFO. Add- On bus signals PTATN#, PTBURST#, PTNUM[1:0], PTWR and PTBE[3:0] will update on the next rising edge of ADCLK.

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 126 Data Book Clock 1: Pass-Thru signals PTATN#, PTBURST#, PTNUM[1:0], PTWR and PTBE[3:0] are driven to indi - cate what action is required by Add-On logic. These status signals are valid only when PTATN# is active. Add-On logic can decode status signals upon the assertion of PTATN#. PTATN# Asserted. Indicates Pass-Thru access is pending. PTBURST# Asserted. The access has multiple data phases. PTNUM[1:0] 0h. Indicates th e access is to Pass-Thru region 3. PTWR Asserted. Indicates the access is a write. PTBE[3:0]# D1. Indicates valid bytes for the first data transfer. Clock 2: Add-On logic samples PTATN# and PTBURST# asserted, indicati ng the start of a burst. The Add-On asserts PTADR# to read th e Pass-Thru Address Register. As it is not ready to receive any data yet, it does not initiate a data read. Clock 3: Add-on logic latches the address. RD#, BE[3:0]#, ADR[6:2], and SELECT# inputs are asserted to select the Pass-Thru Data Register during the next clock. PTRDY# is also asserted to indicate the com - pletion of the first data phase. Clock 4: As the S5920 sampled PTRDY# asserted, the first data phase is completed DATA1 is driven on the DQ bus, a result of t he read from the previous clock cycle. The PTBE# outputs are updated to indi cate which bytes are valid for the second transfer. Add-on logic is not fast enough to store the next data, so a wait state is activated by deasserting PTRDY#. RD# is also deasserted. Clock 5: Add-On logic uses the rising edge of this clock to store DATA1. PTRDY# is sampled deas - serted, so a wait state is activated. PTRDY# is asserted to indicate that the Add-On is ready to accept the next data transfer. RD# is also asserted, request ing DATA2 to be driven during the next clock cycle. Clock 6: PTRDY# is sampled asserted, thus complet - ing the current data-phase. DATA2 is driven on the DQ bus, a result of a read during the previous clock cycle. The PTBE# outputs are updated to indicate which bytes are valid for the third transfer. Add-on logic is not fast enough to store the next data, so a wait state is activated by deasserting PTRDY#. RD# is also deasserted. Clock 7: Add-On logic uses the rising edge of this clock to store DATA2. PTRDY# is sampled deas - serted, so a wait state is activated. PTRDY# is asserted to indicate that the Add-On is ready to accept the next data transfer. RD# is also asserted, request - ing DATA3 to be driven during the next clock cycle. Clock 8: PTRDY# is sampled asserted, thus complet - ing the current data-phase. DATA3 is driven on the DQ bus, a result of a read during the previous cycle. The PTBE# outputs are updated to indicate which bytes are valid for the fourth transfer. Add-On logic is not fast enough to store the next data, so a wait state is acti vated by deasserting PTRDY#. RD# is also deasserted. Clock 9: Add-On logic uses the rising edge of this clock to store DATA3. PTRDY# is sampled deas - serted, so a wait state is activated. PTRDY# is asserted to indicate that the Add-On is ready to accept the next data transfer. RD# is also asserted, request ing DATA4 to be driven during the next clock cycle. Clock 10: PTRDY# is sampled asserted, thus com - pleting the current data-phase. PTBURST# is deasserted, indicating that only one DWORD is left for transfer. DATA4 is driven on the Add-On DQ bus, a result of a read during th e previous clock cycle. The PTBE# outputs are updated to indicate which bytes are valid for the last transfer. Add-On logic is not fast enough to store the next data, so a wait state is acti vated by deasserting PTRDY#. RD# is also deasserted. Clock 11: Add-On logic uses the rising edge of this clock to store DATA4. PTRDY# is sampled deas - serted, so a wait state is activated. PTRDY# is asserted to indicate that the add-on is ready to accept the last data transfer. The add-on knows this is the last transfer as it has sampled PTBURST# deasserted and PTATN# asserted. RD# is al so asserted, requesting DATA5 to be driven during the next clock cycle. Clock 12: PTRDY# is sampled asserted, indicating that the last transfer was completed. As a result, PTATN# is deasserted. As the Add-On has also fin ished its transfer, it deasserts RD#, SELECT#, BE[3:0]#. The last data, DATA5, is driven on the Add- On DQ bus. Clock 13: Add-On logic uses the rising edge of this clock to store DATA5. As PTATN# is deasserted, the Pass-Thru access is comp lete, and the S5920 can accept new Pass-Thru access es starting on the next clock. The other Pass-Thru signals can also change state (in anticipation of a new transfer). Pass-Thru Burst Reads A Pass-Thru burst read operation occurs when a PCI initiator reads multiple DWORDs from a Pass-Thru region. A burst transfer consists of a single address and multiple data phases. The S5920 stores the PCI

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 128 Data Book DQ outputs to float before Add-On logic attempts to write to the Pass-Thru Read FIFO. Clock 4: The BE[3:0]#, ADR[6:2], and SELECT# inputs are asserted. WR# and DQ are asserted, indi - cating that DATA1 is to be written to the PT Read FIFO on the next clock. PTRDY# is asserted, to indicate the completion of the current data phase. Clock 5: As the S5920 samples WR# asserted, it writes DATA1 into the PT Read FIFO. PTRDY# is sam- pled asserted, which completes the first data transfer and updates the internal FIFO pointers. The PTBE# outputs are updated to indicate which bytes are valid for the second transfer. The Add-On logic samples PTBURST# asserted, so it knows more data is being requested. The Add-On keeps WR# asserted, and drives DATA2 onto the DQ bus. PTRDY# is also asserted to complete the current data phase. Clock 6: As the S5920 samples WR# asserted, it writes DATA2 into the PT Read FIFO. PTRDY# is sam- pled asserted, which completes the second data transfer and updates the internal FIFO pointers. The PTBE# outputs are updated to indicate which bytes are valid for the third transfer. The Add-On logic sam ples PTBURST# asserted, so it knows more data is being requested. The Add-On keeps WR# asserted, and drives DATA3 onto the DQ bus. PTRDY# is also asserted to complete the current data phase. Clock 7: As the S5920 samples WR# asserted, it writes DATA3 into the PT Read FIFO. PTRDY# is sam- pled asserted, which completes the third data transfer and updates the internal FIFO pointers. The PTBE# outputs are updated to indicate which bytes are valid for the last transfer. The S5920 deasserts PTBURST#, indicating that the previous read was the second to last. The next transfer from the Add-On bus will be the last. The Add-On logic sa mples PTBURST# asserted, so it knows more data is being requested. The Add-On keeps WR# asserted, and drives DATA4 onto the DQ bus. PTRDY# is also asserted to complete the current data phase. Clock 8: As the S5920 samples WR# asserted, it writes DATA4 into the PT Read FIFO. PTRDY# is sam- pled asserted, which complete s the final data transfer and updates the internal FIFO pointers. The S5920 deasserts PTATN#, indicating that the final transfer was performed. No more data is being requested from PCI. The Add-On logic samples PTBURST# deas serted, so it knows that the previous data transfer was the last, and no more data is being requested. The Add-On deasserts WR#, ADR[6:2], SELECT#, BE[3:0]# and DQ. It also deasserts PTRDY#. Note that in a synchronous design, t he Add-On logic does not require PTATN# in order to terminate a Pass-Thru read operation, PTBURST# is used for this. Clock 9: As PTATN# and PTBURST# are deasserted, the Pass-Thru access is complete, and the S5920 can accept new Pass-Thru access es starting on the next clock. The other Pass-Thru signals can also change state (in anticipation of a new transfer). NOTE: With prefetch disabled, the performance of Pass-Thru burst reads will be less than optimal. Because of certain issues involving synchronizing sig- nals across clock boundaries (ADCLK -> PCLK), Pass-Thru burst reads will o ccur only in double and single accesses. For example, a Pass-Thru burst read of five data phases would tr anslate to a burst-read of two DWORDs, another burst-read of two DWORDs followed by a single burst-read with PTATN# being deasserted between each burst packet, losing poten tially valuable clock cycle s. It is recommended to enable prefetch if maximum performance is desired. Figure 10 also shows a Passive Mode Pass-Thru burst read, but the Add-On logic uses PTRDY# to control the rate at which data is transferred. In many applica tions, Add-On logic is not fa st enough to provide data every ADCLK. In this example, the Add-On interface writes data every other clock cycle. Using PTRDY# to assert Wait-States Clock 0: PCI address information is stored in the Pass- Thru Address Register. The address is recognized as a PCI read of Pass-Thru region 1. Add-On bus signals PTATN#, PTBURST#, PTNUM[1:0], PTWR and PTBE[3:0] will update on the next rising edge of ADCLK. Clock 1: Pass-Thru signals PTATN#, PTBURST#, PTNUM[1:0], PTWR and PTBE[3:0] are driven to indi - cate what action is required by Add-On logic. These status signals are valid only when PTATN# is active. Add-On logic can decode status signals upon the assertion of PTATN#. PTATN# Asserted. Indicates Pass-Thru access is pending. PTBURST# Asserted. The access has multiple data phases. PTNUM[1:0] 0h.Indicates. th e access is to Pass-Thru region 0. PTWR Deasserted. Indicates the access is a read. PTBE[3:0]# D1. Indicates valid bytes for the first data transfer. Clock 2: The Add-On logic has sampled PTATN# and PTBURST# active, indicating that at least two read data transfers are requested by the PCI. The Add-On

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 129 Data Book will start servicing the Burst Read transfer by first read- ing the Pass-Thru Address via PTADR#. This is an asynchronous read, meaning that the address will appear on DQ after a propagation delay from the assertion of PTADR#. In the event that the address is not required, this cycle a nd the next could be skipped (as the next clock provides a turn-around cycle). Clock 3: The Add-On logic will latch the Pass-Thru address on the rising edge of this clock. This cycle is also required to avoid contention on the DQ bus. Time must be allowed after PTADR# is deasserted for the DQ outputs to float before Add-On logic attempts to write to the Pass-Thru Read FIFO. Clock 4: The BE[3:0]#, ADR[6:2], and SELECT# inputs are asserted. WR# and DQ are asserted, indi - cating that DATA1 is to be written to the PT Read FIFO on the next clock. PTRDY# is asserted, to indicate the completion of the current data phase. Clock 5: As the S5920 samples WR# asserted, it writes DATA1 into the PT Read FIFO. PTRDY# is sam- pled asserted, which completes the first data transfer and updates the internal FIFO pointers. The PTBE# outputs are updated to indicate which bytes are valid for the second transfer. The Add-On logic samples PTBURST# asserted, so it knows more data is being requested WR# remains asserted, and DATA2 is driven onto DQ. PTRDY# is also asserted to complete the current data phase. Clock 6: As the S5920 samples WR# asserted, it writes DATA2 into the PT Read FIFO. PTRDY# is sam- pled asserted, which completes the second data transfer and updates the internal FIFO pointers. The PTBE# outputs are updated to indicate which bytes are valid for the third transfer. The Add-On logic sam ples PTBURST# asserted, so it knows more data is being requested. However, it is not ready to transfer data yet, so it deasserts PTRDY# and WR#, and stop driving the DQ bus. The DQ bus could be in tri-state. Clock 7: As the S5920 samples WR# and PTRDY# deasserted, no data was written to the PT Read FIFO and the FIFO pointer was not updated (as the transfer was not signaled complete via a PTRDY#). The Add- On logic is ready to continue the transfer, so it asserts WR# and drives the DQ bus with DATA3. PTRDY# is also asserted to complete the current data phase. Clock 8: As the S5920 samples WR# asserted, it writes DATA3 into the PT Read FIFO. PTRDY# is sam- pled asserted, which completes the third data transfer and updates the internal FIFO pointers. The S5920 deasserts PTBURST#, indicating that the previus read was the second to last. The next transfer from the Add-On will be the last. The PTBE# outputs are updated to indicate which bytes are valid for the last transfer. The Add-On lo gic samples PTBURST# asserted, so it knows more data is being requested. However, it is not ready to transfer data yet, so it deas serts PTRDY# and WR#. The data on the DQ bus is a donÕt care, as the Add-On is not writing during this cycle. The DQ bus could be in tri-state. Clock 9: As the S5920 samples WR# and PTRDY# deasserted, no data was written to the PT Read FIFO and the FIFO pointer was not updated (as the transfer was not signaled complete via a PTRDY#). The Add- On logic samples PTBURST# deasserted and PTATN# asserted, so it know s that the previous data transfer was the last, and no more data is being requested. However, as it inserted a wait state during the previous cycle, it still has one more transfer to complete. As the Add-On l ogic is ready to complete the transfer, it asserts WR # and drives the DQ bus with DATA4. PTRDY# is also asserted to complete the last data phase. Clock 10: As the S5920 samples WR# asserted, it writes DATA4 into the PT Read FIFO. PTRDY# is sam- pled asserted, which complete s the last data transfer and updates the internal FIFO pointers. The S5920 deasserts PTATN#, indicating that the final transfer was performed. No more data is being requested from PCI. Since the Add-On logic previously sampled PTBURST# deasserted, and transferred the last data, it knows that no more data is being requested. The Add-On deasserts WR#, ADR[6:2], SELECT#, BE[3:0]# and DQ. It also deasserts PTRDY#. Clock 11: As PTATN# and PTBURST# are deas - serted, the Pass-Thru access is complete, and the S5920 can accept new Pass-Thru accesses starting on the next clock. The other Pass-Thru signals can also change state (in anticipation of a new transfer). 8-Bit and 16-Bit Pass-Thru Add-On Bus Interface in Passive Mode The S5920 allows a simple interface to devices with 8- bit or 16-bit data buses. Each Pass-Thru region may be defined as 8, 16 or 32 bits, depending on the con tents of the boot device which is loaded into the PCI Base Address Configuration Registers during initial ization. The result of the initialization is a unique bussize (8/16/32 bits) for each Pass-Thru region. The Pass-Thru Add-On interface internally co ntrols byte lane steering to allow acce ss to the 32-bit Pass-Thru Data FIFO (APTD) from 8-bit or 16-bit Add-On buses. The four DQ data bytes are internally steered depend ing upon the bus size of the region and the values of the Byte Enables (BE#). Note that this 8-/16-bit inter nal byte-lane steering is not performed for other Add-

word at a time (depending on the Add-On bus width). the byte lane steering mechanism used by the S5920. written (and which bytes have already been written). PTRDY#, completing the cycle. steered into BYTE1 of the APTD register. by the Add-On, completing the access. region bus-sizes have no effect on APTA accesses. device must access the APTD one byte at a time. enables of the DWORDs were active. Table 54. Byte Lane Steering for PCI Write (Add-On Table 55. Byte Lane Steering for PCI Read (Add-On

32 Bit Data Bus DQ[31:24] DQ[23:16] DQ[15:8] DQ[7:0]

16 Bit Data Bus DQ[15:8] DQ[7:0] DQ[15:8] DQ[7:0]

8 Bit Data Bus DQ[7:0] DQ[7:0] DQ[7:0] DQ[7:0]

PTWR and PTBE[3:0] will update on the next ADCLK. status signals are valid only when PTATN# is active. PTWR Asserted. Indicates the access is a write. driven on DQ[7:0] during the next clock cycle. driven on the DQ bus during the next cycle. the DQ bus during the next cycle. Figure 69. PCI to Add-On Passive Write to an 8-bit

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 132 Data Book Clock 5: The Add-On logic latches BYTE1. RD# and BE2# are sampled asserted by the S5920, so BYTE2 of the APTD is driven on DQ[7:0] and PTBE2# is deas serted. The Add-On devic e asserts RD# and BE3#, thus requesting that BYTE3 of the APTD be driven on the DQ bus during the ne xt cycle. PTRDY# is also asserted, indicating that the transfer is complete. Clock 6: The Add-On logic latches BYTE2. RD# and BE3# are sampled asserted by the S5920, so BYTE3 of the APTD is driven on DQ[7:0]. PTRDY# is sampled asserted, so the previous transfer is complete. The PTBE# signals are updated to indicate which bytes are valid for the next transfer (i n this case, all bytes are valid for the second DWO RD, so PTBE# = 0h). The S5920 deasserts PTBURST#, as it only has one DWORD left to transfer. The Add-On device asserts RD# and BE3#, thus requesting that BYTE3 of the second DWORD in the APTD be driven on the DQ bus during the next cycle. Clock 7: The Add-On logic latches BYTE3 of the first DWORD. RD# and BE3# are sampled asserted by the S5920, so BYTE3 of the second DWORD in the APTD is driven on DQ[7:0] and PTBE3# is deasserted. The Add-On device asserts RD# and BE2#, thus request ing that BYTE2 of the APTD be driven on the DQ bus during the next cycle. Clock 8: The Add-On logic latches BYTE3 of the sec - ond DWORD. RD# and BE2# are sampled asserted by the S5920, so BYTE2 of the APTD is driven on DQ[7:0] and PTBE2# is deasserted. The Add-On asserts RD# and BE1#, thus requesting that BYTE1 of the APTD be driven on the DQ bus during the next cycle. Clock 9: The Add-On logic latches BYTE2 of the sec - ond DWORD. RD# and BE1# are sampled by the S5920, so BYTE1 of the APTD is driven on DQ[7:0] and PTBE1# is deasserted. The Add-On asserts RD# and BE0#, thus requesting that BYTE0 of the APTD be driven on the DQ bus during the next cycle. PTRDY# is also asserted, indicating that the transfer is com plete. As PTBURST# is already deasserted, the Add- On recognizes that this is the last transfer. Clock 10: The Add-On logic latches BYTE1 of the second DWORD. RD# and BE0# are sampled by the S5920, so BYTE0 of the APTD is driven on DQ[7:0]. PTRDY# is sampled asserted, so the previous transfer is complete. The PTBE# signals are updated to indi cate which bytes are valid for the next transfer (in this case, there is no more valid data to transfer, so PTBE = Fh). The S5920 deasserts PTATN#, as it has no data left to transfer. The Add-On device deasserts RD#, BE#, ADR[6:2], SELECT# as the data transfer is complete. Clock 11: The Add-On logic latches BYTE0 of the second DWORD. PTATN# and PTBURST# both deas- serted indicate that the Pass-Thru transfer is complete. The PCI can start another access on the next clock cycle. For 16-bi t peripheral devices, the byte steering works in th e same way. Because the Add-On data bus is 16 bits wide, only two 16-bit cycles are required to access the entire APTD Register. Two byte enables can be asserted during each access. Figure 12 shows a Pass-Thru read operation for a region defined for a 16-bit Add-On bus interface. As the 16-bit device is conne cted only to DQ[15:0], the device must access the APTD one word at a time. The Add-On must be capable of latching the upper 16 bits of the APTA (if they are needed). The PCI initiator has requested a 32-bit burst read from Pass-Thru region three. All PTBE#s are asserted. Clock 1: The Add-On begins by reading the APTA register (asserting PTADR#). All 32 bits of the address are driven on the DQ bus. Clock 2: Turn-around cycle, pr eventing potential bus contention on the DQ bus. Clock 3: The Add-On initiates the write by asserting WR#, SELECT#, BE[3:0]# = “1100”, ADR[6:2] = 2Ch and the low word of the first DWORD to be transferred (D0-LO). Clock 4: The S5920 updates the PTBE#s to indicate that the low word was provided, and that the upper word is still required. The Add-On drives the upper word (D0-HI), and activates the appropriate byte enables, BE# = 0011 The Add-On also asserts PTRDY#, indicating that it is done with the current DWORD, and to advance the FIFO pointer and pre pare for the second DWORD. Clock 5: The PTBE#s are updated to indicate that the next DWORD to be transferred requires all bytes. The Add-On drives DQ[15:0] wi th the lower word of the second DWORD (D1-LO), and the byte-enables indi cate the same, BE# = 1100. The Add-On also deasserts PTRDY#. This pr ocess continues until the transfer is complete and all words have been written. Endian Conversion Endian conversion can be enabled/disabled for each Pass-Thru Region. It is controlled by bits 6, 14, 22 and 30 of the PTCR. The default endian type for the S5920 is Little Endian. For this reason, the default values in the PTCR are for Little Endian. If Big Endian is selected, the Pass-Thru dat a and byte-enable inter face will be converted to Big Endian type.

designer flexibility through programmable features. The following is a brief description of these features.

• Pass-Thru address can be driven automatically at the beginning of all transfers or can be skipped altogether if addresses are unneeded by Add-On logic.
• Programmed or Add-On controlled wait states to delay data transfers automatically or on the fly.
• Endian Conversion
• Write FIFO ( Write posting )
• Read FIFO ( Prefetch ) Active Operation In Active mode, a data transfer start is signaled on the first clock edge in which PTATN# is sampled low. If PTADR# has been programmed to be output it will go active (low) at this time, and the data presented on the DQ bus is the address for the current transaction. Add- On logic may latch the address value at the rising edge of the clock. Address cycles do not count toward the number of wait states needed to complete data phases. In Active mode, the PTRDY# pin is renamed to PTWAIT#. On cycles after PTWAIT# is sampled low, the state machine is idle. Idle cycles are also not counted as wait states by the S5920. To control the number of wait states on an as-needed basis only, zero wait states should be programmed and PTWAIT# can be driven low when wait states are to be inserted. If PTWAIT# is low when PT ATN# is asserted by the S5920, the pending transfer cycle won’t be started until PTWAIT# is driven high.

Figure 70. PCI to Add-On Passive Read to an 16-bit Add-On Device Table 56. Showing Big Endian Conversion for 32-bit

0 D7-D0 D31-D24

1 D15-D8 D23-D16

2 D23-D15 D15-D8

3 D31-D24 D7-D0

Figure 76. Active Mode 32-Bit PCI Write w/PTWAIT# latch the first data word at the rising edge of this clock. requesting a wait state on the next cycle. must latch the second data word at this clock edge. (low) requesting a wait state on the next cycle. active (low) at the rising edge of clock 6). there is only one data word left to transfer.

address at the rising edge of this clock. 5). Data1 is driven onto the DQ[31:0] bus. determined by decoding the PTBE[3:0]# lines. transferred on the next rising clock edge (clock 7). DATA2 is driven onto the DQ[31:0] bus. data word (DATA2) at the rising edge of this clock. transferred on the next rising clock edge (clock 9). transferred, there is only one data word left to transfer. data word (DATA3) at this clock edge. be transferred on the next rising clock edge (clock 11). since the access is complete. Clock 12: PTBE# may change state. data transfers (one for each byte) vice 2. Figure 79. Active Mode PCI Read w/ Programmed Wait States

BADR1:4 bits D31:30 are used only by the S5920. region to a maximum size of 512 Mbytes of memory. Figure 82. 8-Bit Active Mode PCI Write Pass-Thru region is requesting. set, the region should be I/O mapped. only used for memory mapped regions. ory region is not cacheable. 58h = 3xxxxxxxh Pass-Thru region 2 is disabled. 60h = 00000000h Pass-Thru region 4 is disabled.

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 142 Data Book After the host reads all Base Address Registers in the system (as every PCI device implements from one to six), the PCI BIOS allocates memory and I/O space to each Base Address region. The host then writes the start address of each region back into the Base Address Registers. The st art address of a region is always an integer multiple of the region size. For example, a 64-Kbyte memory region is always mapped to begin on a 64K boundary in memory. It is important to note that no PCI device can be absolutely located in system memory or I/O space. All mapping is determined by the system, not the application. PCI or Add-On Operation registers PTCR or APTCR provide additional configuration control for each region. Accessing a Pass-Thru Region After the system is finished defining all Base Address Regions within a system, each Base Address Register contains a physical addre ss. The application software must now find the location in memory or I/O space of its hardware. PCI systems provide BIOS or operating system function calls for application software to find particular devices on the PCI bus based on Vendor ID and Device ID values. This allows application software to access the device’s Configuration Registers. The Base Address Register values in the S5920’s Configuration Space may then be read and stored for use by the program to acce ss application hardware. The value in the Base Address Registers is the physi cal address of the first lo cation of that Pass-Thru region. Some processor architectures allow this address to be used directl y to access the PCI device. For Intel Architecture systems, the physical address must be changed into a Segment/Offset combination. For Real Mode operation in an Intel Architecture sys - tem (device mapped below 1 Mbyte in memory), creating a Segment/Offset pair is relatively simple. To calculate a physical address, the CPU shifts the seg - ment register 4 bits to the left and adds the offset (resulting in a 20 bit physical address). The value in the Base Address Register must be read and shifted 4 bits to the right. This is the segment value and should be stored in one of the Segment registers. An offset of zero (stored in SI, DI or another offset register) accesses the first location in the Pass-Thru region. Special Programming Features A few additional features have been provided to the user which will allow for optimal “tuning” of their sys - tem. As these are not features that will be changed “on the fly”, they have been included as part of the nvRAM boot-up sequence. nvRAM address 45h is a memory location in the external nvRAM which will contain these custom programmed bits. These features, and their corresponding bit at location 45h, are described as follows: Target Latency describes the number of cycles that a target device may respond to a PCI data transfer request. The PCI 2.1 specific ation indicates that the target device has 16 clocks to respond to an initial request (from the assertion of FRAME#), and 8 clocks from each subsequent data phase. If the target is not capable of asserting TRDY# within these time frames, it must assert a STOP#, thus initiating a disconnect. The Target Latency programmed bit allows the user to disable the generation of disconnects in the event of a slow Add-On device. If Target Latency Enb is low, target latency is ignored. In this case, the S5920 will never issue a retry/discon nect in the event of a slow add-on device. Instead, TRDY# wait states will be asserted. This might be use- ful for an embedded system, where the S5920 can take up as many clock cycles as necessary to com - plete a transfer. This programmable bit is only provided for flexibility and most users should leave this bit set to 1. If Target Latency Enb is high, the device will be PCI 2.1 compliant with respect to Target Latency. Retry Flush Enb indicates to the Pass-Thru whether to hold prefetched data following a disconnect, or to allow the data to be flushed out during the next PCI read access. If low, the data will be held in the PT read FIFO until the initiator co mes back to read it out. All subsequent PCI accesses to the S5920 from a device other than the one who initiated the read will be acknowledged with a retry. If the master never returns for the data, the Pass-Thru function will be hung. Even though the PCI 2.1 Specification does not require a master to return for data following a disconnect, it is unlikely that a master will terminate a read transfer until all data has been collected. If Retry Flush Enb is high, the data will be flushed from the FIFO if a subsequent PCI read access is not to the same address. If the original master received a retry LOC_45(h) Descripton Default b = 0 Target Latency Enb 1 b = 1 Retry Flush Enb 0 b = 2 Write FIFO Mode 0 b = (7:3) Reserved x

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 143 Data Book (disconnect, but with no data transfer), the read data is held in the FIFO until the master comes back for it. In this case, the Retry Flush Enb has no effect. The PCI

2.1 Specification states that the master must come

back if it receives a retry. Write FIFO Mode indicates what to do in the event that a full FIFO is detected duri ng a PCI write transfer. If low, the S5920 will perform an immediate disconnect, thus freeing up the PCI bus for other transfers. The ini tiator will have to come back to complete the data transfer, after which time the FIFO should no longer be full. If Write FIFO Mode is high, the S5920 will deas - sert TRDY#, and allow for either another FIFO location to become available (as the Add-On has read a DWORD), or wait for the Target Latency to expire (8 clocks from previous data phase), thus initiating a dis connect. This will allow for the Add-on device to “catch-up” without losing the burst.

beyond those indicated in the Operating Characteristics section of this specification is not implied. device tested. All values are maximum guaranteed values. Table 59. Absolute Maximum Stress Ratings Table 60. Operating Conditions

IDSEL (in), DEVSEL# (s/t/s), PERR# (s/t/s), SERR# (o/d), INTA# (o/d), RST# (in), CLK (in).

1. Recommended values for all PC I signals except CLK to be Vih = 2.4 Min and Vil = .4 Max.
2. Input leakage applies to all inputs and bi-directional buffers.
3. PCI bus signals without pull-up resistors will provide the 3 mA output current. Signals which require a pull-up resistor will provide 6 mA output
4. The PCI specification limits all PCI inputs not located on the motherboard to 10 pF (the clock is allowed to be 12 pF).

Table 61. PCI Signal DC Characteristics (V CC = 5.0V 5%, 0 0 C to 70 0 C, 50 pF load on outputs)

tion of BPCLK which can sink or source 8 mA. Table 62. Add-On Operating Characteristics (V CC = 5.0V 5%, 0 0 C to 70 0 C, 50 pF load on outputs)

Table 5 visually indicate the timing relationships.

1. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate is met across the minimum peak-to-peak portion

of the clock waveform as shown in Figure 1.

1. Minimum times are evaluated with 0 pF equivalent load; maximum times are evaluated with 50 pF equivalent load.
2. For purposes of Active/Float timing measurements, the Hi-Z or 'off" state is defined to be when the total current delivered through the compo-

nent pin is less than or equal to the leakage current specification.

1. See the timing measurem ent conditions in Figure 3.

Figure 83. PCI Clock Timing Table 63. Functional Operation Range

after Table 6 visually indicate the timing relationships. Table 64. Add-On Timings, Functional Operation Range

1. Refers to Pass-Thru Passive mode only.
2. Refers to Pass-Thru Active and Passive modes.

Figure 89. Passive Mode Pass-Thru Operation

1. Refers to Pass-Thru Active mode only.

Table 65. Add-On Timings

Figure 90. Active Mode Pass-Thru Write Operation

1. Applies only when external mailbox is in input mode (MDMODE = 1).
2. Applies only when external mailbox is in input/output mode (MDMODE = 0).
3. When the S5920 is driving MD[7:0] w/ Add-On incoming mailbox byte 3, the PCI can update this output synchronously to the PCI clock. As a

result, once driving, this output is asynchronous to ADCLK. Figure 91. Mailbox Data Figure 92. Mailbox Data Table 66. Mailbox Timings

5920 Driving 5920 Driving

Figure 93. S5920 Pinout and Pin Assignment

160 PQFP

Figure 94. S5920 – 160 PQFP Package Marking Drawing (Top View) guaranteed to meet the specifications in this document. RoHS Lead Free Compliant Symbol (per JEDEC: JESD97). When present, this signifies a lead free package.

Figure 95. 160 PQFP (28 x 28 x 3.37 mm) - Plastic Quad Flat Package Standard Package: Pin Compiosition - 85Sn/15Pb.

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 159 Data Book DOCUMENT REVISION HISTORY Revision Date Description 1.01 11/28/05 • Page 2, Updated Features section

• Page 157, Added Figure 94, S5920 – 176 LQFP Package Marking Drawing
• Page 158, Added Note to Figure 95
• Page 160, Updated Ordering Information

S5920 – PCI Product Revision 1.01 – November 28, 2005 AMCC Confidential and Proprietary DS1596 160 Data Book

Ordering Information

Applied Micro Circuits Corporation 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) 450-9333 — (800) 755-2622 — Fax: (858) 450-9885 http://www.amcc.com AMCC reserves the right to make changes to its products, its datasheets, or related documentation, without notice and war- rants its products solely pursuant to its terms and conditions of sale, only to substantially co mply with the la test available datasheet. Please consult AMCC’s Term and Conditions of Sale for its warranties and other terms, conditions and limitations. AMCC may discontinue any semiconductor product or service wit hout notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information is current. AMCC does not assume any lia- bility arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the ri ght to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright © 2005 Applied Micro Circuits Corporation. Prefix PackageDevice S - Integrated Circuit 5920 Q -160 PQFP, Standard Package X XXXX XX Prefix Device Package S - Integrated Circuit 5920 QRC - 160 PQFP ,RoHS/Green Lead Free