CPMF-1200-S080B

CPMF-1200-S080B CREE | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 10

Technical content

Features

• Industry Leading RDS(on)
• High Speed Switching
• Low Capacitances
• Easy to Parallel
• Simple to Drive
• Lead-Free Benefits
• Higher System Efficiency
• Reduced Cooling Requirements
• Avalanche Ruggedness
• Increase System Switching Frequency

Applications

• Solar Inverters
• Motor Drives
• Military and Aerospace Package DIE Part Number Package CPMF-1200-S080B DIE G D S S G D Note: 1. Assumes a thermal resistance junction to case of ≤ 0.4 °C/W. VDS = 1200 V RDS(on) = 80 mΩ Qg = 90.8 nC Maximum Ratings Symbol Parameter Value Unit Test Conditions Note ID Continuous Drain Current A VGS@20V, TJ = 25˚C

30 VGS@20V, TJ = 100˚C

IDpulse Pulsed Drain Current 90 A Pulse width tP limited by Tjmax TJ = 25˚C, tp = 1ms EAS Single Pulse Avalanche Energy 2.2 J ID = 20A, VDD = 50 V, L = 9.5 mH EAR Repetitive Avalanche Energy 1.5 J tAR limited by Tjmax IAR Repetitive Avalanche Current 20 A ID = 20A, VDD = 50 V, L = 3 mH tAR limited by Tjmax VGS Gate Source Voltage -5/+25 V Ptot Power Dissipation 313 W Tj=25˚C 1 TJ , Tstg Operating Junction and Storage Temperature -55 to +150 ˚C TL Solder Temperature 260 ˚C 1.6mm (0.063”) from case for 10s

CPMF-1200-S080B Rev. A

Electrical Characteristics

Symbol Parameter Min. Typ. Max. Unit Test Conditions Note V(BR)DSS Drain-Source Breakdown Voltage 1200 V VGS = 0V, ID = 100μA VGS(th) Gate Threshold Voltage 2.5 4 V VDS = VGS, ID = 1mA, TJ = 25ºC

1.7 VDS = VGS, ID = 1mA, TJ = 150ºC

IDSS Zero Gate Voltage Drain Current 1 100 μA VDS = 1200V, VGS = 0V, TJ = 25ºC 10 265 VDS = 1200V, VGS = 0V, TJ = 150ºC IGSS Gate-Source Leakage Current 250 nA VGS = 20V, VDS = 0V RDS(on) Drain-Source On-State Resistance 80 110 mΩ VGS = 20V, ID = 20A, TJ = 25ºC 110 140 VGS = 20V, ID = 20A, TJ = 150ºC gfs Transconductance 7.3 S VDS= 20V, IDS= 20A, TJ = 25ºC fig. 3

6.7 VDS= 20V, IDS= 20A, TJ = 150ºC

Ciss Input Capacitance 1915 pF VGS = 0V VDS = 800V f = 1MHz VAC = 25mV fig. 5 Coss Output Capacitance 120 Crss Reverse Transfer Capacitance 13 td(on)i Turn-On Delay Time 17.2 ns VDD = 800V VGS = -2/20V ID = 20A RG = 6.8Ω L = 856μH Per JEDEC24 Page 27 fig. 11 tr Rise Time 13.6 td(off)i Turn-Off Delay Time 62 tfi Fall Time 35.6 EON Turn-On Switching Loss (25ºC) (150ºC) 530 410 μJ EOff Turn-Off Switching Loss (25ºC) (150ºC) 320 345 μJ RG Internal Gate Resistance 5 Ω VGS = 0V, f = 1MHz, VAC = 25mV Note: 2. The recommended on-state VGS is +20V and the recommended off-state VGS is between 0V and -5V Reverse Diode Characteristics Symbol Parameter Typ. Max. Unit Test Conditions Note Vsd Diode Forward Voltage 3.5 V VGS = -5V, IF=10A, TJ = 25ºC

3.1 VGS = -2V, IF=10A, TJ = 25ºC

trr Reverse Recovery Time 220 ns VGS = -5V, IF=20A, TJ = 25ºC VR = 800V, diF/dt= 100A/μs fig. 12,13Qrr Reverse Recovery Charge 142 nC Irrm Peak Reverse Recovery Current 2.3 A Gate Charge Characteristics Symbol Parameter Typ. Max. Unit Test Conditions Note Qgs Gate to Source Charge 23.8 nC VDD = 800V ID =20A VGS = -2/20V Per JEDEC24-2 fig.8 Qgd Gate to Drain Charge 43.1 Qg Gate Charge Total 90.8

Figure 3. Typical Transfer Characteristics

CPMF-1200-S080B Rev. A 100 200 300 400 500 600 0 25 50 75 100 125 150 100 200 300 400 500 600 0 25 50 75 100 125 150 V GS (V) 0 20 40 60 80 100 V GS (V) Gate Charge (nC) Typical Performance Fig 8. Typical Gate Charge Characteristics @ 25°C Fig 6. Inductive Switching Energy(Turn-on) vs. Temp Fig 7. Inductive Switching Energy(Turn-off) vs. Temp ID=20A VDD=800V VGS= -2/20V RG= 6.8Ω VDD= 800V ID= 20A VGS= -2/20V RG= 6.8Ω VDD= 800V ID= 20A 1000 1500 2000 2500 VDS (V) IDS (A) IDS VDS 500 Time (s) EAS = 2.20 J Fig 9. Typical Avalanche Waveform TJ ˚C TJ ˚C Switching Loss (µJ) Switching Loss (µJ)

CPMF-1200-S080B Rev. A 10% Irr Vcc trr Irr Ic Vpk tx 10% Vcc Qrr=∫ trr id dt tx Diode Reverse Recovery Energy Diode Recovery Waveforms Erec=∫ id dt t1 t2 VGS(off) VGS(on) iD(off) iD(on) td(on)i td(off)itfi tri pulse duration tw Input (Vi) Output (iD) Input Pulse Rise Time Input Pulse Fall Time 90% 50% 10% 90% 50% 10% 10% 10% 90% 90% ton(i) toff(i) 800V - 42.3μf 856μH CMF20120D C2D10120D 10A, 1200V SiC Schottky Clamped Inductive Switch Testing Fixture Fig 10. Switching Waveform Test Circuit Fig 13. Body Diode Recovery Test 800V 42.3μf 856μH CMF20120D CMF20120D Fig 11. Switching Test Waveform Times Fig 12. Body Diode Recovery Waveform D.U.T. D.U.T.

CPMF-1200-S080B Rev. A Fig 15. Theoretical Avalanche WaveformFig 14. Avalanche Test Circuit EA = 1/2L x ID

This product has not been designed or tested for use in, and is not intended for use in, applications implanted into the human body nor in applications in which failure of the product could lead to death, personal injury or property damage, including but not limited to equipment used in the operation of nuclear facilities, life-support machines, cardiac defibrillators or similar emergency medical equipment, aircraft navigation or communication or control systems, air traffic control systems, or weapons systems. Copyright © 2011 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree, the Cree logo is a registered trademark of Cree, Inc. 7 CPMF-1200-S080B Rev. A Cree, Inc.

4600 Silicon Drive

Durham, NC 27703 USA Tel: +1.919.313.5300 Fax: +1.919.313.5451 www.cree.com/power * The levels of environmentally sensitive, persistent biologically toxic (PBT), persistent organic pollutants (POP), or otherwise restricted materials in this product are below the maximum concentration values (also referred to as the threshold limits) permitted for such substances, or are used in an exempted application, in accordance with EU Directive 2002/95/EC on the restriction of the use of certain hazardous substances in electrical and electronic equipment (RoHS), as amended through April 21, 2006. * The die-on-tape method of delivering these SiC die may be considered a means of temporary storage only. Due to an increase in adhesion over time, die stored for an extended period may affix too strongly to the tape. These die should be stored in a temperature-controlled nitrogen dry box soon after receipt. Cree will further recommend that all die be removed from tape to a waffle pack, to a similar storage medium, or used in production within 2 – 3 weeks of delivery to assure 100% release of all die without issues. Part Number Package CPMF-1200-S080B DIE G D S S G D S G D Chip Dimensions Parameter Typ Unit Die Dimensions (L x W) 4.08 x 4.08 mm Exposed Source Pad Metal Dimensions 0.98 x 2.09 (x 2) mm Gate Pad Dimensions 0.84 x 0.60 mm Chip Thickness 365 ± 40 µm Frontside (Source) metallization (Al) 4 µm Frontside (Gate) metallization (Al) 4 µm Backside (Drain) metallization (Ni/Ag) 0.8 / 0.6 µm Mechanical Parameters

CPMF-1200-S080B Rev. A 2.5V Applications Information: The Cree SiC DMOSFET has removed the upper voltage limit of silicon MOSFETs. However, there are some differences in characteristics when compared to what is usually expected with high voltage silicon MOSFETs. These differences need to be carefully addressed to get maximum benefit from the SiC DMOSFET. In general, although the SiC DMOSFET is a superior switch compared to its silicon counter- parts, it should not be considered as a direct drop-in replacement in existing appli- cations. There are two key characteristics that need to be kept in mind when applying the SiC DMOSFETs; modest transconductance and no turn-off tail. The modest trans- conductance requires that VGS needs to be 20V to optimize performance. This can be seen the Output and Transfer Characteristics shown in Figures 1-3. The modest transconductance also affects the transition where the device behaves as a voltage controlled resistance to where it behaves as a voltage controlled current source as a function of VDS. The result is that the transition occurs over higher values of VDS than is usually experienced with Si MOSFETs and IGBTs. This might affect the operation anti-desaturation circuits, especially if the circuit takes advantage of the device entering the constant current region at low values of forward voltage. The modest transconductance needs to be carefully considered in the design of the gate drive circuit. The first obvious requirement is that the gate driver be capable of a 22V (or higher) swing. The recommended on state VGS is +20V and the rec- ommended off state VGS is between 0V to -5V. Please carefully note that although the gate voltage swing is higher than typical silicon MOSFETs and IGBTs, the to- tal gate charge of the SiC DMOSFET is considerably lower. In fact, the product of gate voltage swing and gate charge for the SiC DMOSFET is lower than comparable silicon devices. The gate voltage must have a fast dV/dt to achieve fast switching times which indicates that a very low impedance driver is necessary. Lastly, the fidelity of the gate drive pulse must be carefully controlled. The nominal threshold voltage is 2.3V and the device is not fully on (dVDS/dt ≈ 0) until the VGS is above 16V. This is a noticeably wider range than what is typically experienced with sili- con MOSFETs and IGBTs. The net result of this is that the SiC DMOSFET has a somewhat lower ‘noise margin’. Any excessive ringing that is present on the gate drive signal could cause unintentional turn-on or partial turn-off of the device. The gate resistance should be carefully selected to insure that the gate drive pulse is adequately dampened. To first order, the gate circuit can be approximated as a

CPMF-1200-S080B Rev. A As shown, minimizing LLOOP minimizes the value of RLOOP needed for critical dampening. Minimizing LLOOP also minimizes the rise/fall time. Therefore, it is strongly recommended that the gate drive be located as close to the SiC DMOSFET as possible to minimize LLOOP. An external resistance of 6.8 Ω was used to characterize this device. Lower values of external gate resistance can be used so long as the gate pulse fidelity is maintained. In the event that no external gate resistance is used, it is suggested that the gate current be checked to indirectly verify that there is no ringing present in the gate circuit. This can be accomplished with a very small current transformer. A recommended setup is a two-stage current transformer as shown below: The two stage current transformer first stage consists of 10 turns of AWG 30 wire on a small high permeability core. A Ferroxcube 3E27 material is recommended. The second stage is a small wide bandwidth current transformer, such as the Tektronix CT-2. Lastly, a separate source return should be used for the gate drive as shown below: RLOOP LLOOP CGATEVPULSE

CPMF-1200-S080B Rev. A Stray inductance on source lead causes load di/dt to be fed back into gate drive which causes the following:

• Switch di/dt is limited
• Could cause oscillation LOAD CURRENT LOAD CURRENT SiC DMOSR GATE SiC DMOS R GATE L STRAY Kelvin gate connection with separate source return is highly recommended DRIVE DRIVE 20V 20V A significant benefit of the SiC DMOSFET is the elimination of the tail current observed in silicon IGBTs. However, it is very important to note that the current tail does provide a certain degree of parasitic dampening during turn-off. Additional ringing and overshoot is typically observed when silicon IGBTs is replaced with SiC DMOSFETs. The additional voltage overshoot can be high enough to destroy the device. Therefore, it is critical to manage the output interconnection parasitics (and snubbers) to keep the ringing and overshoot from becoming problematic. ESD RATINGS ESD Test Total Devices Sampled Resulting Classification ESD-HBM All Devices Passed 1000V 2 (>2000V) ESD-MM All Devices Passed 400V C (>400V) ESD-CDM All Devices Passed 1000V IV (>1000V)