CPC7584

CPC7584 CLARE | Alldatasheet

Document overview

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Technical content

Features

• Small 16-pin SOIC or micro-leadframe package  Micro-leadframe package (MLP) printed circuit board footprint is 70% smaller than 4TH generation EMRs and 60% smaller than SOIC version  Monolithic IC reliability  Low matched RON  Eliminates the need for zero cross switching  Flexible switch timing to transition from ringing mode to talk mode.  Clean, bounce free switching  Tertiary protection consisting of integrated current limiting, voltage clamping, and thermal shutdown for SLIC protection  5V operation with power consumption < 10 mW  Intelligent battery monitor  Latched logic level inputs, no external drive circuitry required

Applications

 Central office (CO)  Digital Loop Carrier (DLC)  PBX Systems  Digitally Added Main Line (DAML)  Hybrid Fiber Coax (HFC)  Fiber in the Loop (FITL)  Pair Gain System  Channel Banks

Description

The CPC7584 is a monolithic solid state switch in a 16-pin SOIC or MLP surface mount package. It provides the necessary functions to replace two 2-Form-C electro-mechanical relays on traditional analog and integrated voice and data (IVD) line cards found in Central Office, Access, and PBX equipment. The device contains solid state switches for tip and ring line break, ringing injection/ringing return and channel test access. The CPC7584 requires only a +5V supply and offers “break-before-make” or “make-before-break” switch operation using simple logic-level input control. The CPC7584xC logic differs from the CPC7584xA/B with an enhancement permitting channel monitoring in the test state. See “Functional Description” on page 9 for more information. The CPC7584xC also has a higher trigger and hold current for the protection SCR. Specify CPC7584Bx for SOIC or specify CPC7582Mx for MLP devices shipped in tubes. Append the part number with the suffix TR for tape and reel packaging.

Ordering Information

Figure 1. CPC7584 Block Diagram

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Rev. B www.clare.com 3 Preliminary 1. Specifications 1.1 Package Pinout 1.2 Pinout CPC7584 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 FGND TTEST TBAT TLINE TRINGING VDD TSD DGND RTEST VBAT RBAT RLINE RRINGING LATCH INRINGING INTEST Pin Name Description

1 TTEST Connect to Tip lead of test bus

2 FGND Fault ground

3 TBA T Connect to tip lead of SLIC

4 TLINE Connect to tip lead of the line (drop)

5 TRINGING Connect to ringing generator return

6 VDD +5 V supply

7 TSD

T emperature shutdown indicator pin. Bi-directional I/O with internal pull up to V DD. Output function indicates status of thermal shutdown circuitry, Input function can be used to set the “All-Off” mode using an open-drain type output. 8 D GND Digital ground

9 INTEST Logic-level switch control input

10 INRINGING Logic-level switch control input

11 LA TCH Data latch control, active high, transparent

12 RRINGING

Connect to ringing generator current limiting resistor

13 RLINE Connect to ring lead of the line (drop)

14 RBA T Connect to ring lead of the SLIC

15 VBA T Connect to ring lead of SLIC

16 RTEST

Battery voltage supply. Must be capable of sourcing the trigger current for proper operation of the protection SCR.

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1.3 Absolute Maximum Ratings (at 25° C)

1.4 Electrical Characteristics, TA = -40° C to +85° C

Unless otherwise specified: Minimum and maximum values are production testing requirements. Typical values are provided for information purposes only and are not part of the testing requirements. They are characteristic of the device and are the result of engineering evaluations. V DD =+ 5 Vdc and VBAT =- 4 8 Vdc Absolute maximum ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not implied.

1.4.1 Power Supply Specifications

1.4.2 Break Switches, SW1 and SW2

Parameter Minimum Maximum Unit Operating temperature -40 +110 °C Storage temperature -40 +150 °C Operating relative humidity 5 95 % Pin soldering temperature (10 seconds max) - +260 °C +5 V power supply -0.3 7 V Battery Supply - -85 V Logic input voltage -0.3 V DD+0.3 V Logic input to switch output isolation -3 3 0 V Switch isolation (SW1, SW2, SW3, SW5, SW6) -3 3 0 V Switch Isolation (SW4) - 465 V Supply Minimum Typical Maximum Unit VBA T 1 -19 - -72 V 1 VBAT is used only for internal protection circuitry. If VBA T rises above -10 V, the device will enter and remain in the all-off state until the battery exceeds -15 V. ESD Rating (Human Body Model) 1000 V Parameter Conditions Symbol Minimum Typical Maximum Unit Open Contact Isolation - Off-state leakage current VSW1 = TLINE to TBA T VSW2 = RLINE to RBA T VSW = -320V to GND +25°C VSW = +260 V to -60 V ISW - 0.1 1 µAVSW = -330V to GND +85°C VSW = +270 V to -60 V 0.3 VSW = -310 V to GND -40°C VSW = +250 V to -60 V 0.1 On Resistance ISW = ±10 mA, ±40 mA, TBA T = -2 V +25°C RON -1 4 . 5- Ω ISW = ±10 mA, ±40 mA, TBA T = -2 V +85°C -2 0 . 5 2 8 ISW = ±10 mA, ±40 mA, TBA T = -2 V -40°C -1 0 . 5- Switch Resistance Matching Per On Resistance test conditions above. Magnitude RON SW1 - RON SW2 ∆RON - 0.15 0.8 DC Current Limit VSW (on) = ±10 V +25°C ILIM - 300 - mAVSW (on) = ±10 V +85°C 80 160 - VSW (on) = ±10 V -40°C - 400 425

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1.4.3 Ringing Return Switch, SW3

(t = <0.5 µs) Break switches on, all other switches off, apply ±1 kV 10/1000 µs pulse to Tip/Ring interface with appropriate protection in place. ISW -2 . 5- A Contacts to Input Isolation VSW (TLINE, RLINE) = ±320 V +25°C logic inputs = GND ISW - 0.1 1 µAVSW (TLINE, RLINE) = ±330 V +85°C logic inputs = GND 0.3 VSW (TLINE, RLINE) = ±310 V , -40°C logic inputs = GND 0.1 dv/dt sensitivity Applied voltage = 100 V p-p square wave at

100 Hz - - 200 - V/ µs

Parameter Conditions Symbol Minimum Typical Maximum Unit Open Contact Isolation - Off-state leakage current VSW3 = TLINE to TRINGING VSW = -320V to GND +25°C VSW = +260 V to -60 V ISW - 0.1 1 µAVSW = -330 V to GND +85°C VSW = +270 V to -60 V 0.3 VSW = -310 V to GND -40°C VSW = +250 V to -60 V 0.1 On Resistance ISW (on) = ±0 mA, ±10 mA +25°C RON - 60 - ΩISW (on) = ±0 mA, ±10 mA +85°C 85 100 ISW (on) = ±0 mA, ±10 mA -40°C 45 - DC Current Limit VSW (on) = ±10 V +25°C ISW - 135 -m AVSW (on) = ±10 V +85°C 85 VSW (on) = ±10 V -40°C 210 Dynamic current limit (t = <0.5 µs) Ringing switches on, all other switches off, apply ±1 kV 10/1000 µs pulse to Tip/Ring interface with appropriate protection in place. ISW -2 . 5- A Contacts to Input Isolation VSW (TLINE, TRINGING) = ±320 V +25°C logic inputs = GND ISW - 0.1 1 µAVSW (TLINE, TRINGING) = ±330 V +85°C logic inputs = GND 0.3 VSW (TLINE, TRINGING) = ±310 V -40°C logic inputs = GND 0.1 dv/dt sensitivity Applied voltage = 100 V p-p square wave at Parameter Conditions Symbol Minimum Typical Maximum Unit

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1.4.4 Ringing Switch, SW4

1.4.5 T est Switches, SW5 and SW6

Parameter Conditions Symbol Minimum Typical Maximum Unit Open Contact Isolation - Off-state leakage current VSW4 = RLINE to RRINGING VSW = -255 V to +210 V +25°C VSW = +255 V to -210 V ISW - 0.05 1 µAVSW = -270 V to +210 V +85°C VSW = +270 V to -210 V 0.1 VSW = -245 V to +210 V -40°C VSW = +245 V to -210 V 0.05 On Voltage ISW (on) = ± 1 mA V SW -1 . 53 V On Resistance ISW (on) = ±70 mA, ±80 mA R ON -8 . 5 1 2 Ω Ringing generator current to ground Ringing switches on. IRINGING -0 . 1 0 . 2 5 m A On steady-state current* Ringing switches on. - - - 2 A Surge current* Ringing switches on. - - - 2 A Release current Remove ringing mode, SW4 on. ISW - 300 - µA Contacts to Inout Isolation VSW (RLINE, RRINGING) = ±320 V +25°C logic inputs = GND ISW - 0.05 1 µAVSW (RLINE, RRINGING) = ±330 V +85°C logic inputs = GND 0.1 VSW (RLINE, RRINGING) = ±310 V -40°C logic inputs = GND 0.05 dv/dt sensitivity Applied voltage = 100 V p-p square wave at

• Secondary protection and ringing source current limiting must prevent exceeding these parameters. Parameter Conditions Symbol Minimum Typical Maximum Unit Open Contact Isolation - Off-state leakage current VSW5 = TTEST to TBA T VSW6 = RTEST to RBA T VSW = -320 V to GND +25°C VSW = +260 V to -60 V ISW - 0.1 1 µAVSW = -330 V to GND +85°C VSW =+270 V to -60 V 0.3 VSW = -310 V to GND -40°C VSW = +250 V to -60 V 0.1

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1.5 Digital Input Characteristics - INTEST,INRINGING and LATCH Pins

1.6 Power Consumption Characteristics

TLINE = ±10 mA, ±40 mA, TBA T = -2 V +25°C RON - 38 - ΩTLINE = ±10 mA, ±40 mA, TBA T = -2 V +85°C 46 70 TLINE = ±10 mA, ±40 mA, TBA T = -2 V -40°C 28 - DC Current Limit VSW (on) = ±10 V +25°C ISW - 175 - mAVSW (on) = ±10 V +85°C 80 110 - VSW (on) = ±10 V -40°C - 210 250 Dynamic current limit (t = <0.5 µs) T est switches on , ringing access switches off, apply ±1 kV at 10/1000 µs pulse, with appropriate secondary protection in place. ISW -2 . 5- A Contacts to Input Isolation VSW (TTEST, RTEST) = ±320 V +25°C logic inputs = GND ISW - 0.1 1 µAVSW (TTEST, RTEST) = ±330 V +85°C logic inputs = GND 0.3 VSW (TTEST, RTEST) = ±310 V -40°C logic inputs = GND 0.1 dv/dt sensitivity Applied voltage = 100 V p-p square wave at Parameter Conditions Symbol Minimum Typical Maximum Unit Input Threshold Logic low VIL -- 1 . 5 V Logic high VIH 3.5 - - Input Leakage Current VDD = 5.5 V , VBA T = -75 V , VIH = 5 V I IH -0 . 11 µAVDD = 5.5 V , VBA T = -75 V , VIL = 0 V I IL -0 . 11 Parameter Conditions Symbol Minimum Typical Maximum Unit Parameter Conditions Symbol Minimum Typical Maximum Unit VDD Current Consumption VDD = 5 V , VBA T = -48V , T alk or All-Off states. IDD -1 . 1 2 . 0 mAVDD = 5 V , VBA T = -48 V , Ringing or T est states. -1 . 3 2 . 0 VBA T Current Consumption VDD = 5 V , VBA T = -48 V , Any state IBA T -0 . 1 1 0 µA Power Consumption VDD = 5 V , VBA T = -48 V , T alk or All-Off states. P- 5.5 10 mWVDD = 5 V , VBA T = -48 V , Ringing or T est states. 6.5 10

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1.7 Thermal Shutdown Characteristics

1.8 Protection Circuitry Electrical Specifications

Parameter Conditions Symbol Minimum Typical Maximum Unit Activation T emperature TSD => Low T 110 125 150 °C Hysteresis TSD => High ∆T1 0 - 2 5 ° C Parameter Conditions Symbol Minimum Typical Maximum Unit Parameters Related to the Diodes in the Diode Bridge Voltage drop at continuous current (50/60 Hz) Apply ± dc current limit of break switches VF -2 . 13 VVoltage drop at surge current Apply ± dynamic current limit of break switches VF -5- Parameters Related to the Protection SCR Surge current - - - - * A T rigger current +25°C ITRIG - 60 -m A+85°C 35 Hold current +25°C IHOLD - 100 -m A+85°C 60 70 Gate trigger voltage IGA TE = ITr i g g e r ** VTBA T or VRBA T VBA T -4 - VBA T -2 V Reverse leakage current VBA T = -48V I VBA T -- 1 . 0 µA On-state voltage 0.5 A, t = 0.5 ms V TBA T or VRBA T *Passes GR1089 and ITU-T K.20 with appropriate protection in place. ** VBA T must be capable of sourcing ITRIGGER for the internal SCR to activate.

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1.9 Truth Table - CPC7584xA/B

1.10 Truth Table - CPC7584xC

State INRINGING INTest LATCH TSD 1 Break Switches Ringing Switches Test Switches Ta l k 0 0 0 1 or Floating On Off Off Ringing 1 0 Off On Off Te s t 0 1 Off Off On All Off 1 1 Off Off Off Latched X X 1 Unchanged Unchanged Unchanged A l l o f f XXX0 Off Off Off 1If TSD = 5V , thermal shutdown is disabled. If TSD is left floating, the thermal shutdown mechanism is enabled. State INRINGING INTest LATCH TSD 1 Break Switches Ringing Switches Test Switches Ta l k 0 0 0 1 or Floating On Off Off Ringing 1 0 Off On Off T est / Monitor 0 1 On Off On All Off 1 1 Off Off Off Latched X X 1 Unchanged Unchanged Unchanged A l l o f f XXX0 Off Off Off 1If TSD = 5V , thermal shutdown is disabled. If TSD is left floating, the thermal shutdown mechanism is enabled.

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2.1 Introduction

The CPC7584xA/B has four states:  Talk. Line break switches SW1 and SW2 closed, ringing switches SW3 and SW4 open, and test switches SW5 and SW6 open.  Ringing. Line break switches SW1 and SW2 open, ringing switches SW3 and SW4 closed, and test-in switches SW5 and SW6 open.  Test. Line break switches SW1 and SW2 open, ringing switches SW3 and SW4 open, and test-in switches SW5 and SW6 closed.  All off. Line break switches SW1 and SW2 open, ringing switches SW3 and SW4 open, and loop test switches SW5 and SW6 open. The CPC7584xC replaces the Test state with the Test/Monitor state as defined below.  Test/Monitor. Line break switches SW1 and SW2 closed, ringing switches SW3 and SW4 open, and test-in switches SW5 and SW6 closed. The CPC7584 offers break-before-make and make-before-break switching with simple logic-level input control. Solid-state switch construction means no impulse noise is generated when switching during ring cadence or ring trip, eliminating the need for external zero-cross switching circuitry. State-control is via logic-level input so no additional driver circuitry is required. The line break switches SW1 and SW2 are linear switches that have exceptionally low RDS ON and excellent matching characteristics. The ringing access switch SW4 has a breakdown voltage rating of greater than 480 V. This is sufficiently high, with proper protection, to prevent breakdown in the presence of a transient fault condition (i.e., passing the transient on to the ring generator). Integrated into the CPC7584 is a diode bridge/SCR clamping circuit, current limiting, and a thermal shutdown mechanism to provide protection to the SLIC device during a fault condition. Positive and negative surges are reduced by the current limiting circuitry and steered to ground via diodes and the integrated SCR. Power-cross transients are also reduced by the current limiting and thermal shutdown circuits. Note that only the CPC7584xA and CPC7584xC parts include the integrated protection SCR. To protect the CPC7584 from an overvoltage fault condition, use of a secondary protector is required. The secondary protector must limit the voltage seen at the tip and ring terminals to a level below the maximum breakdown voltage of the switches. To minimize the stress on the solid-state contacts, use of a foldback or crowbar type secondary protector is recommended. With proper selection of the secondary protector, a line card using the CPC7582BC will meet all relevant ITU, LSSGR, FCC and UL protection requirements. The CPC7584 operates from a +5 V supply only. This gives the device extremely low idle and active power dissipation and allows use with virtually any range of battery voltage. A battery voltage is also used by the CPC7584 as a reference for the integrated protection circuit. In the event of a loss of battery voltage, the CPC7584 enters the all-off state.

2.2 Switch Timing

The CPC7584 provides, when switching from the ringing state to the idle/talk state, the ability to control the release timing of the ringing access switches SW3 and SW4 relative to the state of the line break switches SW1 and SW2 using simple logic-level input. This is referred to a make-before-break or break-before-make operation. When the line break switch contacts (SW1 and SW2) are closed (or made) before the ringing access switch contacts (SW3 and SW4) are opened (or broken), this is referred to make-before-break operation. Break-before-make operation occurs when the ringing access contacts (SW3 and SW4) are opened (broken) before the line break switch contacts (SW1 and SW2) are closed (made). With the CPC7584, the make-before-break and break-before-make operations can easily be selected by applying logic-level inputs to pins 9 and 10 (IN RING and INTEST -IN) of the device. The logic sequences for either mode of operation are given in “Make-Before-Break Operation (Ringing to Talk Transition)” on page 11 and “Break-Before-Make Operation (Ringing to Talk Transition)” on page 11. Logic states and explanations are given in “Truth Table - CPC7584xA/B” on page 9. Break-before-make operation can also be achieved using pin 7 (TSD) as an input. In “Break-Before-Make Operation (Ringing to Talk Transition)” on page 11 lines 2 and 3, it is possible to induce the switches to the all-off state by grounding pin 7 (TSD) instead of

Rev. B www.clare.com 11 Preliminary apply logic input to the pins. This has the effect of overriding the logic inputs and forcing the device to the all-off state. Hold this input state for 25 ms. During this hold period, toggle the inputs from the ringing state (10) to the idle/talk state (00). After the 25 ms, release pin 7 (TSD) to return the switch control to the input pins 9 and 10 and reset the device to the idle/talk state. Setting TSD to +5 V allows switch control using the logic pins 9 and 10. This setting, however, also disables the thermal shutdown circuit and is therefore not recommended. When using logic controls via the input pins 9 and 10, pin 7 (TSD) should be allowed to float. As a result, the two recommended states when using pin 7 (TSD) as a control are 0, which forces the device to the all-off state, or float, which allows logic inputs to pins 9 and 10 to remain active. This may require the use of an open-collector buffer.

2.2.1 Make-Before-Break Operation (Ringing to T alk T ransition)

2.2.2 Break-Before-Make Operation (Ringing to T alk T ransition)

2.2.3 Alternate Break-Before-Make Operation

Break-before-make operation can also be achieved using TSD as an input. In lines 2 and 3 of “Break-Before-Make Operation (Ringing to Talk Transition)” on page 11, instead of using the logic input pins to force the all-off state, force TSD to ground. This overrides the logic inputs and also forces the all off state. Hold this state for 25 ms. During this 25 ms all-off state, toggle the inputs from the ringing state (Ring = 5 V, Test-In = 0 V) to the idle/talk state (Ring = 0 V, Test-In=0 V). After 25 ms, release TSD to return switch control to the input pins which will set the idle talk state. When using the CPC7584 in this mode, forcing TSD to ground overrides the input pins and force an all off state. Setting TSD to +5 V allows switch control via the logic input pins. However, setting TSD to +5 V also disables the thermal shutdown mechanism. This is not recommended. Therefore, to allow switch control via the logic input pins, allow TSD to float. When using TSD as an input, the two recommended states are 0 (overrides logic input pins and forces all off state) and float (allows switch control via logic input pins and the thermal shutdown mechanism is active). This may require use of an open-collector buffer. State INRINGING INTEST TSD Timing Break Switches Ringing Return Switch (SW3) Ringing Switch (SW4) Test Switches Ringing 1 0 Floating - Open Closed Closed Open Make- before- break 0 0 Floating SW4 waiting for next zero-current crossing to turn off. Maximum time is one-half of ringing. In this transition state, current that is limited to the dc break switch current limit value will be sourced from the ring node of the SLIC. Closed Open Closed Open T alk 0 0 Floating Zero-cross current has occurred Closed Open Open Open State INRINGING INTEST TSD Timing Break Switches Ringing Return Switch (SW3) Ringing Switch (SW4) Test Switches Ringing 1 0 Floating - Open Closed Closed Open All-off 1 1 Floating Hold this state for at least 25 ms. SW4 waiting for zero current to turn off. Open Open Closed Open SW4 has opened. Open T alk 0 0 Floating Close Break Switches Closed Open Open Open

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2.3 Ring Access Switch Zero-Cross Current Turn Off

After the application of a logic input to turn SW4 off, the ring access switch is designed to delay the change in state until the next zero-crossing. Once on, the switch requires a zero-current cross to turn off, and therefore should not be used to switch a pure DC signal. The switch will remain in the on state no matter what logic input until the next zero crossing. For proper operation, pin 12 (R RING) should be connected using proper impedance to a ring generator or other AC source. These switching characteristics will reduce and possibly eliminate overall system impulse noise normally associated with ringing access switches. The attributes of ringing access switch SW4 may make it possible to eliminate the need for a zero-cross switching scheme. A minimum impedance of 300 Ω in series with the ring generator is recommended.

2.4 Power Supplies

Both a +5 V supply and battery voltage are connected to the CPC7584. CPC7584 switch state control is powered exclusively by the +5 V supply. As a result, the CPC7584 exhibits extremely low power dissipation during both active and idle states. The battery voltage is not used for switch control but rather as a reference for the integrated secondary protection circuitry. The integrated SCR is designed to trigger when pin 3 (T BAT) or pin 14 (RBAT) drops 2 to 4 V below the battery. This trigger prevents a fault induced overvoltage event at the TBAT or RBAT nodes.

2.5 Battery Voltage Monitor

The CPC7584 also uses the voltage reference to monitor battery voltage. If battery voltage is lost, the CPC7582BC immediately enters the all-off state. It remains in this state until the battery voltage is restored. The device also enters the all-off state if the battery voltage rises above –10 V and remains in the all-off state until the battery voltage drops below –15 V. This battery monitor feature draws a small current from the battery (less than 1 mA typical) and will add slightly to the device’s overall power dissipation.

2.6 Protection

2.6.1 Diode Bridge/SCR

The CPC7584 uses a combination of current limited break switches, a diode bridge/SCR clamping circuit, and a thermal shutdown mechanism to protect the SLIC device or other associated circuitry from damage during line transient events such as lightning. During a positive transient condition, the fault current is conducted through the diode bridge to ground. Voltage is clamped to the diode drop above ground. During a negative transient of 2 to 4 V more negative than the battery, the SCR conducts and faults are shunted to ground via the SCR and diode bridge. In order for the SCR to crowbar or foldback, the on voltage (see “Protection Circuitry Electrical Specifications” on page 8) of the SCR must be less negative than the battery reference voltage. If the battery voltage is less negative the SCR on voltage, the SCR will not crowbar, however it will conduct fault currents to ground. For power induction or power-cross fault conditions, the positive cycle of the transient is clamped to the diode drop above ground and the fault current directed to ground. The negative cycle of the transient will cause the SCR to conduct when the voltage exceeds the battery reference voltage by two to four volts, steering the current to ground.

2.6.2 Current Limiting function

If a lightning strike transient occurs when the device in the talk/idle state, the current is passed along the line to the integrated protection circuitry and limited by the dynamic current limit response of break switches SW1 and SW2. When a 1000V 10/1000 pulse (LSSGR lightning) is applied to the line though a properly clamped external protector, the current seen at pins 2 BAT) and pin 15 (RBAT) will be a pulse with a typical magnitude of 2.5 A and a duration of less than 0.5 ms. If a power-cross fault occurs with the device in the talk/idle state, the current is passed though break switches SW1 and SW2 on to the integrated protection circuit and is limited by the dynamic DC current limit response of the two break switches. The DC current limit, specified over temperature, is between 80 mA and 425 mA, and the circuitry has a negative temperature coefficient. As a result, if the device is subjected to extended heating due to power cross fault, the measured current at pin 2 (T BAT) and pin 15 (RBAT) will decrease as the device temperature increases. If the device temperature rises sufficiently, the temperature shutdown mechanism will activate and the device will default to the all-off state.

2.7 Temperature Shutdown

The thermal shutdown mechanism will activate when the device temperature reaches a minimum of 110° C, placing the device in the all-off state regardless of logic input. During thermal shutdown mode, pin 7 (TSD) will read 0 V. Normal output of TSD is +V DD.

Rev. B www.clare.com 13 Preliminary If presented with a short duration transient such as a lightning event, the thermal shutdown feature will typically not activate. But in an extended power-cross transient, the device temperature will rise and the thermal shutdown will activate forcing the switches to the all-off state. At this point the current measured at pin 3 (T BAT) and pin 14 (RBAT) will drop to zero. Once the device enters thermal shutdown it will remain in the all-off state until the temperature of the device drops below the activation level of the thermal shutdown circuit. This will return the device to the state prior to thermal shutdown. If the transient has not passed, current will flow at the value allowed by the dynamic DC current limiting of the switches and heating will begin again, reactivating the thermal shutdown mechanism. This cycle of entering and exiting the thermal shutdown mode will continue as long as the fault condition persists. If the magnitude of the fault condition is great enough, the external secondary protector could activate and shunt all current to ground. The thermal shutdown mechanism of the CPC7584 can be disable by applying +V DD to pin 7 (TSD).

2.8 External Protection Elements

The CPC7584 requires only one overvoltage secondary protector on the loop side of the device. The integrated protection feature described above negates the need for protection on the line side. The secondary protector limits voltage transients to levels that do not exceed the breakdown voltage or input-output isolation barrier of the CPC7584. A foldback or crowbar type protector is recommended to minimize stresses on the device. Consult Clare’s application note, AN-100, “Designing Surge and Power Fault Protection Circuits for Solid State Subscriber Line Interfaces” for equations related to the specifications of external secondary protectors, fused resistors and PTCs.

2.9 Data Latch

The CPC7584 has an integrated data latch. The latch operation is controlled by logic-level input pin 11 (LATCH). The data input of the latch is pin 10 (IN RING) and pin 9 (INTEST -IN) of the device while the output of the data latch is an internal node used for state control. When LATCH control pin is at logic 0, the data latch is transparent and data control signals flow directly through to state control. A change in input will be reflected in a change is switch state. When LATCH control pin is at logic 1, the data latch is active and a change in input control will not affect switch state. The switches will remain in the position they were in when the LATCH changed from logic 0 to logic 1 and will not respond to changes in input as long as the latch is at logic 1. The TSD input is not tied to the data latch. Therefore, TSD is not affected by the LATCH input and the TSD input will override state control via pin 10 (IN RING) and pin 9 (INTEST -IN) and the LATCH.

14 www.clare.com Rev. B Preliminary 3. Manufacturing Information

3.1 Mechanical Dimensions

3.1.1 SOIC

3.1.2 MLP

7.40 MIN / 7.60 MAX (.291 MIN / .299 MAX) 0.23 MIN / 0.32 MAX (.0091 MIN / .0125 MAX) 1.27 (.050) 2.44 MIN / 2.64 MAX (.096 MIN / .104 MAX) 0.51 MIN / 1.01 MAX (.020 MIN / .040 MAX) 10.11 MIN / 10.51 MAX (.398 MIN / .414 MAX) 0.36 MIN / 0.46 MAX (.014 MIN / .018 MAX) 10.11 MIN / 10.31 MAX (.398 MIN / .406 MAX)

16 Pin SOIC (JEDEC Package)

0.55 0.80 0.23 0.55 0.33 (+0.07, -0.05) 0.2 0.80 (±0.10) 0.02 (+0.05, -0) Terminal Tip INDEX AREA SEATING PLANE EXPOSED PAD TOP VIEW SIDE VIEW BOTTOM VIEW 4.0 (±0.05) 6.0 (±0.05) 0.55 (±0.1) Dimensions in mm

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3.2 Printed-Circuit Board Layout

3.2.1 SOIC

3.2.2 MLP

3.3 Tape and Reel Packaging

3.3.1 SOIC

3.4 Soldering

3.4.1 Moisture Reflow Sensitivity

Clare has characterized the moisture reflow sensitivity of LCAS products using IPC/JEDEC standard J-STD-020A. Moisture uptake from atmospheric humidity occurs by diffusion. During the solder reflow process, in which the component is attached to the PCB, the whole body of the component is exposed to high process temperatures. The combination of moisture uptake and high reflow soldering PC Board Pattern (Top View) 1.193 (.047) 9.728 ± .051 (.383 ± .002) .787 (.031) 1.270 (.050) 0.65 6.1 0.38 0.65 0.38 0.47 0.66 5.75 6.13 0.75 on center 5.35 on center Detail A Detail A All dimensions in mm Not drawn to scale 16.00 7.50 R = .50 2.30 1.30 6.80 3.00 2.00 4.00 2.001.50 12.00 6.50 2.70 A0 = B0 = K0 = K1 = NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS AND CARRY TOLERANCES OF EIA STANDARD 481-2. 2. THE TAPE COMPLIES WITH ALL "NOTES" FOR CONSTANT DIMENSIONS LISTED ON PAGE 5 OF EIA-481-2. 6.5 mm 10.3 mm 2.3 mm 2.7 mm

For additional information please visit www.clare.com Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set forth in Clare’s Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty relating to its products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of Clare’s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its product s at any time without notice. Specifications: DS-CPC7584 - R0B © Copyright 2004, Clare, Inc. All rights reserved. Printed in USA. 1/23/2004 temperatures may lead to moisture induced delamination and cracking of the component. To prevent this, this component must be handled in accordance with IPC/JEDEC standard J-STD-020A per the labeled moisture sensitivity level (MSL), level 1 for the SOIC package, and level 2 for the MLP package.

3.4.2 Reflow Profile

The maximum ramp rates, dwell times, and temperatures of the assembly reflow profile should not exceed those specified in IPC/JEDEC standard J-STD-020A, which were used to determine the moisture sensitivity level of this component.

3.5 Washing

Clare does not recommend ultrasonic cleaning of LCAS parts.