CPC7583BATR

CPC7583 CLARE | Alldatasheet

Document overview

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Technical content

Features

• Small 28 pin surface mount SOIC package
• Monolithic IC reliability
• Low matched RDSON
• Eliminates the need for zero cross switching
• Flexible switch timing to transition from ringing mode to idle/talk mode
• Clean, bounce free switching
• Tertiary protection consisting of integrated current limiting, thermal shutdown and SLIC protection
• 5V operation with power consumption <10mW
• Intelligent battery monitor
• Latched logic level inputs, no drive circuitry
• Pin to pin compatible to the Lucent 7583 family Block Diagram

Applications

• Central office (CO)
• Digital Loop Carrier (DLC)
• PBX Systems
• Digitally Added Main Line (DAML)
• Hybrid Fiber Coax (HFC)
• Fiber in the Loop (FITL)
• Pair Gain System
• Channel Banks CPC7583

Ordering Information

Part # Description CPC7583BA 10 Pole with protection SCR CPC7583BB 10 Pole without protection SCR CPC7583BC 10 Pole extra logic state with protection SCR CPC7583BD 10 Pole extra logic state without protection SCR CPC7583BATR Tape and Reel Version CPC7583BBTR Tape and Reel Version CPC7583BCTR Tape and Reel Version CPC7583BDTR Tape and Reel Version DS-CPC7583-RE /K52/K31 /K52/K32/K52/K69/K6E/K67 /K54/K49/K50 /K53/K65/K63/K6F/K6E/K64/K61/K72/K79 /K50/K72/K6F/K74/K65/K63/K74/K69/K6F/K6E /K53/K57/K36 /K54 /K65/K73/K74 /K4F/K75/K74 /K53/K57/K31 /K42/K72/K65/K61/K6B /K53/K57/K31/K30 /K54 /K65/K73/K74 /K49/K6E /K53/K57/K33 /K52/K69/K6E/K67/K69/K6E/K67 /K52/K65/K74/K75/K72/K6E /K53/K57/K37 /K52/K69/K6E/K67/K69/K6E/K67 /K54 /K65/K73/K74 /K52/K65/K74/K75/K72/K6E /K53/K57/K38 /K52/K69/K6E/K67/K69/K6E/K67 /K54 /K65/K73/K74 /K53/K57/K34 /K52/K69/K6E/K67/K69/K6E/K67 /K41/K63/K63/K65/K73/K73 /K54 /K42/K41 /K54 /K28/K36/K29 /K52 /K42/K41 /K54 /K28/K32/K33/K29 /K52/K69/K6E/K67 /K47/K65/K6E/K65/K72/K61/K74/K6F/K72 /K56 /K42/K41 /K54 /K52/K65/K66/K65/K72/K65/K6E/K63/K65 /K28/K32/K38/K29 CPC7583BA /K42/K61/K74/K74/K65/K72/K79 /K53/K4C/K49/K43 /K53/K57/K39 /K54 /K65/K73/K74 /K49/K6E /K53/K57/K35 /K54 /K65/K73/K74 /K4F/K75/K74 /K42/K72/K65/K61/K6B /K53/K57/K32 /K53/K43/K52 /K61/K6E/K64/K3 /K54/K52/K49/K50 /K43/K69/K72/K63/K75/K69/K74 /K54 /K4C/K49/K4E/K45 /K28/K37/K29 /K52 /K4C/K49/K4E/K45 /K28/K32/K32/K29 /K54 /K54/K45/K53/K54 /K6F/K75/K74 /K28/K31/K30/K29 /K54 /K52/K49/K4E/K47 /K28/K38/K29 /K54 /K54/K45/K53/K54 /K69/K6E /K28/K35/K29 /K52 /K54/K45/K53/K54 /K69/K6E /K28/K32/K34/K29/K52 /K52/K49/K4E/K47 /K28/K32/K30/K29/K52 /K54/K45/K53/K54 /K6F/K75/K74 /K28/K31/K39/K29

of engineering evaluations. Typical values are provided for information purposes only and are not part of the testing requirements. 1 VBAT is used only as a reference for internal protection circuitry. If VBAT rises above -10V, the device will enter an all off state and will remain in the all off state until the battery voltage drops below -15V. Table 1. Break Switch, SW1 and SW2 secondary protection in place. 1 Applied voltage is 100 Vp-p square wave at 100Hz.

Table 2. Ring Return Switch, SW3 secondary protection in place. Table 3. Ringing Access Switch, SW4

Table 4. Loop Access Switches, SW5 and SW6 Table 5. Ringing Test Return Switch SW7

Table 6. Ringing Test Switch SW8

• Choice of secondary protector and series current-limit resistor should ensure these ratings are not exceeded.

Table 7. Test in Switches, SW9 and SW10

Table 8. Additional Electrical Characteristics 1 Temperature shutdown flag (TSD) will be high during normal operation and low during temperature shutdown state. Table 9. Make-Before-Break Operation (Ringing to Idle/Talk Transition)

Table 10. Break-Before-Make Operation (Ringing to Idle/Talk Transition) release TSD to return switch control to the input pins which will set the idle talk state. nism. This is not recommended. Therefore, to allow switch control via the logic INPUT pins, allow TSD to float. Table 11. Electrical Specifications, Protection Circuitry 1 Only for the CPC7583BA and CPC7583BC.

• Passes GR1089 and ITU-T K.20 with appropriate secondary protection in place.

Table 12. Truth Table for the CPC7583BA and CPC7583BB 1 If TSD = 5V, the thermal shutdown mechanism is disabled. If TSD if floating, the thermal shutdown mechanism is active. 2 Forcing TSD to ground overrides the logic input pins and forces an all off state. 7 Ringing generator test state. 8 Simultaneous TESTout and TESTin state.

9 All OFF State

latch to state control. Any changes in INPUT will be reflected in the state of the switches. 0 to logic 1. The switches will not respond to changes in INPUT as long as LATCH is held high.

Table 13. Truth Table for the CPC7583BC and CPC7583BD 1 If TSD = 5V, the thermal shutdown mechanism is disabled. If TSD if floating, the thermal shutdown mechanism is active. 2 Forcing TSD to ground overrides the logic input pins and forces an all off state. 7 Ringing generator test state. 8 Simultaneous TESTout and TESTin state. 10 Simultaneous TESTout - Ring Test state. latch to state control. Any changes in INPUT will be reflected in the state of the switches. 0 to logic 1. The switches will not respond to changes in INPUT as long as LATCH is held high.

www.clare.com10 Rev. E CPC7583 SOG Symbol Description 1F GND Fault ground. 2 NC No Connection. 3 NC No Connection. 4 NC No Connection. 5T TESTin Test (in) access on TIP . 6T BAT Connect to TIP on SLIC side. 7T LINE Connect to TIP on line side. 8 TRING Connect to return ground for ringing generator. 9 NC No connection. 10 T TESTout Test (out) access on TIP . 11 NC No connection.

12 V DD 5V supply

13 T SD Temperature shutdown pin. Can be used as a logic level input or an output. See Tables 9, 10, 12 and13 for more details. As an output, will read 5V when the device is in its operational mod and 0V in the thermal shutdown mode. To disable the thermal shutdown mode mechanism, tie this pin to 5V (not recommended).

14 D GND Digital ground

15 IN TESTout Logic level switch input control. 16 IN RING Logic level switch input control. 17 IN TESTin Logic level switch input control. 18 LATCH Data input control, active-high, transparent low. 19 R TESTout Test (out) access on RING. 20 R RING Connect to ringing generator. 21 NC No connection. 22 R LINE Connect to RING on line side. 23 R BAT Connect to RING on SLIC side. 24 R TESTin Test (in) access on RING. 25 NC No connection. 26 NC No connection.

27 NC No connection

28 V BAT Battery voltage. Used as a reference for protection circuit. Package Pinout * Only the CPC7583BA and CPC7583BC contain the protection SCR CPC7583 TBAT SW1 SW5 SW9 SW2 SW8 SW10 Control Logic FGND DGND TTESTin INTESTin R TTESTout INTESTout RTESTout TLINE TRING VDD T NC NC NC NC NC NC NC NC NC SD VBAT RBAT RLINE RRING LATCH INRING SW7 SW6 19 281 SW3 SW4 SCR and TRIP CKT

www.clare.com 11Rev. E Functional Description Introduction The CPC7583 has eight distinct states. Please consult the truth tables in table 12 and 13 for version differences.

• Idle/talk state (line break switches SW1, and SW2 closed). All other switches open.
• Ringing state, (ringing switches SW3, SW4 closed). All other switches open.
• Loop access (loop access switches SW5, SW6 closed). All other switches open.
• Ring generator test state (SW7, SW8 closed). All other switches open.
• SLIC test state Testin switches closed (SW9, SW10).
• Simultaneous Loop and SLIC access state. (SW9, SW10, SW5 and SW6 closed). All other switches open.
• Simultaneous test out and ring test (SW5, SW6, SW7, SW8 closed). All other switches open on the “BC” abd “BD” version.
• All Off state (all switches open). The CPC7583 offers break-before-make and make-before- break switching with simple logic level input control. Solid state switch construction means no impulse noise is gen- erated when switching during ring cadence or ring trip, thus eliminating the need for external “zero cross” switching cir- cuitry. State control is via logic level input so no additional driver circuitry is required. The line break switches SW1 and SW2 are linear switches that have exceptionally low RDS ON and excellent matching characteristics. The ring- ing access switch SW4 has a breakdown voltage rating of >480V which is sufficiently high, with proper protection, to prevent breakdown in the presence of a transient fault con- dition. (i.e., passing the transient on to the ring generator) Integrated into the CPC7583 is a diode bridge clamping circuit, current limiting and thermal shutdown mechanism to provide protection to the SLIC device during a fault con- dition. Positive and negative surges are reduced by the current limiting circuitry and steered to ground via diodes. Power cross transients are also reduced by the current lim- iting and thermal shutdown circuits. To protect the CPC7583 from an overvoltage fault condi- tion, use of a secondary protector is required. The sec- ondary protector must limit the voltage seen at the tip and ring terminals to a level below the max breakdown volt- age of the switches. To minimize the stress on the solid- state contacts, use of a foldback or crowbar type sec- ondary protector is recommended. With proper selection of the secondary protector, a line card using the CPC7583 will meet all relevant ITU, LSSGR, FCC or UL protection requirements. The CPC7583 operates from a +5V supply only. This gives the device extremely low idle and active power dissipation and allows use with virtually any range of battery voltage. A battery voltage is also used by the CP7583 as a refer- ence for the integrated protection circuit. In the event of a loss of battery voltage, the CPC7583 will enter an “all off” state. Switch Timing The CPC7583 provides, when switching from the ringing state to the idle/talk state, the ability to control the timing when the ringing access switches SW3 and SW4 are re- leased relative to the state of the line break switches SW1 and SW2 using simple logic level input. This is referred to as a “make before break” or “break before make” opera- tion. When the line break switch contacts (SW1, SW2) are closed (or made) before the ringing access switch contact (SW3, SW4) is opened (or broken), this is referred to a ‘make-before-break’ operation. Break-before-make opera- tion occurs when the ringing access contact (SW3, SW4) is opened (broken) before the line break switch contacts (SW1, SW2) are closed (made). With the CPC7583 the “make before break” and “break before make” operations can easily be selected by applying logic level inputs to IN TESTout, INRING and INTESTin of the device. The logic sequences for either mode of operation are given in Tables 9 and 10. Logic states and explanations are given in Tables 12 and 13. Break-before make operation can also be achieved using pin 13 (TSD) as an input. In table 10 lines 2 and 3 it is possible to induce the switches to “all off” by grounding pin 13 (TSD) instead of apply logic input to the pins. This has the effect of overriding the logic inputs and forcing the de- vice to the “all off” state. Hold this input state for 25ms. During this hold period, toggle the inputs from the ringing state to the idle/talk state. After the 25ms release pin 13 (TSD) to return the switch control to the input IN TESTout, INRING, INTESTin and reset the device to the idle/talk state. Setting pin 13 (TSD) to +5V will allow switch control using the logic inputs. This setting, however, will also disable the thermal shutdown circuit and is therefore not recommended. When using logic controls via the input pins (IN TESTout, INRING and INTESTin), pin 13 (TSD) should be allowed to float. As a result the two recommended states when using pin 13

www.clare.com12 Rev. E CPC7583 (TSD) as a control are 0 which forces the device to the “all off state” or float which allow logic inputs to remain active. This may require use of an open collector buffer. Ring Access Switch Zero Cross Current Turn Off After the application of a logic input to turn SW4 off, the ring access switch is designed to delay the change in state until the next zero crossing. Once on, the switch requires a zero current cross to turn off and therefore should not be used to switch a pure DC signal. The switch will remain in the on state no matter what logic input until the next zero crossing. These switching characteristics will reduce and possibly eliminate overall system impulse noise normally associated with ringing access switches. The attributes of ringing access switch may make it possible to eliminate the need for a zero cross switching scheme. A minimum impedance of 300 Ω in series with the ring generator is recommended. Power Supplies Both a +5V supply and battery voltage are connected to the CPC7583. CPC7583 switch state control is powered exclusively by the +5V supply. As a result, the CPC7583 exhibits extremely low power dissipation during both active and idle states. Battery Voltage Monitor The CPC7583 also uses the voltage reference to monitor battery voltage. If battery voltage is lost, the CPC7583 will immediately enter the “all off” state and remain in this state until the battery voltage is restored. The device will also enter the “all off” state if the battery voltage rises above – 10V and will remain there until the battery voltage drops below –15V. This battery monitor feature draws a small current from the battery (<1µA) and will add slightly to the device’s overall power dissipation. Protection Diode Bridge/SCR The CPC7583 uses a combination of current limited break switches, a diode bridge/SCR clamping circuit and a ther- mal shutdown mechanism to protect the SLIC device or other associated circuitry from damage during line tran- sient events such as lightning. During a positive transient condition, the fault current is conducted through the diode bridge and to ground. During a negative transient of two or four volts more negative than the battery, the SCR con- ducts and faults are shunted to ground via the SCR and diode bridge. Also, in order for the SCR to crowbar or foldback, the on voltage (see Table 11) of the SCR must be less negative than the battery reference voltage. If the battery voltage is less negative the SCR on voltage, the SCR will not crow- bar, however it will conduct fault currents to ground. For power induction or power cross fault conditions, the positive cycle of the transient is clamped to the diode drop above ground and the fault current directed to ground. The negative cycle of the transient will cause the SCR to con- duct when the voltage exceeds the battery reference volt- age by two to four volts, steering the current to ground. Current Limiting function If a lightning strike transient occurs when the device in the talk/idle state, the current is passed along the line to the integrated protection circuitry and limited by the dynamic current limit response of break switches SW1 and SW2. When a 1000V 10x1000 pulse (LSSGR lightning) is ap- plied to the line though a properly clamped external pro- tector, the current seen at pins 6 (T BAT) and pin 23 (RBAT) will be a pulse with a typical magnitude and duration of 2.5A and < 0.5ms. If a power cross fault occurs with device in the talk/idle state, the current is passed though the break switches SW1 and SW2 on to the integrated protection circuit and is lim- ited by the dynamic DC current limit response of the two break switches. The DC current limit, specified over tem- perature, is between 80mA and 400mA and the circuitry has a negative temperature coefficient. As a result, if the device is subjected to extended heating due to power cross fault, the measured current at pin 6 (T BAT) and pin 23 (RBAT) will decrease as the device temperature increases. If the device temperature rises sufficiently, the temperature shut- down mechanism will activate and the device will default to the “all off” state. Temperature Shutdown The thermal shutdown mechanism will activate when the device temperature reaches a minimum of 110ϒC placing the device in the “all off” state regardless of logic input. During this thermal shutdown mode, pin 13 (TSD) will read 0V. Normal output of TSD is +V DD If presented with a short duration transient such as a light- ning event, the thermal shutdown feature will not typically activate. But in an extended power cross transient, the device temperature will rise and the thermal shutdown will activate forcing the switches to an “all off” state. At this point the current measured at pin 6 (T BAT) and pin 23 (RBAT) will drop to zero. Once the device enters thermal shut- down it will remain in the “all off” state until the temperature of the device drops below the activation level of the ther- mal shutdown circuit. This will return the device to the state prior to thermal shutdown. If the transient has not passed, current will flow at the value allowed by the dynamic DC current limiting of the switches and heating will begin again, reactivating the thermal shutdown mechanism. This cycle

www.clare.com 13Rev. E of entering and exiting the thermal shutdown mode will continue as long as the fault condition persists. If the mag- nitude of the fault condition is great enough, the external secondary protector could activate and shunt all current to ground. The thermal shutdown mechanism of the CPC7583 can be disable by applying +V DD to pin 13 (TSD) External Protection Elements The CPC7583 requires only one overvoltage secondary pro- tector on the loop side of the device. The integrated protec- tion feature described above negates the need for protection on the line side. The purpose of the secondary protector is to limit voltage transients to levels that do not exceed the break- down voltage or input-output isolation barrier of the CPC7583. A foldback or crowbar type protector is recommended to mini- mize stresses on the device. Consult Clare’s app note, AN-100, “Designing Surge and Power Fault Protection Circuits for Solid State Subscriber Line Interfaces” for equations related to the specifications of external secondary protectors, fused resistors, and PTCs. Data Latch The CPC7583 has an integrated data latch. The latch op- eration is controlled by logic level input pin 18 (LATCH). The data input of the latch is pin 15 (IN TESTout), pin 16 (INRING) and pin 17 (IN TESTin) of the device while the output of the data latch is an internal node used for state control. When LATCH control pin is at logic 0, the data latch is transpar- ent and data control signals flow directly through to state control. A change in input will be reflected in a change is switch state. When LATCH control pin is at logic 1, the data latch is now active and a change in input control will not affect switch state. The switches will remain in the po- sition they were in when the LATCH changed from logic 0 to logic 1 and will not respond to changes in input as long as the latch is at logic 1. In addition, TSD input is not tied to the data latch. Therefore, TSD is not affected by the LATCH input and TSD input will override state control via pin 15 (IN TESTout), pin 16 (IN RING) and pin 17 (IN TESTin) and the LATCH.

www.clare.com14 Rev. E CPC7583 Dimensions mm (Inches) Mechanical Dimensions

28 Pin SOIC

1.27 Typ

(.050 Typ) 2.54+/-.127 (.100+/-.005) 7.468+/-.127 (.294+/-.005) 10.312+/-.051 (.406+/-.003) .250 Typ (.032+/-.004) 3 - 7o o 18.034+/-.127 (.710+/-.005) .330 x 45 MAX (.013 x 45 MAX)o o

www.clare.com 15Rev. E Notes:

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