CPC7581BCTR

CPC7581_1 CLARE | Alldatasheet

Document overview

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Technical content

Features

• Small 16-pin SOIC or DFN package
• DFN package printed-circuit board footprint is 60 percent smaller than the SOIC version, 40 percent smaller than fourth generation EMR solutions.
• Monolithic IC reliability
• Low, matched R ON
• Eliminates the need for zero-cross switching
• Flexible switch timing for transition from ringing mode to idle/talk mode.
• Clean, bounce-free switching
• Tertiary protection consisting of integrated current limiting, thermal shutdown for SLIC protection
• 5 V operation with power consumption < 10 mW
• Intelligent battery monitor
• Latched logic-level inputs, no external drive circuitry required
• SOIC package pin-compatible with Legerity product

Applications

• Central office (CO)
• Digital Loop Carrier (DLC)
• PBX Systems
• Digitally Added Main Line (DAML)
• Hybrid Fiber Coax (HFC)
• Fiber in the Loop (FITL)
• Pair Gain System
• Channel Banks

Description

The CPC7581 is a monolithic solid-state four-pole switch in a 16-pin package. It provides the necessary functions to replace a 2-Form-C electromechanical relay on traditional analog and integrated voice and data (IVD) line cards found in central office, access, and PBX equipment. The CPC7581 contains solid-state switches for tip and ring lead line break and ringing injection/ringing return. The device requires only a +5 V supply and offers break-before-make and make-before-break operation using logic-level inputs. The CPC7581xA versions include an SCR that provides protection to the SLIC and subsequent circuitry during a fault condition. The CPC7581xC versions are functionally identical to the CPC7581xA versions, but with higher SCR hold current.

Ordering Information

Figure 1. CPC7581 Block Diagram

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R05 www.clare.com 3 1. Specifications 1.1 Package Pinout 1.2 Pinout CPC7581 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 TBAT DD FGND TLINE NC NC TRINGING V TSD VBAT RBAT RLINE NC RRINGING LATCH RINGINGIN DGND Pin Name Description

1 FGND Fault ground

2 TBA T Tip lead of the SLIC

3 TLINE Tip lead of the line side

4 NC No connection

5 NC No connection

6 TRINGING Ringing generator return

7 VDD +5 V supply

8 TSD T emperature shutdown pin

9 DGND Digital ground

10 INRINGING Logic control input

11 LA TCH Data latch enable control input

12 RRINGING Ringing generator source

13 NC No connection

14 RLINE Ring lead of the line side

15 RBA T Ring lead of the SLIC

16 VBA T Battery supply

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1.3 Absolute Maximum Ratings

Absolute maximum electrical ratings are at 25°C. Absolute maximum ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this data sheet is not implied. Exposure of the device to the absolute maximum ratings for an extended period may degrade the device and affect its reliability.

1.4 ESD Rating

1.5 General Conditions

Unless otherwise specified, minimum and maximum values are production testing requirements. Typical values are characteristic of the device at 25°C and are the result of engineering evaluations. They are provided for informational purposes only and are not part of the manufacturing testing requirements. Specifications cover the operating temperature range T A = -40°C to +85°C. Also, unless otherwise specified all testing is performed with VDD = +5Vdc, logic low input voltage is 0Vdc and logic high input voltage is +5Vdc. Parameter Minimum Maximum Unit +5 V power supply (VDD) -0.3 7 V Battery Supply - -85 V DGND to FGND Separation -5 +5 V Logic input voltage -0.3 VDD + 0.3 V Logic input to switch output isolation -3 2 0 V Switch open-contact isolation (SW1, SW2, SW3) -3 2 0 V Switch open-contact isolation (SW4) -4 6 5 V Operating relative humidity 5 95 % Operating temperature -40 +110 °C Storage temperature -40 +150 °C ESD Rating (Human Body Model) 1000 V

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1.6 Switch Specifications

1.6.1 Break Switches, SW1 and SW2

Parameter Conditions Symbol Minimum Typical Maximum Unit Off-state leakage current +25° C VSW (differential) = -320 V to gnd VSW (differential) = +260 V to -60 V ISW - 0.1 1 μA+85° C VSW (differential) = -330 V to gnd VSW (differential) = +270 V to -60 V 0.3 -40° C VSW (differential) = -310 V to gnd VSW (differential) = +250 V to -60 V 0.1 RON +25° C ISW = ±10 mA, ±40 mA, RBA T and TBA T= -2 V RON - 14.5 - Ω +85° C 20.5 28 -40° C 10.5 - RON match Per on-resistance test condition of SW1, SW2. Magnitude R ON SW1-RON SW2 Δ RON - 0.15 0.8 DC current limit +25° C VSW (on) = ±10 V ISW - 300 - mA+85° C 80 160 - -40° C - 400 425 Dynamic current limit (t ≤ 0.5 μs) Break switches on, all other switches off, apply ±1 kV at 10x1000 μs pulse, with appropriate protection in place. -2 . 5- A Logic input to switch output isolation +25° C VSW (TLINE, RLINE) = ±320 V , logic inputs = gnd ISW - 0.1 1 μA+85° C VSW (TLINE, RLINE) = ±330 V , logic inputs = gnd 0.3 -40° C VSW (TLINE, RLINE) = ±310 V , logic inputs = gnd 0.1 dv/dt sensitivity - - 200 - V/ μs

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1.6.2 Ringing Return Switch, SW3

Parameter Conditions Symbol Minimum Typical Maximum Unit Off-state leakage current +25° C VSW (differential) = -320 V to gnd VSW (differential) = +260 V to -60 V ISW - 0.1 1 μA+85° C VSW (differential) = -330 V to gnd VSW (differential) = +270 V to -60 V 0.3 -40° C VSW (differential) = -310 V to gnd VSW (differential) = +250 V to -60 V 0.1 RON +25° C ISW (on) = ±0 mA, ±10 mA R ON - 60 - Ω+85° C 85 100 -40° C 45 - DC current limit +25° C V SW (on) = ±10 V ISW - 135 mA+85° C 70 85 -40° C 210 Dynamic current limit (t ≤ 0.5 μs) Ringing switches on, all other switches off, apply ±1 kV at 10x1000 μs pulse, with appropriate protection in place. 2.5 A Logic input to switch output isolation +25° C VSW (TRINGING, TLINE) = ±320 V , logic inputs = gnd ISW - 0.1 1 μA+85° C VSW (TRINGING, TLINE) = ±330 V , logic inputs = gnd 0.3 -40° C VSW (TRINGING, TLINE) = ±310 V , logic inputs = gnd 0.1 dv/dt sensitivity - - 200 - V/ μs

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1.6.3 Ringing Switch, SW4

Parameter Conditions Symbol Minimum Typical Maximum Unit Off-state leakage current +25° C VSW (differential) = -255 V to +210 V VSW (differential) = +255 V to -210 V ISW 0.05 1 μA+85° C VSW (differential) = -270 V to +210 V VSW (differential) = +270 V to -210 V 0.1 -40° C VSW (differential) = -245 V to +210 V VSW (differential) = +245 V to -210 V 0.05 On Voltage ISW (on) = ± 1 mA -1 . 5 3 V Ringing generator current to ground during ringing V DD = 5 V , INRINGING = 0 I RINGING 0.1 0.25 mA On steady-state current* Inputs set for ringing mode ISW - 150 mA Surge current* Ringing switches on, all other switches off, apply ±1 kV at 10x1000 μs pulse, with appropriate protection in place. -- 2 A Release current - IRINGING 300 - μA RON ISW (on) = ±70 mA, ±80 mA R ON 10 15 Ω Logic input to switch output isolation +25° C VSW (RRINGING, RLINE) = ±320 V , logic inputs = gnd ISW - 0.1 1 μA+85° C VSW (RRINGING, RLINE) = ±330 V , logic inputs = gnd 0.3 -40° C VSW (RRINGING, RLINE) = ±310 V , logic inputs = gnd 0.1 dv/dt sensitivity - - 200 - V/ μs *Secondary protection and ringing source current limiting must prevent exceeding this parameter.

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1.7 Additional Electrical Characteristics

Parameter Conditions Symbol Minimum Typical Maximum Unit Digital input characteristics Input low voltage - VIL -2 . 2 1 . 5 V Input high voltage - VIH 3.5 2.3 - Input leakage current (high) VDD = 5.5 V , VBA T = -75 V , VIH = 5 V I IH -0 . 11 μAInput leakage current (low) VDD = 5.5 V , VBA T = -75 V , VIL = 0 V I IL -0 . 11 Voltage Requirements VDD - VDD 4.5 5.0 5.5 V VBA T 1 - VBA T -19 -48 -72 V 1VBAT is used only for internal protection circuitry. If VBAT goes more positive than -10 V, the device will enter the all-off state and will remain in the all-off state until the battery goes more negative than -15 V Power requirements Power consumption in talk and all-off states VDD = 5 V , VBA T = -48 V , measure IDD and IBA T P -5 . 5 1 0 mWPower consumption in ringing state 6.5 10 VDD current in talk and all-off states VDD = 5 V , VBA T = -48 V IDD -1 . 1 2 . 0 mAVDD current in ringing state -1 . 3 2 . 0 VBA T current in any state I BA T -0 . 1 1 0 μA Temperature Shutdown Requirements (temperature shutdown flag is active low) Shutdown activation temperature -- 110 125 150 °CShutdown circuit hysteresis 10 - 25 Temperature shutdown requirements are not production tested, but rather guaranteed by design.

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1.8 Protection Circuitry Electrical Specifications

1.9 Truth Table

Parameter Conditions Symbol Minimum Typical Maximum Unit Parameters Related to the Diodes in the Diode Bridge Voltage drop at continuous current (50/

60 Hz)

Apply ± dc current limit of break switches Forward Voltage -2 . 13 V Voltage drop at surge current Apply ± dynamic current limit of break switches Forward Voltage -5- Parameters Related to the Protection SCR Surge current - - - - * A T rigger current T=+25°C I TRIG (CPC7581xA) (CPC7581xC) -m A T=+85°C (CPC7581xA) (CPC7581xC) Hold current T=+25°C IHOLD 110 (CPC7581xA) 135 (CPC7581xC) T=+85°C (CPC7581xA) 110 (CPC7581xC) (CPC7581xA) 115 (CPC7581xC) Gate trigger voltage IGA TE = ITRIGGER** VTBA T or VRBA T VBA T -4 - VBA T -2 V Reverse leakage currentVBA T = -48 V I VBA T -- 1 . 0 μA On-state voltage 0.5 A, t = 0.5 μsV TBA T or VRBA T- -- 3-V *Passes GR1089 and ITU-T K.20 with appropriate secondary protection in place. **VBA T must be capable of sourcing ITRIGGER for the internal SCR to activate. State INRINGING Latch TSD Break Switches Ringing Switches Ta l k 0 0 On Off Ringing 1 Off On Latched X 1 Unchanged All-Off X X 0 Off Off 1 Z = High Impedance. Because TSD has an internal pull up at this pin, it should be controlled with an open-collector or open-drain type device.

10 www.clare.com R05 2. Functional Description

2.1 Introduction

The CPC7581 has three states:

• Talk. Line break switches SW1 and SW2 closed, ringing switches SW3 and SW4 open.
• Ringing. Ringing switches SW3 and SW4 closed, line break switches SW1 and SW2 open.
• All-off. All switches open. See “Truth Table” on page 9 for more information. The CPC7581 offers break-before-make and make-before-break switching from the ringing state to the talk state with simple logic-level input control. Solid-state switch construction means no impulse noise is generated when switching during ring cadence or ring trip, eliminating the need for external zero-cross switching circuitry. State control is via logic-level input so no additional driver circuitry is required. The line break switches SW1 and SW2 are linear switches that have exceptionally low R ON and excellent matching characteristics. The ringing switch SW4 has a breakdown voltage rating of 465V @ 25°C. This is sufficiently high, with proper protection, to prevent breakdown in the presence of a transient fault condition (i.e., passing the transient on to the ringing generator). Integrated into the CPC7581 is a over voltage clamping circuit, active current limiting, and a thermal shutdown mechanism to provide protection to the SLIC device during a fault condition. Positive and negative surges are reduced by the current limiting circuitry and hazardous potentials are steered to ground via diodes and, in CPC7581xA and CPC7581xC parts, an integrated SCR. Power-cross potentials are also reduced by the current limiting and thermal shutdown circuits. To protect the CPC7581 from an overvoltage fault condition, the use of a secondary protector is required. The secondary protector must limit the voltage seen at the tip and ring terminals to a level below the maximum breakdown voltage of the switches. To minimize the stress on the solid-state contacts, use of a foldback or crowbar type secondary protector is recommended. With proper selection of the secondary protector, a line card using the CPC7581 will meet all relevant ITU, LSSGR, TIA/EIA and IEC protection requirements. The CPC7581 operates from a +5 V supply only. This gives the device extremely low idle and active power consumption and allows use with virtually any range of battery voltage. Battery voltage is also used by the CPC7581 as a reference for the integrated protection circuit. In the event of a loss of battery voltage, the CPC7581 enters the all-off state.

2.2 Switch Logic

The CPC7581 provides, when switching from the ringing state to the talk state, the ability to control the release timing of the ringing switches SW3 and SW4 relative to the state of the line break switches SW1 and SW2 using simple logic-level input. This is called make-before-break or break-before-make operation. When the line break switch contacts (SW1 and SW2) are closed (or made) before the ringing switch contacts (SW3 and SW4) are opened (or broken), this is called make-before-break operation. Break-before-make operation occurs when the ringing contacts (SW3 and SW4) are opened (broken) before the line break contacts (SW1 and SW2) are closed (made). To use make-before-break ringing switch release timing, de-assert IN RINGING during ringing. This causes the operational sequence shown in “Make- Before-Break Operation Logic Table (Ringing to Talk Transition)” on page 11 to occur.

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2.2.1 Make-Before-Break Operation Logic Table (Ringing to Talk Transition)

To use break-before-make ringing switch release timing, assert TSD during ringing. This causes the operational sequence shown in “Break-Before-Make Operation Logic Table (Ringing to Talk Transition)” on page 11 to occur.

2.2.2 Break-Before-Make Operation Logic Table (Ringing to Talk Transition)

Logic states and explanations are given in “Truth Table” on page 9.

2.3 Data Latch

The CPC7581 has an integrated data latch. The latch operation is controlled by logic-level input pin 11 (LATCH). The data input of the latch is pin 10 (IN RINGING), while the output of the data latch is an internal node used for state control. When the LATCH control pin is at logic 0, the data latch is transparent and data control signals flow directly through to state control. A change in input will be reflected in a change is switch state. When the LATCH control pin is at logic 1, the data latch is active and a change in input control will not affect switch state. The switches will remain in the position they were in when the LATCH changed from logic 0 to logic 1 and will not respond to changes in input as long as the latch is at logic 1. The T SD input is not tied to the data latch. Therefore, TSD is not affected by the LATCH input and the TSD input will override state control.

2.4 TSD

The thermal shutdown mechanism activates when the device die temperature reaches a minimum of 110° C, placing the device in the all-off state regardless of logic input. During thermal shutdown mode, pin 8 SD) will read a nominal 0 V. Normal output of TSD is typically equal to VDD. If presented with a short duration transient such as a lightning event, the thermal shutdown feature will typically not activate. But in an extended power-cross event, the device temperature will rise and the thermal shutdown will activate forcing the switches to the all-off state. At this point the current measured through the break switches (SW1 and SW2) will drop to zero. Once the device enters thermal shutdown it will remain in the all-off state until the temperature of the device drops below the de-activation level of the thermal shutdown circuit. This permits the device to State INRINGING Latch TSD Timing Break Switches Ringing Return Switch (SW3) Ringing Switch (SW4) Ringing 1 -O f f On On Make- Before- Break SW4 waiting for next zero-current crossing to turn off. Maximum time is one-half of the ringing cycle. In this transition state, current that is limited to the dc break switch current limit value will be sourced from the ring node of the SLIC. On Off On T alk 0 Zero-cross current has occurred On Off Off State INRINGING Latch TSD Timing Break Switches Ringing Return Switch (SW3) Ringing Switch (SW4) Ringing 1 Z- O f f On On All-off 1 0 Hold this state for one-half of the ringing cycle. SW4 waiting for zero current to turn off. Off Off On All-off 1 Zero current has occu rred. SW4 has opened Off Off Off T alk 0 Z Release break switches On Off Off

12 www.clare.com R05 return to normal operation. If the transient has not passed, current will flow at the value allowed by the dynamic DC current limiting of the switches and heating will begin again, reactivating the thermal shutdown mechanism. This cycle of entering and exiting the thermal shutdown mode will continue as long as the fault condition persists. If the magnitude of the fault condition is great enough, the external secondary protector could activate and shunt all current to ground. The T SD pin is a pull-up current source with a nominal value of 300 μA biased from VDD. For applications using low-voltage logic devices (lower than VDD), Clare recommends the use of an open-drain type output to control TSD. This avoids sinking the TSD bias current to ground during normal operation when the all-off state is not required.

2.5 Ringing Switch Zero-Cross

After the application of a logic input to turn SW4 off, the ringing switch is designed to delay the change in state until the next zero-crossing. Once on, the switch requires a zero-current cross to turn off, and therefore should not be used to switch a pure DC signal. The switch will remain in the on state no matter the logic input until the next zero crossing. These switching characteristics will reduce and possibly eliminate overall system impulse noise normally associated with ringing switches. See Clare application note AN-144, Impulse Noise Benefits of Line Card Access Switches for more information. The attributes of ringing switch SW4 may make it possible to eliminate the need for a zero-cross switching scheme. A minimum impedance of 300 Ω in series with the ring generator is recommended.

2.6 Power Supplies

Both a +5 V supply and battery voltage are connected to the CPC7581. CPC7581 switch state control is powered exclusively by the +5 V supply. As a result, the CPC7581 exhibits extremely low power dissipation during both active and all-off states. The battery voltage is not used for switch control but rather as a supply for the integrated secondary protection circuitry. The integrated SCR is designed to trigger when pin 2 (T BAT) or pin 15 (RBAT) drops 2 to 4 V below the voltage on pin 16 (VBAT). This trigger prevents a fault-induced overvoltage event at the TBAT or RBAT nodes.

2.7 Battery Voltage Monitor

The CPC7581 also uses the VBAT voltage to monitor battery voltage. If system battery voltage is lost, the CPC7581 immediately enters the all-off state. It remains in this state until the battery voltage is restored. The device also enters the all-off state if the system battery voltage goes more positive than –10 V, and remains in the all-off state until the battery voltage goes more negative than –15 V. This battery monitor feature draws a small current from the battery (less than 1 μA typical) and adds slightly to the device’s overall power dissipation. Due to the nature of the internal protection circuitry, the V BAT pin can be biased via potentials applied to TBAT or RBAT. This allows the CPC7581 switches to operate, but offers no transient protection. The supply voltage applied to VBAT should therefor be the same supply voltage applied to the line driver device.

2.8 Protection

2.8.1 Diode Bridge/SCR

The CPC7581 uses a combination of current limited break switches, a diode bridge/SCR clamping circuit, and a thermal shutdown mechanism to protect the SLIC device or other associated circuitry from damage during line transient events such as lightning. During a positive transient condition, the fault current is conducted through the diode bridge to ground via F GND. Voltage is clamped to a diode drop above ground. During a negative transient of 2 to 4 V more negative than the battery, the SCR conducts and faults are shunted to F GND via the SCR or the diode bridge. In order for the SCR to crowbar (or foldback), the on voltage (see “Protection Circuitry Electrical Specifications” on page 9) of the SCR must be less negative than the battery reference voltage. If the battery voltage is less negative than the SCR on voltage, or if the V BAT supply is unable to source the trigger current, the SCR will not crowbar. For power induction or power-cross fault conditions, the positive cycle of the transient is clamped to a diode drop above ground and the fault current directed to ground. The negative cycle of the transient will cause the SCR to conduct when the voltage exceeds the

R05 www.clare.com 13 battery reference voltage by two to four volts, steering the current to ground. Note: The CPC7581xB does not contain the protection SCR.

2.8.2 Current Limiting function

If a lightning strike transient occurs when the device in the talk state, the current is passed along the line to the integrated protection circuitry and limited by the dynamic current limit response of break switches SW1 and SW2. When a 1000V 10x1000 μs pulse (GR-1089-CORE lightning) is applied to the line though a properly clamped external protector, the current seen through the break switches will be a pulse with a typical magnitude of 2.5 A and a duration of less than 0.5 μs. If a power-cross fault occurs with the device in the talk state, the current is passed though the break switches SW1 and SW2 on to the integrated protection circuit and is limited by the dynamic DC current limit response of the two break switches. The DC current limit, specified over temperature, is between 80 mA and 425 mA, and the circuitry has a negative temperature coefficient. As a result, if the device is subjected to extended heating due to power cross fault, the measured current through the break switches (SW1 and SW2) will decrease as the device temperature increases. If the device temperature rises sufficiently, the temperature shutdown mechanism will activate and the device will enter the all-off state.

2.9 External Protection Elements

The CPC7581 requires only overvoltage secondary protection on the loop side of the device. The integrated protection feature described above negates the need for protection on the other (usually SLIC) side. The secondary protector limits voltage transients to levels that do not exceed the breakdown voltage or input-output isolation barrier of the CPC7581. A foldback or crowbar type protector is recommended to minimize stresses on the device. Consult Clare’s application note, AN-100, “Designing Surge and Power Fault Protection Circuits for Solid State Subscriber Line Interfaces” for equations related to the specifications of external secondary protectors, fused resistors and PTCs.

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3.1 Mechanical Dimensions

3.1.1 SOIC

3.1.2 DFN

0.406 ± 0.076 (0.016 ± 0.003) 10.211 ± 0.254 (0.402 ± 0.010) 7.493 ± 0.127 (0.295 ± 0.005) 10.312 ± 0.381 (0.406 ± 0.015)

1.270 TYP

(0.050 TYP) 0.254 MIN / 0.737 MAX X 45° (0.010 MIN / 0.029 MAX X 45°) 0.2311 MIN / 0.3175 MAX (0.0091 MIN / 0.0125 MAX) 0.889 ± 0.178 (0.035 ± 0.007) 0.649 ± 0.102 (0.026 ± 0.004) PIN 1 PIN 16 2.540 ± 0.152 (0.100 ± 0.006) (inches) mm DIMENSIONS NOTES: 1. Coplanarity = 0.1016 (0.004) max. 2. Leadframe thickness does not include solder plating (1000 microinch maximum). 2.337 ± 0.051 (0.092 ± 0.002) 0.203 ± 0.102 (0.008 ± 0.004) EXPOSED MET ALLIC P AD 7.00 ± 0.25 (0.276 ± 0.01) 6.00 ± 0.25 (0.236 ± 0.01) INDEX AREA TOP VIEW SEA TING PLANESIDE VIEW 0.90 ± 0.10 (0.035 ± 0.004) 0.30 ± 0.05 (0.012 ± 0.002) 0.20 (0.008) 4.25 ± 0.05 (0.167 ± 0.002) 0.55 ± 0.10 (0.022 ± 0.004) 6.00 ± 0.05 (0.236 ± 0.002) BOTTOM VIEW Dimensions mm (inch) T erminal Tip 0.80 (0.032) 16

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3.2 Printed-Circuit Board Layout

3.2.1 SOIC

3.2.2 DFN

As the metallic pad on the bottom of the DFN package is connected to the substrate of the die, Clare recommends that no printed circuit board traces or vias be placed under this area. 2.00 (0.079) 1.27 (0.050) mm (inches) DIMENSIONS 9.40 (0.370) 0.60 (0.024) DIMENSIONS mm (inches) 5.80 (0.228) 0.35 (0.014) 1.05 (0.041) 0.80 (0.031)

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3.3 Tape and Reel Packaging

3.3.1 SOIC

3.3.2 DFN

NOTE: Tape dimensions not shown comply with JEDEC Standard EIA-481-2 Tape and Reel Packaging for 16-Pin SOIC Package Dimensions mm (inches) Embossment Embossed Carrier

330.2 Dia

(13.00 Dia) Top Cover Tape Thickness

0.102 Max

(0.004 Max) User Direction of Feed Top Cover Tape P=12.00 (0.47) A0=10.90 + 0.15 (0.429 + 0.010) B0=10.70 + 0.15 (0.421 + 0.01) W=16.00 + 0.30 (0.630 + 0.010) K0=3.20 + 0.15 (0.193 + 0.01) K1=2.70 + 0.15 (0.106 + 0.01) Pin 1 NOTE: Tape dimensions not shown comply with JEDEC Standard EIA-481-2 Dimensions mm (inches) Embossment Embossed Carrier (13.00 Dia) Top Cover Tape Thickness (0.004 Max) K0=1.61 + 0.10 (0.063 + 0.004) B0=7.24 + 0.10 (0.285 + 0.004) W=16.00 + 0.30 (0.630 + 0.012) P=12.00 + 0.10 (0.246 + 0.004) Pin 1 User Direction of Feed

17 www.clare.com For additional information please visit www.clare.com Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set forth in Clare’s Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty relating to its products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of Clare’s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice. Specification: DS-CPC7581-R05 © Copyright 2009, Clare, Inc. All rights reserved. Printed in USA. 10/14/09

3.4 Soldering

3.4.1 Moisture Reflow Sensitivity

Clare has characterized the moisture reflow sensitivity for this product using IPC/JEDEC standard J-STD-020. Moisture uptake from atmospheric humidity occurs by diffusion. During the solder reflow process, in which the component is attached to the PCB, the whole body of the component is exposed to high process temperatures. The combination of moisture uptake and high reflow soldering temperatures may lead to moisture induced delamination and cracking of the component. To prevent this, this component must be handled in accordance with IPC/JEDEC standard J-STD-033 per the labeled moisture sensitivity level (MSL), level 1 for the SOIC package, and level 3 for the DFN package.

3.4.2 Reflow Profile

For proper assembly, this component must be processed in accordance with the current revision of IPC/JEDEC standard J-STD-020. Failure to follow the recommended guidelines may cause permanent damage to the device resulting in impaired performance and/or a reduced lifetime expectancy.

3.5 Washing

Clare does not recommend ultrasonic cleaning of this part. RoHS 2002/95/EC e3Pb