CPC7556 CLARE | Alldatasheet
Document overview
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- PDF pages: 6
Technical content
Features
- Monolithic Construction
- Surface Mount Package
Applications
- Telecommunications Protection Clamp
- High Voltage Multiplexer/Switch
- High Voltage ESD Clamp
Description
100V Diode Bridge with an integrated Over-Voltage Protection (OVP) thyristor uses Clare's High Voltage SOI technology. The CPC7556N integrated diode bridge offers protection from high voltage transients by means of an adjustable voltage clamp. The clamp performs two actions, first to limit the voltage across the diode bridge rectified outputs to a value determined by external resistors and the gate voltage and second to fully discharge the V + to V outputs when the Gate’s trigger threshold is exceeded during the voltage limiting function. The rectified outputs are discharged as a result of the voltage fold-back function of the OVP device. Voltage fold back of the OVP circuit will continue until the current through the protector falls below the hold current threshold. Terminating the gate to V will disable the clamp voltage feature up to the thyristor’s off state voltage.
Ordering Information
CPC7556N 8-Pin SOIC in Tubes (50/Tube) CPC7556NTR 8-Pin SOIC Tape & Reel (1000/Reel) G A/B B/A A K CPC7556 Diode Bridge with Integrated Adjustable OVP Circuit
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1 Specifications
1.1 Package Pinout
1.2 Pin Description
1.3 Absolute Maximum Ratings
Unless Otherwise Specified all electrical ratings are at 25C 1 Derate package for PDISS 120C/W. Absolute maximum ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not implied. G N/C N/C N/C Pin# Name Description 1 Negative Bridge Output 2G Thyristor Gate 3N / C No Connection 4+ Positive Bridge Output 5~ A Input A 6N / C No Connection 7N / C No Connection 8~ B Input B Parameter Symbol Minimum Maximum Units Reverse Voltage VRRM - 120 V Diode Forward Current (Average) IF - 250 mArms Diode Forward Surge Current IFSM -2 A Gate Voltage VGK -4 7 V Gate Current IGK -2 0 m A Overvoltage Current IAK - 120 mA Thyristor Surge Current ITSM -1 . 2 A Fusing Current I2t -0 . 0 2 A2s ESD, Human Body Model -- 3 k V Junction Temperature 1 TJ -+ 1 5 0 C Storage Temperature TSTG -65 +150 C
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1.4 Recommended Operating Conditions
1.5 General Conditions
Typical values are characteristic of the device at 25C and are the result of engineering evaluations. They are provided for information purposes only and are not part of the manufacturing testing requirements. Unless otherwise noted, all electrical specifications are listed for T A=25C.
1.6 DC Electrical Characteristics
Parameter Symbol Minimum Maximum Units Diode Forward Current (Average) IF - 240 mArms Reverse Voltage VR - 100 V Operating Temperature Range TA -40 +125 C Thermal Impedance JA 120 - C/W Parameter Conditions Symbol Minimum Typical Maximum Units Diode Bridge Characteristics: Forward Current - IF - - 240 mArms Diode Forward Voltage Drop IF = 40mA VF 0.83 0.91 0.97 VIF = 250mA 1 1.3 1.49 Reverse Voltage Leakage Current VR = 100V I R --1 A Thyrister Characteristics: Gate Trigger Current V+/ = VAK = 10V , IAK = 110mA IGT 0.5 1.2 1.8 mA Gate Trigger Voltage VGK 2.5 2.8 3.2 V Trigger Current - IAKT -2 5 4 0 m A Hold Current - IH 70 100 - mA Peak Off State Voltage VGK = 0V , IAK = 5 uA V DRM 110 - - V
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1.7 AC Electrical Characteristics
2 Typical Performance Data
Parameter Conditions Symbol Minimum Typical Maximum Units Input Zero Bias Capacitance V+ V = 0V Measured from V~A to V~B C~A~B -4 . 4 1 2 p F Output Zero Bias Capacitance V~A = V~B Measured from V+ to V Bridge Zero Bias Capacitance V+ V = 0V Measured from V~A to V+/- and V~B to V+/- C~A/+, C~A/, C~B/+, C~B/ -8 . 5 1 2 p F Thyristor Peak Pulse Discharge Energy Single Event Over-Voltage Discharge Energy EPP - - 300 mJ Thyristor Repeated Discharge Energy Allowable Repeated Discharge Energy, Rectified 60Hz EAVE -- 1 4 m J 2.8 2.6 2.4 2.0 1.8 1.6 -20 20 60-40 0 40 80 Temperature (ºC) Diode Forward Voltage (V) Bridge Forward Voltage (VF) vs. Temperature 100 1.4 1.2 1.0 IF=250mA IF=40mA 2.2 1.6 1.4 1.2 1.0 0.8 0.6 -20 20 60-40 0 40 80 Temperature (ºC) Diode Forward Voltage (V) Diode Forward Voltage (VF) vs. Temperature 100 0.4 0.2 IF=250mA IF=40mA 152 150 148 146 144 142 -20 20 60-40 0 40 80 Temperature (ºC) Reverse Breakdown Voltage (V) Diode Reverse Breakdown Voltage (VRRM) vs. Temperature 100 140 138 3.0 2.5 2.0 1.5 1.0 -20 20 60-40 0 40 80 Temperature (ºC) Gate Trigger Current (mA) Gate Trigger Current vs. Temperature 100 0.5 3.4 3.2 3.0 2.8 2.6 2.4 -20 20 60-40 0 40 80 Temperature (ºC) Gate Trigger Voltage (V) Gate Trigger Voltage vs. Temperature 100 2.2 2.0
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3 Manufacturing Information
3.1 Moisture Sensitivity
All plastic encapsulated semiconductor packages are susceptible to moisture ingression. Clare classified all of its plastic encapsulated devices for moisture sensitivity according to the latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee proper operation of our devices when handled according to the limitations and information in that standard as well as to any limitations set forth in the information or standards referenced below. Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced product performance, reduction of operable life, and/or reduction of overall reliability. This product carries a Moisture Sensitivity Level (MSL) rating as shown below, and should be handled according to the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033.
3.2 ESD Sensitivity
This product is ESD Sensitive, and should be handled according to the industry standard JESD-625.
3.3 Reflow Profile
This product has a maximum body temperature and time rating as shown below. All other guidelines of J-STD-020 must be observed.
3.4 Board Wash
Clare recommends the use of no-clean flux formulations. However, board washing to remove flux residue is acceptable. The use of a short drying bake may be necessary if a wash is used after solder reflow processes. Chlorine-based or Fluorine-based solvents or fluxes should not be used. Cleaning methods that employ ultrasonic energy should not be used. Device Moisture Sensitivity Level (MSL) Rating CPC7556N MSL 1 Device Maximum Temperature x Time CPC7556N 260 C for 30 seconds RoHS 2002/95/EC e3Pb
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3.6 Tape & Reel Dimensions
(inches MIN / inches MAX) PCB Land Pattern 1.524 / 1.727 (0.060 / 0.068)0.533 REF (0.021 REF) 0.1016 / 0.2489 (0.0040 / 0.0098) 4.801 / 4.978 (0.189 / 0.196) PIN 1 0.356 / 0.457 (0.014 / 0.018) 5.8014 / 6.1976 (0.2284 / 0.2440) 3.810 / 3.988 (0.150 / 0.157)
1.27 TYP
(0.05 TYP) 0.406 / 1.270 (0.016 / 0.050) 0.1905 / 0.2489 (0.0075 / 0.0098) 1.372 / 1.575 (0.054 / 0.062) 1.27 (0.050) 5.30 (0.209) 1.50 (0.059) 0.60 (0.024) Dimensions mm (inches) NOTE: Tape dimensions not shown comply with JEDEC Standard EIA-481-2Embossment Embossed Carrier Top Cover Tape Thickness 0.102 MAX. (0.004 MAX.) 330.2 DIA. (13.00 DIA.) K0= 2.10 (0.083) W=12.00 (0.472)B0=5.30 (0.209) User Direction of Feed A0=6.50 (0.256) P=8.00 (0.315) For additional information please visit our website at: www.clare.com Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in Clare’s Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of Clare’s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice. Specification: DS-CPC7556 - R02 ©Copyright 2011, Clare, Inc. All rights reserved. Printed in USA. 8/17/2011