CPC75282KATR

CPC75282 CLARE | Alldatasheet

Document overview

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Technical content

Features

• Improved Switch dV/dt Immunity of 1500V/μs
• Smart logic for power-up/hot-plug state control
• Small 44-pin TQFP Package
• Monolithic IC reliability
• Low, matched RON
• Eliminates the need for zero-cross switching
• Flexible switch timing to transition from ringing mode to talk mode.
• Clean, bounce-free switching
• Tertiary protection consisting of integrated current limiting, voltage clamping, and thermal shutdown for SLIC protection
• 5V operation with very low power consumption
• Intelligent battery monitor
• Latched logic-level inputs, no external drive circuitry required

Applications

• VoIP Gateways
• Central Office (CO)
• Digital Loop Carrier (DLC)
• PBX Systems
• Digitally Added Main Line (DAML)
• Hybrid Fiber Coax (HFC)
• Fiber In The Loop (FITL)
• Pair Gain System
• Channel Banks

Description

The CPC75282 Dual Line Card Access Switch (LCAS), a member of Clare’s next generation Line Card Access Switch family, is a monolithic solid state device that provides the switching functionality of four 2-Form-C relays in a single, small, economical package. The CPC75282 Dual LCAS device is designed to provide ringing and test access to the telephone loop in Central Office, Digitally Added Main Line, Private Branch Exchange, Digital Loop Carrier, and Hybrid Fiber Coax/Fiber-In-The-Loop analog line card applications. Test access switches provide access to the telephone loop for line (drop) test or message waiting in the PBX application.

Ordering Information

Figure 1. CPC75282 Block Diagram

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R00D www.clare.com 3 1. Specifications

1.1 Package Pinout

1.2 Pinout by Channel

1 “x” denotes channel number

2 An internal pull-down device is included on this node to set

Off as the power-up default state. These pins can also be used as a device reset. If these pins are not used, tie to V DD

1.3 Pinout by Pin Number

21 13 TBA Tx Tip Lead to the SLIC 36 42 TLINEx Tip Lead of the Line Side 38 40 TRINGINGx Ringing Generator Return 37 41 TTESTx Tip Lead of the T est Bus 9, 25 VDD +5V Supply 33 1 RTESTx Ring Lead of the T est Bus 30 4 RRINGINGx Ringing Generator Source 34 44 RLINEx Ring Lead of the Line Side 22 12 RBA Tx Ring Lead to the SLIC 8, 26 VBA T Battery Supply 17 18 LA TCHx Data Latch Enable Control Input 28 6 TSDx T emperature Shutdown Pin 19 20 OFFx All Off Logic Level Input Switch Control 2 11, 23 DGND Digital Ground

14 P1 Logic Control Input

15 P2 Logic Control Input

16 P3 Logic Control Input

24 CFG Operating States Configuration

2, 3, 5, 10, 29, 31, 32, 35, 39, NC Not Connected RTEST2 NC NC RRINGING2 NC TSD2 FGND2 VBAT VDD NC DGND RTEST1 NC NC RRINGING1 NC TSD1 FGND1 VBAT VDD CFG DGND RLINE2 NC TLINE2 TTEST2 TRINGING2 NC TRINGING1 TTEST1 TLINE1 NC RLINE1 RBAT2 TBAT2 LATCH1 LATCH2 OFF1 OFF2 TBAT1 RBAT1 Pin 1 Pin Name Description

1 RTEST2 Ring Lead of the T est Bus

4 RRINGING2 Ringing Generator Source

6 TSD2 T emperature Shutdown Pin

7 FGND2 Fault Ground

9 VDD +5V Supply

12 RBA T2 Ring Lead to the SLIC

13 TBA T2 Tip Lead to the SLIC

17 LA TCH

1 Data Latch Enable Control Input

18 LA TCH2 Data Latch Enable Control Input

19 OFF1 All Off Logic Level Input Switch Control

20 OFF2 All Off Logic Level Input Switch Control

21 TBA T1 Tip Lead to the SLIC

22 RBA T1 Ring Lead to the SLIC

25 VDD +5V Supply

27 FGND1 Fault Ground

28 TSD1 T emperature Shutdown Pin

30 RRINGING1 Ringing Generator Source

32 NC Not Connected

TEST1 Ring Lead of the T est Bus

34 RLINE1 Ring Lead of the Line Side

35 NC Not Connected

LINE1 Tip Lead of the Line Side

37 TTEST1 Tip Lead of the T est Bus

38 TRINGING1 Ringing Generator Return

39 NC Not Connected

40 TRINGING2 Ringing Generator Return

41 TTEST2 Tip Lead of the T est Bus

42 TLINE2 Tip Lead of the Line Side

43 NC Not Connected

LINE2 Ring Lead of the Line Side 9, 25 VDD +5V Supply 11, 23 DGND Digital Ground 8, 26 VBA T Battery Supply 2, 3, 5, 10, 29, 31, 32, 35, 39, 43 NC Not Connected

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1.4 Absolute Maximum Ratings

Absolute maximum electrical ratings are at 25°C. Absolute Maximum Ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not implied.

1.5 ESD Rating

1.6 General Conditions

Unless otherwise specified, minimum and maximum values are production testing requirements. Typical values are characteristic of the device and are the result of engineering evaluations. They are provided for information purposes only and are not part of the testing requirements. Specifications cover the operating temperature range T A = -40°C to +85°C. Also, unless otherwise specified, all testing is performed with VDD = 5VDC, logic low input voltage is 0VDC and logic high voltage is 5VDC. Parameter Minimum Maximum Unit +5V power supply (VDD) -0.3 7 V Battery Supply - -85 V DGND to FGND Separation -5 +5 V Logic input voltage -0.3 VDD + 0.3 V Logic input to switch output isolation -3 2 0 V Switch open-contact isolation (SW1, SW2, SW3, SW5, SW6) -3 2 0 V Switch open-contact Isolation (SW4) -4 6 5 V Operating relative humidity 5 95 % Operating temperature -40 +110 °C Storage temperature -40 +150 °C ESD Rating (Human Body Model) 1000V

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1.7 Switch Specifications

1.7.1 Break Switches, SW1 and SW2

Parameter Test Conditions Symbol Minimum Typical Maximum Unit Off-State Leakage Current VSW1 (differential) = TLINE to TBA T VSW2 (differential) = RLINE to RBA T All-Off state. +25°C, VSW (differential) = -320V to gnd VSW (differential) = +260V to -60V ISW --1 μA +85° C, VSW (differential) = -330V to gnd VSW (differential) = +270V to -60V -40°C, VSW (differential) = -310V to gnd VSW (differential) = +250V to -60V On Resistance ISW(on) = ±10mA, ±40mA, RBA T and TBA T = -2V +25°C RON - 14.5 - Ω+85°C- 3 1 -40°C1 0 . 5 - On Resistance Matching Per SW1 & SW2 On Resistance test conditions. ΔRON - 0.02 1.0 Ω ON-State Voltage 1 Maximum Differential Voltage (Vmax) ΔVON - - 320 VFoldback Voltage Breakpoint 1 (V1) 60 - - Foldback Voltage Breakpoint 2 (V2)V 1 + 0.5 -- DC current limit 1 (ILIM1) VSW (on) = ±10V , +25°C ISW - 300 mA VSW (on) = ±10V , +85°C 80 DC current limit 2 (ILIM2) I SW 1-- Dynamic current limit (t = <0.5 μs) Break switches on, all other switches off. Apply ±1 kV 10x1000 μs pulse with appropriate protection in place. ISW -2 . 5- A Logic Input to Switch Output Isolation +25° C, OFFx = 0, VSW (TLINE, RLINE) = ±320V ISW 1 μA+85° C, OFFx = 0, VSW (TLINE, RLINE) = ±330V -- -40° C, OFFx = 0, VSW (TLINE, RLINE) = ±310V -- T ransient Immunity 2 dV/dt 1500 2100 - V/ μs 1 Choice of secondary protector should ensure this rating is not exceeded. 2 Applied voltage is 100VP-P square wave at 100Hz.

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1.7.2 Ringing Return Switch, SW3

Parameter Test Conditions Symbol Minimum Typical Maximum Unit Off-State Leakage Current VSW3 (differential) = TLINE to TRINGING All-Off state. +25° C, VSW (differential) = -320V to gnd VSW (differential) = +260V to -60V ISW - 1 μA +85° C, VSW (differential) = -330V to gnd VSW (differential) = +270V to -60V -40° C, VSW (differential) = -310V to gnd VSW (differential) = +250V to -60V On Resistance ISW(on) = ±0mA, ±10mA, +25°C RON - 60 - ΩISW(on) = ±0mA, ±10mA, +85°C 85 100 ISW(on) = ±0mA, ±10mA, -40°C 45 - ON-State Voltage 1 Maximum Differential Voltage (Vmax) ΔVON - - 320 VFoldback Voltage Breakpoint 1 (V1) 200 - - Foldback Voltage Breakpoint 2 (V2)V 1 + 0.5 -- DC current limit 1 (ILIM1) VSW (on) = ±10V , +25°C ISW - 135 mA VSW (on) = ±10V , +85°C 70 85 DC current limit 2 (ILIM2) 1-- Dynamic current limit (t = <0.5 μs) Ringing switches on, all other switches off. Apply ±1kV 10x1000 μs pulse with appropriate protection in place. ISW -2 . 5- A Logic Input to Switch Output Isolation +25°C, OFFx = 0, VSW (TRINGING, TLINE) = ±320V ISW - 1 μA+85°C, OFFx = 0, VSW (TRINGING, TLINE) = ±330V - -40°C, OFFx = 0, VSW (TRINGING, TLINE) = ±310V - T ransient Immunity 2 - dV/dt 1500 2100 - V/ μs 1 This parameter is not tested in production. Choice of secondary protector should ensure this rating is not exceeded. 2 Applied voltage is 100VP-P square wave at 100Hz.

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1.7.3 Ringing Switch, SW4

Parameter Test Conditions Symbol Minimum Typical Maximum Unit Off-State Leakage Current VSW4 (differential) = RLINE to RRINGING All-Off state. +25°C VSW (differential) = -255V to +210V VSW (differential) = +255V to -210V ISW - 1 μA +85° C VSW (differential) = -270V to +210V VSW (differential) = +270V to -210V -40° C VSW (differential) = -245V to +210V VSW (differential) = +245V to -210V On Resistance ISW (on) = ±70mA, ±80mA R ON - 10 15 Ω On Voltage ISW (on) = ±1mA V ON --3 V On-State Leakage Current Inputs set for ringing -Measure ringing generator current to ground. IRINGING -2- m A Steady-State Current 1 Inputs set for ringing mode. ISW - - 150 mA Surge Current 1 Ringing switches on, all other switches off. Apply ±1kV 10x1000 μs pulse with appropriate protection in place. ISW --2 A Release Current SW4 transition from on to off. IRINGING - 300 1000 μA Logic input to switch output isolation +25°C, OFFx = 0, VSW (RRINGING, RLINE) = ±320V ISW - 1 μA+85°C, OFFx = 0, VSW (RRINGING, RLINE) = ±330V - -40°C, OFFx = 0, VSW (RRINGING, RLINE) = ±310V - T ransient Immunity 2 - dV/dt 1500 2100 - V/ μs 1 This parameter is not tested in production. Choice of secondary protector should ensure this rating is not exceeded. 2 Applied voltage is 100VP-P square wave at 100Hz.

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1.7.4 T est Switches, SW5 and SW6

Parameter Test Conditions Symbol Minimum Typical Maximum Unit Off-State Leakage Current VSW1 (differential) = TLINE to TBA T VSW2 (differential) = RLINE to RBA T All-Off state. +25°C, VSW (differential) = -320V to gnd VSW (differential) = +260V to -60V ISW - 1 μA +85° C, VSW (differential) = -330V to gnd VSW (differential) = +270V to -60V -40° C, VSW (differential) = -310V to gnd VSW (differential) = +250V to -60V On Resistance ISW(on) = ±10mA, ±40mA, RBA T and TBA T = -2V +25°C RON - 38 - Ω+85°C4 6 7 0 -40°C2 8 - DC current limit VSW (on) = ±10V , +25°C ISW - 175 mAVSW (on) = ±10V , +85°C 80 110 VSW (on) = ±10V , -40°C - 210 250 Dynamic current limit (t = <0.5 μs) Break switches on, all other switches off. Apply ±1kV 10x1000 μs pulse with appropriate protection in place. ISW -2 . 5- A Logic Input to Switch Output Isolation +25°C, OFFx = 0, VSW (TLINE, RLINE) = ±320V ISW 1 μA+85°C, OFFx = 0, VSW (TLINE, RLINE) = ±330V -- -40°C, OFFx = 0, VSW (TLINE, RLINE) = ±310V -- T ransient Immunity 1 - dV/dt 1500 2100 - V/ μs 1 Applied voltage is 100VP-P square wave at 100Hz.

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1.8 Digital I/O Electrical Specifications

Parameter Test Conditions Symbol Minimum Typical Maximum Unit Input Characteristics Input Voltage, Logic Low (P1-P3, OFFx, CFG) Input voltage falling VIL 0.8 - - V Input Voltage, Logic Low (LA TCHx) 0.6 - - Input voltage, Logic High (P1-P3, OFFx) Input voltage rising VIH -- 2 . 0 Input Voltage, Logic High (CFG) -- 3 . 0 Input Voltage, Logic High (LA TCHx) -- 1 . 1 Input Leakage Current, Logic High (OFFx) VDD = 5.25V , VBA T = -72V , VIH =5 V I IH 15 32 60 μA Input Leakage Current, Logic High (P1-P3, LA TCH x, CFG) VDD = 5.25V , VBA T = -72V , VIH =5 V I IH -- 2 0 μA Input leakage current, Logic Low (P1-P3, LA TCH x, OFFx, CFG) VDD = 5.25V , VBA T = -72V , VIL =0 V I IL -- 2 0 μA Input leakage current, TSDx Logic High VDD = 5.25V , VBA T = -72V , VIH = 2.4V I IH 10 16 30 μA Input leakage current, TSDx Logic low VDD = 5.25V , VBA T = -72V , VIL = 0.4V I IL 10 16 30 μA Output Characteristics Output voltage, TSDx Logic High VDD = 5.25V , VBA T = -72V , ITSD = 10μAV TSD_off 2.4 VDD -V Output voltage, TSDx Logic Low VDD = 5.25V , VBA T = -72V , ITSD = 1mA V TSD_on -0 0 . 4 V

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1.9 Voltage and Power Specifications

1.10 Protection Circuitry Electrical Specifications

Parameter Test Conditions Symbol Minimum Typical Maximum Unit Voltage Requirements VDD - VDD 4.75 5.0 5.25 V VBA T 1 - VBA T -19 -48 -72 V 1VBA T is used only for internal protection circuitry. If VBA T rises above-10 V , the device will enter the all-off state and will remain in the all-off state until the battery drops below approximately -15V . Power Specifications Power consumption VDD = 5V , VBA T = -48V , VIH = 2.4V , VIL = 0.4V , Measure IDD and IBA T mWIdle/T alk State P -- 15 3 All-Off State 2 -- 7.5 3 Ringing or T est Access State - - 20 3 VDD Current VDD = 5V , VBA T = -48V , VIH = 2.4V , VIL = 0.4V mAIdle/T alk State IDD - 1.6 3 3.0 All-Off State - 0.75 3 1.5 Ringing or T est Access State - 1.8/1.5 3 4.0 VBA T Current VDD = 5V , VBA T = -48V , VIH = 2.4V , VIL = 0.4V , All States IBA T -4 1 0 μA 2 Controlled via OFFx pins. 3 Combined power or current of both channels, both channels in the same state. T ypical values from simulation. Parameter Conditions Symbol Minimum Typical Maximum Unit Protection Diode Bridge Forward Voltage drop, continuous current (50/60 Hz) Apply ± DC current limit of break switches V F -2 . 1 3 . 0 V Forward Voltage drop, surge current Apply ± dynamic current limit of break switches VF -5- Temperature Shutdown Specifications 1 Shutdown activation temperature Not production tested - limits are guaranteed by design and Quality Control sampling audits. T TSD_on 110 125 150 °C Shutdown circuit hysteresis TTSD_off 10 - 25 °C Loss of Battery Detector Threshold Loss of Battery -19 -10 -5 VResumption of Battery =19 -15 -5 1 T emperature shutdown flag (TSDx) will be high during normal operation and low during temperature shutdown state.

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1.11 Truth Tables

1.11.1 Operating States: CFG=0

1.11.2 Operating States: CFG=1

1 Break

Idle/T alk 0 0 0 1 ON OFF OFF T e s t 0011 OFF OFF ON R i n g i n g 0101 OFF ON OFF T e s t / M o n i t o r 0111 O N O F F O N I d l e / T a l k 1001 O N O F F O F F T e s t / M o n i t o r 1011 O N O F F O N R i n g i n g 1101 O F F O N O F F T e s t R i n g i n g 1111 OFF ON ON A l l - O f f xxx 02 OFF OFF OFF 1 P1, P2, and P3 data input values are directed to a given channel when the respective LA TCHx logic signal is set to “0.” OFFx is a per-channel control. 2 A “0” on OFFx resets the CPC75282, the device will remain in the All-Off state until OFFx is returned to “1” and the next LA TCHx signal is applied. 3 CFG is fixed at DGND; if CFG switches states when VDD is applied, the change will be recognized by a given channel after a LA TCH low transition is applied to that channel. State P3 P2 P1 OFFx Idle/T alk 0 0 0 1 ON OFF OFF T e s t 0011 OFF OFF ON R i n g i n g 0101 OFF ON OFF A l l - O f f 0111 O F F O F F O F F I d l e / T a l k 1001 O N O F F O F F T e s t / M o n i t o r 1011 O N O F F O N R i n g i n g 1101 O F F O N O F F T e s t R i n g i n g 1111 OFF ON ON A l l - O f f xxx 02 OFF OFF OFF 1 P1, P2, and P3 data input values are directed to a given channel when the respective LA TCHx logic signal is set to “0.” OFFx is a per-channel control. 2 A “0” on OFFx resets the CPC75282, the device will remain in the All-Off state until OFFx is returned to “1” and the next LA TCHx signal is applied. 3 CFG is fixed at vDD; if CFG switches states when VDD is applied, the change will be recognized by a given channel after a LA TCH low transition is applied to that channel.

12 www.clare.com R00D 2. Functional Description

2.1 Introduction

The CPC75282 Dual LCAS device has six operating states:

• Idle/Talk: Break switches SW1 and SW2 closed, ringing switches SW3 and SW4 open, and test switches SW5 and SW6 open.
• Ringing: Break switches SW1 and SW2 open, ringing switches SW3 and SW4 closed, and test switches SW5 and SW6 open.
• Test: Break switches SW1 and SW2 open, ringing switches SW3 and SW4 open, and loop test switches SW5 and SW6 closed.
• Test/Monitor: Break switches SW1 and SW2 closed, ringing switches SW3 and SW4 open, and test switches SW5 and SW6 closed.
• Test Ringing: Break switches SW1 and SW2 open, ringing switches SW3 and SW4 closed, and test switches SW5 and SW6 closed.
• All-off: Break switches SW1 and SW2 open, ringing switches SW3 and SW4 open, and test switches SW5 and SW6 open. See “Truth Tables” on page 11 for more information. The CPC75282 offers break-before-make and make-before-break switching from the ringing state to the idle/talk state with simple logic input control. Solid-state switch construction means no impulse noise is generated when switching during ring cadence or ring trip, eliminating the need for external zero-cross switching circuitry. State control is via simple logic input so no additional driver circuitry is required. The linear break switches, SW1 and SW2, have exceptionally low R ON and excellent matching characteristics. The ringing switch, SW4, has a minimum open contact breakdown voltage of 465V at +25°C sufficiently high with proper protection to prevent breakdown in the presence of a transient fault condition (i.e., passing the transient on to the ringing generator). Integrated into the CPC75282 is an over-voltage clamping circuit, active current limiting, and a thermal shutdown mechanism to provide protection for the SLIC during a fault condition. Positive and negative lightning surge currents are reduced by the current limiting circuitry and hazardous potentials are diverted away from the SLIC via the protection diode bridge. Power-cross potentials are also reduced by the current limiting and thermal shutdown circuits. To protect the CPC75282 from an over-voltage fault condition, use of a secondary protector is required. The secondary protector must limit the voltage seen at the tip and ring terminals to a level below the maximum breakdown voltage of the switches. To minimize the stress on the solid-state contacts, use of a foldback or crowbar type secondary protector is highly recommended. With proper selection of the secondary protector, a line card using the CPC75282 will meet all relevant ITU, LSSGR, TIA/EIA and IEC protection requirements. The CPC75282 operates from a single +5V supply. This gives the device extremely low idle and active power consumption with virtually any range of battery voltage. The battery voltage used by the CPC75282 has a two-fold function. For protection purpose it is used as a fault condition current source during a negative lightning event. Second, it is used as a reference so that in the event of battery voltage loss, the CPC75282 will enter the All-Off state.

2.2 Under Voltage Switch Lock-Out Circuitry

Smart logic in the CPC75282 now provides for switch state control during both power up and power loss transitions. An internal detector is used to evaluate the V DD supply to determine when to de-assert the under-voltage switch lock-out circuitry with a rising VDD and when to assert the under-voltage switch lock-out circuitry with a falling VDD. Any time unsatisfactory low VDD conditions exist, the lock-out circuit overrides user switch control by blocking the information at the external input pins, and conditioning internal switch commands to the All-Off state. Upon restoration of V DD, the switches will remain in the All-Off state until the LATCHx input is pulled low. The rising VDD lock-out release threshold is internally set to ensure all internal logic is properly biased and functional before accepting external switch commands from the input to control the switch states. For a falling V DD event, the lock-out threshold is set to assure proper logic and switch behavior up to the moment the switches are forced off and external inputs are suppressed.

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2.3 Switch Logic

2.3.1 Start-up

The CPC75282 uses smart logic to monitor the VDD supply. Any time the VDD is below an internally set threshold, the smart logic places the control logic to the all-off state until the LATCHx input is pulled low. Prior to the assertion of a logic low at the LATCHx pin, the switch control inputs must be properly conditioned.

2.3.2 Switch Timing

When switching from the ringing state to the idle/talk state, the CPC75282 provides the ability to control the release timing of the ringing switches, SW3 and SW4, relative to the state of the switches, SW1 and SW2, using simple logic inputs. The two available techniques are referred to as make-before-break and break-before-make operation. When the break switch contacts of SW1 and SW2 are closed (made) before the ringing switch contacts of SW3 and SW4 are opened (broken), this is referred to as make-before-break operation. Break-before-make operation occurs when the ringing contacts of SW3 and SW4 are opened (broken) before the switch contacts of SW1 and SW2 are closed (made). With the CPC75282, make-before-break and break-before-make operations can easily be accomplished by applying the proper sequence of logic-level inputs to the device. The logic sequences for either mode of operation are given in “Make-Before-Break Operation Logic Table (Ringing to Talk Transition)” on page 13 and “Break-Before-Make Ringing to Talk Transition Logic Sequence CPC7592xA/B” on page 14. Logic states and explanations are shown in “Truth Tables” on page 11.

2.3.3 Make-Before-Break Operation

To use make-before-break operation, change the logic inputs from the ringing state directly to the idle/talk state. Application of the idle/talk state opens the ringing return switch, SW3, as the break switches, SW1 and SW2, close. The ringing switch, SW4, remains closed until the next zero-crossing of the ringing current. While in the make-before-break state, ringing potentials in excess of the CPC75282 protection circuitry thresholds will be diverted away from the SLIC. 2.3.4: Make-Before-Break Operation Logic T able (Ringing to T alk T ransition) State (CFG=0, P3=0) P2 P1 LATCHx OFFx Timing Break Switches 1x & 2x Ringing Return Switch Ringing Switch Test Switches 5x & 6x Ringing 1 0 -O f f On On Off Make- before- break SW4 waiting for next zero-current crossing to turn off. Maximum time is one-half of the ringing cycle. In this transition state current limited by the DC break switch current limit value will be sourced from the ring node of the SLIC. On Off On Off Idle/T alk 0 0 Zero-cross current has occurred On Off Off Off

14 www.clare.com R00D Break-before-make operation occurs when the ringing switches open before the break switches, SW1 and SW2, close. 2.3.5: Break-Before-Make Ringing to T alk T ransition Logic Sequence CPC7592xA/B

2.3.6 Break -Before- Make Operation

Break-before-make operation can be achieved using OFFx to disable all of the switches when pulled to a logic low. Although logically disabled, an active (closed) ringing switch, SW4, will remain closed until the next zero crossing current event. 1. Pull OFF x to a logic low to end the ringing state. This opens the ringing return switch, SW3, and prevents any other switches from closing. 2. Keep OFF x low for at least one-half the duration of the ringing cycle period to allow sufficient time for a zero crossing current event to occur and for the circuit to enter the break-before-make state. 3. During the OFF x low period, set the P1, P2, and P3 inputs to the idle/talk state. 4. Release OFF x , allowing the internal pull-up to activate the break switches.

2.4 Data Latch

The CPC75282 has integrated transparent data latches. The latch enable operation is controlled by logic input levels at the LATCH x pin. Data input to the latch is via the input pins P1, P2, and P3 while the outputs of the data latch are internal nodes used for state control. When the latch enable control pin is at a logic 0 the data latch is transparent and the input control signals flow directly through the data latch to the state control circuitry. A change in input will be reflected by a change in the switch states. Whenever the latch enable control pin is at logic 1, the data latch is active and data is locked. Subsequent changes to the input controls P1, P2, and P3 will not result in a change to the control logic or affect the existing switch states. The switches will remain in the state they were in when the LATCH x changes from logic 0 to logic 1, and will not respond to changes in input as long as the LATCHx is at logic 1. However, neither the TSDx nor the OFFx are affected by the latch function. Since internal thermal shutdown control and external OFFx control is not affected by the state of the latch enable input, TSDx and OFFx will override state control.

2.5 TSD Pin Description

The TSDx pins are bidirectional I/O structures with internal pull-up resistors sourced from VDD. As outputs, these pins indicate the status of the thermal shutdown circuitry for the associated channels. Typically, during normal operation, these pins will be pulled up to V DD , but, under fault conditions that create excess thermal loading, the channels will enter thermal shutdown and a logic low will be output. As inputs, the TSDx pins are utilized to place the channel into the All-Off state by simply pulling the input low. For applications using low-voltage logic devices (lower than VDD), Clare recommends the use of an open-collector or an open-drain type output to control TSDx. This avoids sinking the TSDx pull up bias current to ground during normal operation when the All-Off state is not required. If TSDx is set to a logic 1 or State CFG=0, P3=0 P2 P1 LATCHx OFFx Timing Break Switches 1x & 2x Ringing Return Switch Ringing Switch Test Switches 5x & 6x Ringing 1 0 1-O f f On On Off All-Off 1 1 0 Hold this state for at least one-half of the ringing cycle. SW4 waiting for zero current to turn off. Off Off On Off All-Off 1 1 0 Zero current has occurred. SW4 has opened O f fO f fO f fO f f T alk 0 0 1 Break switches close. On Off Off Off

R00D www.clare.com 15 tied to VCC, the channel just ignores this input, and still enters the thermal shutdown state at high temperature.

2.6 Ringing Switch Zero-Cross Current Turn Off

After the application of a logic input to turn SW4 off, the ringing switch is designed to delay the change in state until the next zero-crossing. Once on, the switch requires a zero-current cross to turn off, and therefore should not be used to switch a pure DC signal. The switch will remain in the on state no matter the logic input until the next zero crossing. These switching characteristics will reduce and possibly eliminate overall system impulse noise normally associated with ringing switches. See Clare’s application note, AN-144, Impulse Noise Benefits of Line Card Access Switches, for more information. The attributes of ringing switch, SW4, may make it possible to eliminate the need for a zero-cross switching scheme. A minimum impedance of 300Ω in series with the ringing generator is recommended.

2.7 Power Supplies

Both a +5V supply and battery voltage are connected to the CPC75282. Switch state control is powered exclusively by the +5V supply. As a result, the CPC75282 exhibits extremely low power consumption during active and idle states. Although battery power is not used for switch control, it is required to supply current during negative overvoltage fault conditions at tip and ring.

2.8 Battery Voltage Monitor

The CPC75282 also uses the V BAT voltage to monitor battery voltage. If system battery voltage is lost, both channels of the CPC75282 immediately enter the All-Off state. It remains in this state until the battery voltage is restored. The device also enters the All-Off state if the battery voltage rises more positive than about –10V with respect to ground and remains in the All-Off state until the battery voltage drops below approximately –15V with respect to ground. This battery monitor feature draws a small current from the battery (less than 1μA typical) and will add slightly to the device’s overall power dissipation.

2.9 Protection

2.9.1 Diode Bridge

Both channels of the CPC75282 use a combination of current limited break switches, a diode bridge, and a thermal shutdown mechanism to protect the SLIC device or other associated circuitry from damage during line transient events, such as lightning. During a positive transient condition, the fault current is conducted through the diode bridge to ground via F GND. Voltage is clamped to a diode drop above ground. Negative lightning is directed to battery via steering diodes in the diode bridge. For power induction or power-cross fault conditions, the positive cycle of the transient is clamped to a diode drop above ground and the fault current directed to ground. The negative cycle of the transient is steered to battery. Fault currents are limited by the current-limit circuit.

2.9.2 Current Limiting function

If a lightning strike transient occurs when the device is in the Idle/Talk state, the current is passed along the line to the integrated protection circuitry, and restricted by the dynamic current limit response of the active switches. During the Idle/Talk state, when a 1000V 10x1000μs lightning pulse (GR-1089-CORE lightning) is applied to the line though a properly clamped external protector, the current seen at T LINE and RLINE will be a pulse with a typical magnitude of 2.5A and a duration less than 0.5μs. If a power-cross fault occurs with the device in the Idle/Talk state, the current is passed though break switches, SW1 and SW2, on to the integrated protection circuit, but is limited by the DC current limit response of the two break switches. The DC current limit is dependent on the switch differential voltage, as shown in “Figure 2: Switches 1-3” on page 17. Note that the current limit circuitry has a negative temperature coefficient. As a result, if the device is subjected to extended heating due to a power cross fault condition, the measured current at T LINE and RLINE will decrease as the device temperature increases. If the device temperature rises sufficiently, the temperature shutdown mechanism will activate and the device will enter the All-Off state.

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2.10 Thermal Shutdown

The thermal shutdown mechanism activates when the device die temperature reaches a minimum of 110°C, placing the device in the All-Off state regardless of logic input. During thermal shutdown events the T SDx pin will output a logic low with a nominal 0V level. A logic high is output from the TSDx pin during normal operation with a typical output level equal to VDD. If presented with a short duration transient, such as a lightning event, the thermal shutdown feature will typically not activate. But in an extended power-cross event, the device temperature will rise and the thermal shutdown mechanism will activate forcing the switches to the All-Off state. At this point the current measured into T LINE or RLINE will drop to zero. Once the device enters thermal shutdown, it will remain in the All-Off state until the temperature of the device drops below the de-activation level of the thermal shutdown circuit. This permits the device to autonomously return to normal operation. If the transient has not passed, current will again flow up to the value allowed by the dynamic DC current limiting of the switches and heating will resume, reactivating the thermal shutdown mechanism. This cycle of entering and exiting the thermal shutdown mode will continue as long as the fault condition persists. If the magnitude of the fault condition is great enough, the external secondary protector will activate, shunting the fault current to ground.

2.11 External Protection Elements

The CPC75282 requires only over-voltage secondary protection on the loop side of the device. The integrated protection feature described above negates the need for additional external protection on the SLIC side. The secondary protector must limit voltage transients to levels that do not exceed the breakdown voltage or input-output isolation barrier of the CPC75282. A foldback or crowbar type protector is recommended to minimize stresses on the CPC75282. Consult Clare’s application note, AN-100, “Designing Surge and Power Fault Protection Circuits for Solid State Subscriber Line Interfaces,” for equations related to the specifications of external secondary protectors, fused resistors, and PTCs.

R00D www.clare.com 17 3. Typical Performance Characteristics

3.1 Figure 1: Protection Circuit

3.2 Figure 2: Switches 1-3

3.3 Figure 3: Switch 4

3.4 Figure 4: Switches 5-6

(of Break Switches) DC Current Limit (Break Switches) VBAT <1μA VBAT-3 ISW VSW VMAX ILIM1 -ILIM1 2/3 RON -ILIM2 ILIM2-VMAX -V2 -V1 -1.5 V2V11.5 RON -VOS +VOS -V +V RON +V-V ILIMIT ILIMIT RON RON -1.5V 1.5V 2/3 RON 2/3 RON

18 www.clare.com R00D 4. Manufacturing Information

4.1 Mechanical Dimensions

4.1.1 Package Dimensions

4.1.2 T ape & Reel Specification

44-Pin TQFP Package Recommended PCB Land Pattern Dimensions mm (inches)

1.20 Max

(0.047 Max) 1.00 ± 0.05 (0.039 ± 0.002) 0.05 Min - 0.15 Max (0.002 Min - 0.006 Max) 0.80 (0.031) 11.50 (0.453) 0.60 ± 0.15 (0.024 ± 0.006)

1.00 Ref

(0.039) Ref 0.80 (0.031) 0.55 (0.022) 1.45 (0.057) 11.50 (0.453) Pin 44 Pin 1 0.37 ± 0.07 (0.014 ± 0.003) 10.00 ± 0.10 (0.394 ± 0.004) 12.00 ± 0.20 (0.472 ± 0.008) 12.00 ± 0.20 (0.472 ± 0.008) 10.00 ± 0.10 (0.394 ± 0.004) Top Cover Tape Thickness

0.102 MAX

(0.004 MAX) 330.2 DIA. (13.00 DIA) Embossed Carrier Embossment A0=12.35 (0.486) W=24.00 0.3 (0.94 0.01) Dimensions mm (inches) B0=12.35 (0.486) 9.4 (0.37) 11.5 (0.453) (0.63) 9.2 (0.36) 1.0 (0.039) K1=1.35 (0.053) K0=1.85 (0.073)

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4.2 Soldering

For proper assembly, this component must be processed in accordance with the current revision of IPC/JEDEC standard J-STD-020. Failure to follow the recommended guidelines may cause permanent damage to the device resulting in impaired performance and/or a reduced lifetime expectancy.

4.3 Washing

Clare does not recommend ultrasonic cleaning of this part. RoHS 2002/95/EC e3Pb Specifications: DS-CPC75282 - R00D © Copyright 2009, Clare, Inc. All rights reserved. Printed in USA. 8/4/09 For additional information please visit www.clare.com Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set forth in Clare’s Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty relating to its products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of Clare’s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its product s at any time without notice.