CPC7220 CLARE | Alldatasheet
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www.clare.comDS-CPC7220-R00H 1 CPC7220 Low Charge Injection 8-Channel High Voltage Analog Switch PRELIMINARY RoHS 2002/95/EC e3Pb Features Description The CPC7220 is a low charge injection 8-channel high-voltage analog switch integrated circuit (IC) for use in applications requiring high voltage switching. Control of the high voltage switching is via low voltage TTL logic level compatible inputs for direct connectivity to the system controller. Switch manipulation is managed by an 8-bit serial to parallel shift register whose outputs are buffered and stored by an 8-bit transparent latch. Level shifters buffer the latch outputs and operate the high voltage switches. Because the CPC7220 is capable of switching high load voltages and has a flexible load voltage range, e.g. V PP/VNN : +40V/-160V or +100V/-100V, it is well suited for many medical and industrial applications such as medical ultrasound imaging, printers, and industrial measurement equipment. Construction of the high voltage switches using Clare's reliable BCDMOS process technology on SOI (Silicon On Insulator) allow the switches to be organized as solid state switches with direct gate drive. Processed with BCDMOS on SOI (Silicon On Insulator) DC to 10MHz analog signal frequency Surface mount package available Low quiescent power dissipation (< 1µA typical) Output on-resistance typically 20Ω TTL I/O's for 3.3V interface Adjustable high voltage supplies
Ordering Information
Applications
Ultrasound imaging Printers Industrial controls and measurement CLK D CL LE CL D LE CL D LE CL D LE CL D LE CL D LE CL D LE CL D LE SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 DIN DOUT CL LE VNNVPP SR0 SR7 SR1 SR2 SR3 SR4 SR5 SR6 LS0 LS7 LS1 LS2 LS3 LS4 LS5 LS6 LATCHESSHIFT REGISTER SWITCHESLEVEL SHIFTERS Part Number Description CPC7220W 28-Lead PLCC in T ubes (37/T ube) CPC7220WTR 28-Lead PLCC T ape & Reel (500/Reel) CPC7220K 48-Lead LQFP in T rays (250/T ray) CPC7220KTR 48-Lead LQFP T ape & Reel (1000/Reel)
www.clare.com2 CPC7220 R00H PRELIMINARY 25 19 24 23 22 21 20 5 116789 1 0 CPC7220 Name Description
1 SW3 SW3 output
2 SW3 SW3 output
3 SW2 SW2 output
4 SW2 SW2 output
5 SW1 SW1 output
6 SW1 SW1 output
7 SW0 SW0 output
8 SW0 SW0 output
PP Switch positive high voltage supply
12 V NN Switch negative high voltage supply
13 GND Ground
DD Logic positive voltage supply
16 D IN Serial data input
17 CLK Clock input, positive edge trigger
18 LE Latch enable, active low
19 CL Latch clear, active high clears latches and opens switches
21 SW7 SW7 output
22 SW7 SW7 output
23 SW6 SW6 output
24 SW6 SW6 output
25 SW5 SW5 output
26 SW5 SW5 output
27 SW4 SW4 output
28 SW4 SW4 output
9, 11, 15 N/C No Connection
www.clare.com 3R00H PRELIMINARY CPC7220 Name Description
1 SW5 SW5 output
2 N/C No Connection
3 SW4 SW4 output
4 N/C No Connection
5 SW4 SW4 output
6 N/C No Connection
7 N/C No Connection
8 SW3 SW3 output
9 N/C No Connection
10 SW3 SW3 output
11 N/C No Connection
12 SW2 SW2 output
13 N/C No Connection
14 SW2 SW2 output
15 N/C No Connection
16 SW1 SW1 output
17 N/C No Connection
18 SW1 SW1 output
19 N/C No Connection
20 SW0 SW0 output
21 N/C No Connection
22 SW0 SW0 output
23 N/C No Connection
PP Switch positive high voltage supply
25 V NN Switch negative high voltage supply
26 N/C No Connection
27 N/C No Connection
28 GND Ground
DD Logic positive voltage supply
30 N/C No Connection
31 N/C No Connection
32 N/C No Connection
34 CLK Clock input, positive edge trigger
35 LE Latch enable, active low
36 CL Latch clear, active high clears latches and opens switches
38 N/C No Connection
39 SW7 SW7 output
40 N/C No Connection
41 SW7 SW7 output
42 N/C No Connection
43 SW6 SW6 output
44 N/C No Connection
45 SW6 SW6 output
46 N/C No Connection
47 SW5 SW5 output
48 N/C No Connection
www.clare.com4 CPC7220 R00H PRELIMINARY Absolute Maximum Ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not implied. Absolute Maximum Ratings (@ 25˚ C) Parameter Ratings Units VDD logic power supply voltage -0.5 to +6 V VPP - VNN supply voltage 220 V VPP positive high voltage supply -0.5 to V NN +200 V VNN negative high voltage supply +0.5 to V PP -200 V Logic input voltages -0.5 to V DD +0.3 V Analog signal range V NN to VPP - Peak analog signal current/channel 1 A Power dissipation 1.2 W Storage T emperature -60 to +150 °C Parameter Symbol Value Logic power supply voltage 1,3 VDD 4.5V to 6V Positive high voltage supply 1,3 VPP 40V to VNN + 200V Negative high voltage supply 1,3 VNN -40V to -160V Analog signal voltage peak to peak 2 VSIG VNN + 10V to VPP -10V Operating temperature T A 0ºC to 70ºC NOTES: 1 Power up/down sequence is arbitrary except GND must be powered-up fi rst and powered-down last. 2 VSIG must be VNN ≤ VSIG ≤ VPP or fl oating during power up/down transition. 3 Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1msec. Operating Conditions
www.clare.com 5R00H PRELIMINARY Parameter Symbol Test Conditions 0ºC +25ºC +70ºC Unitsmin max min typ max min max Small Signal Switch On-resistance R ONS VPP = 40V , VNN = -160V ISIG = 5mA - 30 - 26 38 - 48 Ω ISIG = 200mA - 25 - 22 27 - 32 VPP = 100V , VNN = -100V ISIG = 5mA - 25 - 22 27 - 33 ISIG = 200mA - 18 - 18 24 - 27 VPP = 160V , VNN = -40V ISIG = 5mA - 23 - 20 25 - 30 ISIG = 200mA - 22 - 16 25 - 27 Small Signal Switch On-resistance Matching ΔRONS ISW = 5mA, VPP = 100V , VNN = -100V - 20 - 5 20 - 20 % Large Signal Switch On-resistance R ONL VSIG = VPP - 10V , ISIG = 0.8A - - - 15 - - - Ω Switch Off Leakage Per Switch I SOL VSIG = VPP - 10V and VNN + 10V - 5 - 0.4 10 - 15 µA DC Offset Switch Off - R L = 100KΩ - 100 - 0 100 - 100 mV DC Offset Switch On - R L = 100KΩ - 100 - 0 100 - 100 mV VPP Quiescent Supply Current I PPQ ALL SWs OFF - - - 0.1 10 - - µAALL SWs ON ISW = 5mA VNN Quiescent Supply Current I NNQ ALL SWs OFF - - - -0.1 -10 - - µAALL SWs ON ISW = 5mA Switch Output Peak Current - V SIG duty cycle 0.1% - - - - 0.8 - - A Output Switch Frequency f SW Duty Cycle = 50% - - - - 50 - - KHz VPP Operating Supply Current I PP VPP = 40V , VNN = -160V 50kHz Output Switching Frequency with no load - 6.5 - - 7 - 8 mAVPP = 100V , VNN Operating Supply Current I NN VPP = 160V , VDD Average Supply Current I DD fCLK = 5MHz, VDD = 5V - 4 - - 4 - 4 mA VDD Quiescent Supply Current I DDQ - - 10 - 1 10 - 10 µA DOUT Source Capability V OH IOUT = -400µA - - VDD -0.7 -- - - V DOUT Sink Capability V OL IOUT = +400µA - - - - 0.7 - - V Logic Input Capacitance C IN - 10 - - 10 - 10 pF Logic Input High V IH 4.75V < VDD < 5.25V 2 - 2 - - 2 - V Electrical Characteristcs DC Characteristics (over recommended operating conditions unless otherwise noted)
www.clare.com6 CPC7220 R00H PRELIMINARY Electrical Characteristcs AC Characteristics (over recommended operating conditions unless otherwise noted) Parameter Symbol Test Conditions 0ºC +25ºC +70ºC Unitsmin max min typ max min max Set Up Time before LE rises t SD 150 - 150 - - 150 - ns Time Width of LE t WLE 150 - 150 - - 150 - ns Clock Delay time to Data Out t DO - 150 - - 150 - 150 ns Time Width of CL t WCL 150 - 150 - - 150 - ns Set Up Time Data to Clock t SU 15 - 15 8 - 20 - ns Hold Time Data from Clock t H 35 - 35 - - 35 - ns Clock Freq f CLK 50% duty cycle fDATA = fCLK/2 - 5 - - 5 - 5 MHz Clock Rise and Fall Times t r, tf - 50 - - 50 - 50 ns T urn On Time t ON VSIG = VPP -10V , RL = 10KΩ -5 - - 5 - 5 µ sT urn Off Time t OFF Maximum VSIG Slew Rate dv/dt VPP = 160V , VNN = -40V - 20 - - 20 - 20 V/nsVPP = 100V , VNN = -100V VPP = 40V , VNN = -160V Off Isolation KO f = 5MHz, 1KΩ/15pF load -30 - -30 -33 - -30 - dBf = 5MHz, 50Ω load -58 - -58 - - -58 - Switch Crosstalk K CR f = 5MHz, 50Ω load -60 - -60 - - -60 - dB Output Switch Isolation Diode Current IID 300ns Pulse Width, 2.0% Duty Cycle 300 300 300 mA Off Capacitance SW to GND C SG(OFF) 0V , 1MHz 5 17 5 21 25 5 20 pF On Capacitance SW to GND C SG(ON) 0V , 1MHz 25 40 20 30 40 25 50 pF Output Voltage Spike +VSPK VPP = 40V , VNN = -160V , RL = 50Ω - - - - 150 - - mV -VSPK +VSPK VPP = 100V , VNN = -100V , RL = 50Ω-VSPK +VSPK VPP = 160V , VNN = -40V , RL = 50Ω-VSPK Charge Injection Q V PP = 100V , VNN = -100V , VSIG = 0V - 880 - pC
www.clare.com 7R00H PRELIMINARY Logic Timing Waveforms DN-1 DN DN+1 50% 50% 50%50% DIN LE tWLE tSD 50% 50%CLK tSU tHtDO 50%DOUT tOFF tON 90% 10% OFF ON CL 50% 50% tWCL VOUT (TYP)
www.clare.com8 CPC7220 R00H PRELIMINARY CPC7220 Description The CPC7220 takes a serial stream of input data along with a synchronous clock signal. As the clock transits from low to high, the data at the input of each shift register is shifted through from SR(n) to SR(n+1). A high data bit, a "1," represents an ON switch; a low data bit, a "0," represents an OFF switch. Data is input and shifted through the internal shift register until all eight shift register positions, SR0 through SR7, are in the desired state. D IN: The data-in line presents data bits to the CPC7220 to be shifted through the internal shift register. CLK: The clock signal's rising edge is associated only with shifting data into and through the shift register. CL: The clear line overrides all other inputs. When CL is high, the shift register is cleared to all 0s and all latches are set low, which causes all output switches to be turned OFF immediately. When CL is low, all output switches remain in whatever state they are in, ON or OFF , in response to CLK, latch inputs, and the LE signal. LE: latch enable controls the state of the latches and thus the state of the eight switches. If LE is high, then the latches do not change states, but retain their most recent status: either ON or OFF . With LE high, input data and CLK have no effect on the state of the output switches. If LE is low, then all latch outputs and their switch states follow the inputs from the shift register. LE is overridden by CL: no matter what state LE is in, CL clears the latches. See table on page 10. D OUT: The data-out pin is the output of SR7. After eight clock pulses, the first bit of eight input data bits is shifted to SR7 and appears on D OUT. SW0 - SW7: The CPC7220 provides eight high- voltage SPST output switches with a typical on- resistance of 20Ω. The two connections of each switch are not polarity-sensitive. V PP and VNN: Voltage inputs to the level shifters for each switch channel that translate the voltage level of the latch output signals to an appropriate level for the voltages being switched. The high-voltage output switches are turned on and off in response to the data sent into the latches from the shift register: data 0 turns a switch OFF , data 1 turns a switch ON. Two or more CPC7220 devices can be cascaded to form an n-switch arrangement. The D OUT pin of the first is connected to the DIN pin of the next in the series. All devices are connected to the same clock (CLK) signal. LE of all devices would normally be connected, as would CL, but this is not necessary. The first data bit applied to D IN of the CPC7220, whether it's a single device or several cascaded devices, ripples through to the last switch output in line after the application of a full clocking sequence of 8 clock pulses per CPC7220. Setting the serial I/O device to output the most significant bit (MSB) first, results in the MSB appearing on SW7 of the last device in line after a full clocking sequence. CL DIN CLK LE SW0 SW7 SW0 SW7 SW0 SW7 DOUT LE CL DIN CLK DOUT LE CL DIN CLK DOUT LE CL DIN CLK CPC7220 CPC7220 CPC7220
www.clare.com 9R00H PRELIMINARY Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the L → H transition CLK. 3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flows through the latch. 4. D OUT is high when switch 7 is on. 5. Shift register clocking has no effect on the switch states if LE is H. 6. The clear input overrides all other inputs. D0 D1 D2 D3 D4 D5 D6 D7 LE CL SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 L L L OFF HL L O N L L L OFF HL L O N L L L OFF HL L O N L L L OFF HL L O N L L L OFF HL L O N L L L OFF HL L O N L L L OFF HL L O N L L L OFF HLL O N X X X X X X X X H L HOLD PREVIOUS STATE X X X X X X X X X H OFF OFF OFF OFF OFF OFF OFF OFF Truth Table
www.clare.com10 CPC7220 R00H PRELIMINARY Manufacturing Information Soldering For proper assembly, the component must be processed in accordance with the current revision of IPC/JEDEC standard J-STD-020. Failure to follow the recommended guidelines may cause permanent damage to the device resulting in impaired performance and/or a reduced lifetime expectancy. Washing Clare does not recommend ultrasonic cleaning or the use of chlorinated solvents. RoHS 2002/95/EC e3Pb 0.660/0.813 (0.026/0.032) 4.191/4.572 (0.165/0.180) 2.286/3.048 (0.090/0.120) 0.330/0.533 (0.013/0.021)
0.020 MIN
(0.004 MIN) 28-Pin PLCC Package Recommended PCB Land Pattern Dimensions mm(Max)/mm(Min) (inches(Max/inches(Min)) 10.90 (0.429) 10.90 (0.429) 0.65 (0.026) 2.40 (0.094) 1.27 (0.050)
1.27 TYP
(0.050 TYP) 12.319/12.573 (0.485/0.495) 11.430/11.582 (0.450/0.456) 12.319/12.573 (0.485/0.495) 11.430/11.582 (0.4500.456) Pin 1 MECHANICAL DIMENSIONS 48-Pin LQFP Package Dimensions mm (inches) 0.60, +0.15/-0.10
1.60 Max
(0.063Max) 1.40 ± 0.05 (0.055 ± 0.002) 0.05 Min / 0.15 Max (0.002 Min - 0.006 Max) 0.50 (0.020) Recommended PCB Land Pattern 8.50 (0.335) 0.50 (0.020) 0.30 (0.012) 1.45 (0.057) 8.50 (0.335) Pin 48 Pin 1 0.22 ± 0.05 (0.009 ± 0.002) 7.00 ± 0.10 (0.276 ± 0.004) 9.00 ± 0.20 (0.354 ± 0.008) 9.00 ± 0.20 (0.354 ± 0.008) 7.00 ± 0.10 (0.276 ± 0.004)
Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Exce pt as set forth in Clare’s Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of Clare’s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice. Specification: DS-CPC7220-R00H ©Copyright 2009, Clare, Inc. All rights reserved. Printed in USA. 4/20/09 For additional information please visit our website at: www.clare.com PRELIMINARY CPC7220