CP555 CENTRAL | Alldatasheet
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Semiconductor Corp. TM PROCESS CP555 Small Signal Transistor PNP - Saturated Switch Transistor Chip PRINCIPAL DEVICE TYPES CMPT3640 CMPT4209 2N4209 Process EPITAXIAL PLANAR Die Size 15 X 10 MILS Die Thickness 8 MILS Base Bonding Pad Area 3.6 X 2.4 MILS Emitter Bonding Pad Area 3.6 X 2.4 MILS Top Side Metalization Al - 20,000Å Back Side Metalization Au - 15,000Å PROCESS DETAILS
145 Adams Avenue
Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com BACKSIDE COLLECTOR GEOMETRY R2 (1-August 2002) GROSS DIE PER 4 INCH WAFER 75,330
Semiconductor Corp. TM PROCESS CP555 Typical Electrical Characteristics Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com R2 (1-August 2002)